library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity display is
    Port ( clk_i : in  STD_LOGIC;
           rst_i : in  STD_LOGIC;
           digit_i : in  STD_LOGIC_VECTOR (31 downto 0);
           led7_an_o : out  STD_LOGIC_VECTOR (3 downto 0);
           led7_seg_o : out  STD_LOGIC_VECTOR (7 downto 0));
end display;

architecture Behavioral of display is
	signal active_led7_an: std_logic_vector (3 downto 0) := "1111";
	--signal active_led7_seg: std_logic_vector (3 downto 0); --abcdefg dp
begin
process (clk_i, rst_i, digit_i, active_led7_an)
  begin
	if (rst_i='1') then
		led7_an_o<="0000";
		led7_seg_o<="00000000";
	elsif (rising_edge(clk_i)) then
		case active_led7_an is
			when "0000" => active_led7_an <= "0111";
			when "0111" => active_led7_an <= "1011";
			when "1011" => active_led7_an <= "1101";
			when "1101" => active_led7_an <= "1110";
			when "1110" => active_led7_an <= "0111";
			when others => active_led7_an <= "0111";
		end case;

		case active_led7_an is
			when "0111" => led7_seg_o <= digit_i (31 downto 24);
			when "1011" => led7_seg_o <= digit_i (23 downto 16);
			when "1101" => led7_seg_o <= digit_i (15 downto 8);
			when "1110" => led7_seg_o <= digit_i (7 downto 0);
			when others => led7_seg_o <= "00000000";
		end case;
	end if;
	led7_an_o <= active_led7_an;
end process;

end Behavioral;