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BGB Jumbo Prefix extension for RISC-V

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Oct 3rd, 2024
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  1. BGB Jumbo Extension for RISC-V
  2. * Rationale: Define extensions that address a few weak areas in RV64.
  3. * This will also assume the existence of the Zba extension.
  4.  
  5.  
  6. === Jumbo Encodings ===
  7.  
  8. * tiiiiii-iiiii-jjjjj-100-kkkkk-00-11011 J22 (Prefix, BGB)
  9. * 0iiiiii-iiiii-jjjjj-100-kkkkk-00-11011 J21I (Prefix, BGB)
  10. * 1iiiiii-iiiii-zzzzV-100-omnpp-00-11011 J21O (Prefix, BGB)
  11. * tiiiiii-iiiii-zzzzz-100-sZnpp-00-11011 J12O (Prefix, BGB)
  12.  
  13. The jumbo prefix will be a prefix op, which will combine with the following instruction.
  14.  
  15. To some extent, the interpretation of the jumbo prefix will depend on the type of instruction it is combined with.
  16.  
  17.  
  18. J21I + Imm12:
  19. * An Imm12 field will be expanded to 33 bits.
  20. ** Instruction ( 31) gives ( 32) / Sign Extension
  21. ** Prefix (11: 7) gives (31:27)
  22. ** Prefix (19:15) gives (26:22)
  23. ** Prefix (30:20) gives (21:11)
  24. ** Instruction (30:20) gives (10: 0)
  25.  
  26. The J21O prefix may combine with Imm12 ops:
  27. * The immediate field will be 22 bits;
  28. ** Instruction ( 31) gives ( 22) / Sign Extension
  29. ** Prefix (30:20) gives (21:11)
  30. ** Instruction (30:20) gives (10: 0)
  31. * The register fields will expand to 6 bits.
  32. * The V field will be an opcode bit.
  33. * the z field will give additional opcode bits.
  34. ** 0 will perform the base operation.
  35. ** The meaning of these bits will depend on base instruction.
  36.  
  37. The J21O prefix may combine with 3 register ops:
  38. * The register fields will expand to 6 bits.
  39. * V=0: The i field may be used as context-dependant bits.
  40. * V=1: The i and Ro fields will combine into an Imm17s.
  41. ** Prefix ( 11) gives ( 16) / Sign Extension
  42. ** Prefix (30:20) gives (15:5)
  43. ** Instruction (24:20) gives ( 4:0)
  44. ** The Immediate will logically replace Ro.
  45. * Possible, FPU Ops:
  46. ** Immediate case is understood as Binary16.
  47. * the z field will give additional opcode bits.
  48. ** 0 will perform the base operation.
  49.  
  50. If combined with LUI, AUIPC, or JAL:
  51. * Will be understood as a J12O.
  52. * The t and i fields will be filled into the low 12 bits.
  53. * The high 20 bits will be taken from the LUI or AUIPC.
  54. * The s field will be taken as a sign extension bit.
  55. * Note that JAL will be decoded the same as LUI and AUIPC in this case.
  56.  
  57. If two prefixes are combined with a LUI:
  58. * Interpreted as J22.
  59. * First Prefix (11: 7) gives (63:59)
  60. * First Prefix (19:15) gives (58:54)
  61. * First Prefix (30:20) gives (53:43)
  62. * First Prefix ( 31) gives ( 42)
  63. * Second Prefix (11: 7) gives (41:37)
  64. * Second Prefix (19:15) gives (36:32)
  65. * Instruction (31:12) gives (31:12)
  66. * Second prefix (31:20) gives (11: 0)
  67.  
  68. The two J22 Prefixes on a LUI will encode a direct 64-bit constant load.
  69. * Note that the pattern for a LUI assumes two decoders working in parallel.
  70. * Each will decode a 32 bit value which will be combined to 64 bits.
  71.  
  72.  
  73. Expanded Register Numbers (Optional):
  74. * Nominally, with the expanded 6 bit registers:
  75. ** 0..31: Map to X0..X31
  76. ** 32..63: Map to F0..F31
  77. * These will map FPU and integer instructions into the same register space.
  78. * (Possible?) V instructions:
  79. ** 0..31: V0..V31
  80. ** If VLEN=64-bit, 32..63 maps to F0..F31.
  81. ** If VLEN=128-bit, 32..63: Map to F and X spaces.
  82. ** Even: Even Pairs in F Space.
  83. ** Odd: Even Pairs in X Space, excluding 0, 2, 4.
  84. ** This will be N/A for other sizes of VLEN.
  85.  
  86.  
  87. Predication (Optional):
  88. * PP=00: Unconditional
  89. * PP=01: Reserved
  90. * PP=10: Execute if True (T=1)
  91. * PP=11: Execute if False (T=0)
  92. * The SLT, SLTI, SLTU, and SLTIU instructions may update T if Rn==X0.
  93. ** These are to be ignored if the implementation does not support a T bit.
  94.  
  95.  
  96. === SHORI ===
  97.  
  98. * 0iiiiii-iiiii-jjjjj-110-nnnnn-00-11011 SHORI Rn, Imm16u
  99. * J21I 0iiiiii-iiiii-mmmmm-110-nnnnn-00-11011 SHORI32 Rn, Rm, Imm32u
  100.  
  101. SHORI will perform the operation:
  102. * Rn = (Rn SHL 16) OR Imm16u
  103.  
  104. SHORI32 will perform the operation:
  105. * Rn = (Rm SHL 32) OR Imm32u
  106.  
  107. Imm16:
  108. * (30:20) will give (10: 0)
  109. * (19:15) will give (15:11)
  110.  
  111.  
  112. === FCVT.D.H (Imm16u) ===
  113.  
  114. * 1iiiiii-iiiii-jjjjj-110-nnnnn-00-11011 FCVT.D.H Fn, Imm16u
  115.  
  116. Imm16:
  117. * (30:20) will give (10: 0)
  118. * (19:15) will give (15:11)
  119.  
  120. This will load a Binary16 value into an FPR, converting it to Binary64.
  121. * Restriction: Only normal-range values allowed and Zero allowed.
  122. ** The exact result of Inf/NaN or Subnormal values will be undefined.
  123.  
  124. For the Binary16 format:
  125. * s.h.eeee.ffffffffff
  126.  
  127. The conversion here will be informally defined as:
  128. * s.h.HHHHHH.eeee.ffffffffff.0000 ...
  129. * Where H = (~h) AND (e!=0).
  130. ** This conversion may be understood for other instances of Binary16 immediates.
  131.  
  132.  
  133. === LDI (Imm17s) ===
  134.  
  135. * iiiiiii-iiiii-jjjjj-111-nnnnn-00-11011 LDI Rn, Imm17s
  136.  
  137. This operation will load a 17-bit sign-extended immediate into Rn.
  138.  
  139. Imm16:
  140. * (30:20) will give (10: 0)
  141. * (19:15) will give (15:11)
  142. * ( 31) will give ( 16) / Sign Extension
  143.  
  144.  
  145. === Load / Store Indexed ===
  146.  
  147. * 00110ss-ooooo-mmmmm-ttt-nnnnn-01-01111 Lt Rn, (Rm, Ro) (BGB: ScIx)
  148. ** 00110ss-ooooo-mmmmm-000-nnnnn-01-01111 LB Rn, (Rm, Ro*Sc)
  149. ** 00110ss-ooooo-mmmmm-001-nnnnn-01-01111 LH Rn, (Rm, Ro*Sc)
  150. ** 00110ss-ooooo-mmmmm-010-nnnnn-01-01111 LW Rn, (Rm, Ro*Sc)
  151. ** 00110ss-ooooo-mmmmm-011-nnnnn-01-01111 LD Rn, (Rm, Ro*Sc)
  152. ** 00110ss-ooooo-mmmmm-100-nnnnn-01-01111 LBU Rn, (Rm, Ro*Sc)
  153. ** 00110ss-ooooo-mmmmm-101-nnnnn-01-01111 LHU Rn, (Rm, Ro*Sc)
  154. ** 00110ss-ooooo-mmmmm-110-nnnnn-01-01111 LWU Rn, (Rm, Ro*Sc)
  155. ** 00110ss-ooooo-mmmmm-111-nnnnn-01-01111 LX Rn, (Rm, Ro*Sc)
  156.  
  157. * 00111ss-ooooo-mmmmm-ttt-nnnnn-01-01111 St (Rm, Ro), Rn (BGB: ScIx)
  158. ** 00111ss-ooooo-mmmmm-000-nnnnn-01-01111 SB (Rm, Ro*Sc), Rn
  159. ** 00111ss-ooooo-mmmmm-001-nnnnn-01-01111 SH (Rm, Ro*Sc), Rn
  160. ** 00111ss-ooooo-mmmmm-010-nnnnn-01-01111 SW (Rm, Ro*Sc), Rn
  161. ** 00111ss-ooooo-mmmmm-011-nnnnn-01-01111 SD (Rm, Ro*Sc), Rn
  162. ** 00111ss-ooooo-mmmmm-100-nnnnn-01-01111 ? SBU (Rm, Ro*Sc), Rn
  163. ** 00111ss-ooooo-mmmmm-101-nnnnn-01-01111 ? SHU (Rm, Ro*Sc), Rn
  164. ** 00111ss-ooooo-mmmmm-110-nnnnn-01-01111 ? SWU (Rm, Ro*Sc), Rn
  165. ** 00111ss-ooooo-mmmmm-111-nnnnn-01-01111 SX (Rm, Ro*Sc), Rn
  166.  
  167. These perform a Load/Store with Ro understood as an index register.
  168. * ss will give the scale (1/2/4/8).
  169.  
  170.  
  171. === Load / Store Pair ===
  172.  
  173. * iiiiiii-iiiii-mmmmm-111-nnnnn-00-00011 LX Rn, Rm, Disp12_I
  174. * iiiiiii-ttttt-mmmmm-111-iiiii-01-00011 SX Rm, Disp12_S, Rt
  175.  
  176. Load or Store a 128 bit register pair.
  177. * An implementation may require an 8 byte alignment for LX/SX.
  178. * Even registers will map to pairs in X space.
  179. * Odd registers will map to pairs in F space.
  180.  
  181.  
  182. === DMULSW / DMULUW ===
  183.  
  184. * 0000001-ttttt-mmmmm-010-nnnnn-01-11011 DMULSW Rn, Rm, Rt
  185. * 0000001-ttttt-mmmmm-011-nnnnn-01-11011 DMULUW Rn, Rm, Rt
  186.  
  187. These perform a widening 32-bit multiply, producing a 64-bit result.
  188. * DMULSW will understand the input values as signed.
  189. * DMULUW will understand the input values as unsigned.
  190.  
  191. While theoretically these don't offer much over MUL, they may hint to use a faster 32-bit multiplier if available.
  192. * May alias to MUL if no fast 32-bit widening multiplier exists.
  193. * Result is implementation defined if values are out of range.
  194.  
  195.  
Tags: RISC-V RV64 RV64G RV64GC
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