Instruction Memory

`timescale 1ns / 1ps

// in the IF phase of pipeline
// emulates the codes being flashed into ROM part of microprocessor


module Instruction_memory(
                            input [31:0] PC,
                            output reg [31:0] IR    // YESSSS!
                            );


reg [6:0] opcode = 0;
reg [4:0] DA = 0;
reg [4:0] AA = 0;
reg [4:0] BA = 0;
reg [9:0] junk = 0;
reg [14:0] IM = 0;
reg [14:0] TAR = 0;

localparam NOP = 7'b0000000;
localparam ADD = 7'b0000010;
localparam SUB = 7'b0000101;
localparam SLT = 7'b1100101;
localparam AND = 7'b0001000;
localparam OR  = 7'b0001010;
localparam XOR = 7'b0001100;
localparam ST  = 7'b0000001;
localparam LD  = 7'b0100001;
localparam ADI = 7'b0100010;
localparam SBI = 7'b0100101;
localparam NOT = 7'b0101110;
localparam ANI = 7'b0101000;
localparam ORI = 7'b0101010;
localparam XRI = 7'b0101100;
localparam AIU = 7'b1100010;
localparam SIU = 7'b1000101;
localparam MOV = 7'b1000000;
localparam LSL = 7'b0110000;
localparam LSR = 7'b0110001;
localparam JMR = 7'b1100001;
localparam BZ  = 7'b0100000;
localparam BNZ = 7'b1100000;
localparam JMP = 7'b1000100;
localparam JML = 7'b0000111;

// NO DATA FORWARDING FOR NOW, SO ADD NO OPS IN BETWEEN

//1, add sign IM, dest = R5, AA = 1, IM = 27
//7-bits opcode, 5-bits dest, 5-bits sA, optional: 5-bit sB/10-junk, 15-bit immediate, 15-bit target jump
// block of code to assign
                // 7-bits |5-bit |5-bit| 5-bit + 10-bit |
                // OPCODE | DEST | AA  | TARGET JUMP    |
always@(*) begin// OPCODE | DEST | AA  | IMMEDIATE      |
    case(PC)    // OPCODE | DEST | AA  | BA  | JUNK     |
        0: IR = NOP;
        1: IR = 32'b0100010_00101_00001_000000000011011; // 27 + R1 (0) --> R 5 {ADI,dest,aa,immediate}
        2: IR = NOP;
        3: IR = 32'b0101110_00100_00101_000000000011011; // NOT R5 --> R4 (immediate unused), {NOT,dest,aa,immediate unused}
        4: IR = NOP;
        5: IR = 32'b0101110_00011_00000_000000000011011; // NOT R0 --> R3 {NOT,dest,aa,immediate unused}
        6: IR = NOP;
        7: IR = 32'b0000001_00000_00101_001000000011011; // Store R4 -->M(R5) {}
        8: IR = NOP;
        9: IR = 32'b0100001_00110_00101_000000000011011;    // load M(R5) --> R6
        10:IR = NOP;
        11:IR = 32'b0100000_00101_00000_100000000001100; // do a jump here BZ (R(A)) = 0 --> PC + 1 +se IM (PC + 1 = 12, + se 12 (MSB = 1, so negative))
            // should have the PC increment, then subtract back to 0
        default: IR = NOP;
    endcase

end

endmodule