RateDivider

module ratedivider(SW,KEY,HEX0,CLOCK_50);
	input CLOCK_50;
	input [9:0] SW;
	input [3:0] KEY;
	output [6:0] HEX0;

	wire out;
	ratedividerinst r0(.reset_n(SW[2]),.speed(SW[1:0]),.clk_in(CLOCK_50),.clk_out(out),.HEX(HEX0));
endmodule

module ratedividerinst(reset_n, speed,clk_in,clk_out,HEX);
	input [1:0] speed;
	input clk_in;
	output clk_out;
	output [6:0] HEX;

// wire clock,par_load;
	input reset_n;
	reg [25:0] q;

	reg clk_out,enable;
	reg [25:0] d;

	reg temp;

	//always @(posedge clk_in or negedge reset_n)
	always @(posedge clk_in)
	begin
		if(reset_n == 1'b0)
			q<=0;
		else if (enable == 1'b1)
			begin
				if(q>=d)
					begin
						q <= 26'b0;
						temp = 1;
					end
				else
					begin
						q <= q + 1'b1;
						temp = 0;
					end
			end
	end

	always @(*)
	begin
		case (speed)
			2'b00:
				begin
					enable = 0;
//					clk_out <= clk_in;
//					temp1 <= clk_in;
				end
			2'b01:
				begin
					enable = 1;
					d <= 26'b10111110101111000001111111;
				end
			2'b10:
				begin
					enable = 1;
					d <= 26'b01011111010111100000111111;
				end
			2'b11:
				begin
					enable = 1;
					d <= 26'b00101111101011110000011111;
				end
		endcase
	end

	always @(*)
	begin
		if (enable==1)
			clk_out = temp;
		else
			clk_out = clk_in;
	end

	reg [3:0] counter;

//	always @(posedge clk_out or negedge reset_n)
	always @(posedge clk_out)
	begin
		if(reset_n ==0)
			counter <=0;
		else if (counter == 4'b1111)
			counter <= 0;
		else
			counter = counter + 1;
	end
	segdecoder d0(.in(counter),.HEX(HEX));


endmodule

module segdecoder(in, HEX);
//	input [3:0] in;
	input [0:3] in;
	output [6:0] HEX;

	assign HEX[0] = in[3]&~in[2]&~in[1]&~in[0] | ~in[3]&~in[2]&in[1]&~in[0] | in[3]&~in[2]&in[1]&in[0] | in[3]&in[2]&~in[1]&in[0];
	assign HEX[1] = in[3]&~in[2]&in[1]&~in[0] | ~in[3]&in[2]&in[1] | ~in[3]&in[1]&in[0] | in[3]&in[2]&in[0];
	assign HEX[2] = ~in[3]&in[2]&~in[1]&~in[0] | ~in[3]&in[1]&in[0] | in[2]&in[1]&in[0];
	assign HEX[3] = in[3]&~in[2]&~in[1] | ~in[3]&~in[2]&in[1]&~in[0] | in[3]&in[2]&in[1] | ~in[3]&in[2]&~in[1]&in[0];
	assign HEX[4] = in[3]&~in[2]&~in[1] | in[3]&~in[0] | ~in[2]&in[1]&~in[0];
	assign HEX[5] = in[3]&~in[1]&~in[0] | in[2]&~in[1]&~in[0] | in[3]&in[2]&~in[0] | in[3]&~in[2]&in[1]&in[0];
	assign HEX[6] = ~in[2]&~in[1]&~in[0] | in[3]&in[2]&in[1]&~in[0] | ~in[3]&~in[2]&in[1]&in[0];
endmodule