diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py
index 1dfda8c..db9f055 100755
--- a/litex_boards/targets/nexys4ddr.py
+++ b/litex_boards/targets/nexys4ddr.py
@@ -27,6 +27,8 @@ from liteeth.phy.rmii import LiteEthPHYRMII

 from litevideo.terminal.core import Terminal

+from litescope import LiteScopeAnalyzer
+
 # CRG ----------------------------------------------------------------------------------------------

 class _CRG(Module):
@@ -56,7 +58,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------

 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, with_vga=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, with_analyzer=False, with_vga=False, **kwargs):
         platform = nexys4ddr.Platform()

         # SoCCore ----------------------------------_-----------------------------------------------
@@ -96,6 +98,24 @@ class BaseSoC(SoCCore):
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy)

+        # Analyzer ------------------------------------------------------------
+        if with_analyzer:
+            analyzer_signals = [
+                self.cpu.mem_axi.aw, self.cpu.mem_axi.w, self.cpu.mem_axi.b,
+                self.cpu.mem_axi.ar, self.cpu.mem_axi.r,
+                self.cpu.mmio_axi.aw, self.cpu.mmio_axi.w, self.cpu.mmio_axi.b,
+                self.cpu.mmio_axi.ar, self.cpu.mmio_axi.r,
+                self.cpu.l2fb_axi.aw, self.cpu.l2fb_axi.w, self.cpu.l2fb_axi.b,
+                self.cpu.l2fb_axi.ar, self.cpu.l2fb_axi.r,
+            ]
+            self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
+                depth        = 512,
+                clock_domain = "sys",
+                csr_csv      = "analyzer.csv")
+            self.add_csr("analyzer")
+            if not with_etherbone:
+                self.add_jtagbone()
+
         # VGA terminal -----------------------------------------------------------------------------
         if with_vga:
             self.submodules.terminal = terminal = Terminal()
@@ -124,6 +144,7 @@ def main():
     parser.add_argument("--sys-clk-freq",    default=75e6,        help="System clock frequency (default: 75MHz)")
     parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-etherbone",  action="store_true", help="Enable Etherbone support")
+    parser.add_argument("--with-analyzer",   action="store_true", help="Enable Analyzer support")
     parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
     parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
     parser.add_argument("--with-vga",        action="store_true", help="Enable VGA support")
@@ -136,6 +157,7 @@ def main():
         sys_clk_freq   = int(float(args.sys_clk_freq)),
         with_ethernet  = args.with_ethernet,
         with_etherbone = args.with_etherbone,
+        with_analyzer  = args.with_analyzer,
         **soc_sdram_argdict(args)
     )
     assert not (args.with_spi_sdcard and args.with_sdcard)
@@ -144,7 +166,10 @@ def main():
     if args.with_sdcard:
         soc.add_sdcard()
     builder = Builder(soc, **builder_argdict(args))
-    builder.build(run=args.build)
+    vns = builder.build(run=args.build)
+
+    if args.with_analyzer:
+        soc.analyzer.export_csv(vns, "analyzer.csv")

     if args.load:
         prog = soc.platform.create_programmer()