VGA

module vgac(
  input clk,
  output vga_h_sync,
  output vga_v_sync,
  output [9:0] R,
  output [9:0] G,
  output [9:0] B
);
reg nclk;
reg [9:0] v_count;
reg [8:0] h_count;
reg cH_display;
reg cV_display;

clock_divisor c1(
  .in_clk(clk),
  .output_clk(nclk)
);

always @(posedge nclk)
if(h_count < 799) begin
  h_count <= h_count + 1;
  if(h_count < 96)
    cH_display = 0;
  else
    cH_display = 1;
end
else
  h_count = 0;

always @(posedge nclk)
if(v_count < 524) begin
    v_count <= v_count + 1;
    if(v_count < 2)
      cV_display = 0;
    else
      cV_display = 1;
end
else
    v_count <= 0;

assign vga_h_sync = ~cH_display;
assign vga_v_sync = ~cV_display;

assign R = 15;
assign G = 15;
assign B = 15;

endmodule