CSE3215_Lab5

module Lab5(
                input CLOCK_50,
                input [3:0] KEY,
                output reg [17:0] LEDR,
                inout reg [35:0] GPIO_0,
                output reg [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7
);

    reg [31:0] time4k, time50, time118, duty;
    reg [15:0] count, index, sum, integral[0:1], error, pid, ki, kp;
    reg [15:0] freq[0:2],temp[0:2];
    reg [8:0] div, setTemp, avTemp, mult;
    reg flag1, flag2;
    wire [6:0] h0,h1,h2,h3,h4,h5,h6,h7,s0,s1,s2,s3;
    wire K0, K1, K2, K3;

    hex_7seg(((temp[0]+temp[1]+temp[2])/3)%10, h0);
    hex_7seg(((temp[0]+temp[1]+temp[2])/3)/10%10, h1);
    hex_7seg(((temp[0]+temp[1]+temp[2])/3)/100%10, h2);
    hex_7seg(((temp[0]+temp[1]+temp[2])/3)/1000%10, h3);

    hex_7seg(mult%10,h4);
    hex_7seg(mult/10%10,h5);

    hex_7seg(setTemp%10,s0);
    hex_7seg(setTemp/10%10,s1);
    hex_7seg(setTemp/100%10,s2);
    hex_7seg(setTemp/1000%10,s3);

    oneshot g1(K1, CLOCK_50, ~KEY[1]);
    oneshot g2(K2, CLOCK_50, ~KEY[2]);

    initial begin
        time50 = 0;
          time4k = 0;
          time118 = 0;
          flag1 = 0;
          flag2 = 0;
          div = 2;
          setTemp = 240;
          index = 0;
          mult = 0;


    end

    always begin
        if(!KEY[0]) begin
            LEDR[3] = 1;
            HEX0 <= s0;
            HEX1 <= s1;
            HEX2 <= s2;
            HEX3 <= s3;
        end
        else begin
            LEDR[3] = 0;
            HEX0 <= h0;
            HEX1 <= h1;
            HEX2 <= h2;
            HEX3 <= h3;

        end

        HEX4 <= h4;
        HEX5 <= h5;
        HEX6 <= h6;
        HEX7 <= h7;

        duty = 139474  ;

        /*HEX6 <= h6;
        HEX7 <= h7;*/
    end

    always @(negedge CLOCK_50) begin

        if(K1) begin
            setTemp = setTemp+1;
            if(setTemp > 280)
                setTemp = 200;
        end

        if(K2) begin
            mult <= mult+1;
            if(mult >= 5)
                mult <= 0;
        end

        if(time50 >= 12500) begin
            time4k = time4k + 1;
            if(time4k >= 4000) begin
                    LEDR[0] = 1'b1;
                    flag1 = 1;
                    time4k = 0;
            end
            if(flag2) begin
                flag1 = 0;
            end
            time50 = 0;
        end

        time50 = time50+1;

    end

     always @ (negedge GPIO_0[0]) begin
        count = count + 1;
        if(flag1) begin

            LEDR[2] = ~LEDR[2];
            freq[index] = count;
            //freq[index] = count;

            temp[index] = 160 + ((((freq[index])) - 800)/11);
            index = index + 1;
            count = 0;
            flag2 = 1;
        end
        else begin
            flag2 = 0;
            if(index > 2)
                index = 0;
        end

     end

    always@(negedge CLOCK_50) begin

        /*error = setTemp - temp[index];
        integral[1] = ki*error + integral[0];
        pid = kp*error + integral[1];
        integral[0] = integral[1];*/


        if(time118 >= 423728) begin
            time118 = 0;
        end

        if(time118 <= duty) begin
            LEDR[1] = 1'b1;
            GPIO_0[1] = 1'b1;
        end
        else begin
            LEDR[1] = 1'b0;
            GPIO_0[1] = 1'b0;
        end

        time118 = time118 + 1;
    end

endmodule

module oneshot(output reg pulse_out,input clk,input trigger_in);
reg delay;

always @ (posedge clk)
begin
       if (trigger_in && !delay) pulse_out <= 1'b1;
       else pulse_out <= 1'b0;
               delay <= trigger_in;
end
endmodule


module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
        4'h0: seg = 7'b1000000;
        4'h1: seg = 7'b1111001;     // ---a----
        4'h2: seg = 7'b0100100;     // |      |
        4'h3: seg = 7'b0110000;     // f      b
        4'h4: seg = 7'b0011001;     // |      |
        4'h5: seg = 7'b0010010;     // ---g----
        4'h6: seg = 7'b0000010;     // |      |
        4'h7: seg = 7'b1111000;     // e      c
        4'h8: seg = 7'b0000000;     // |      |
        4'h9: seg = 7'b0011000;     // ---d----
        4'ha: seg = 7'b0001000;
        4'hb: seg = 7'b0000011;
        4'hc: seg = 7'b1000110;
        4'hd: seg = 7'b0100001;
        4'he: seg = 7'b0000110;
        4'hf: seg = 7'b0001110;
endcase
endmodule