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aidanozo
Oct 23rd, 2024
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VeriLog
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module
led7
(
output
wire
[
6
:
0
]
o_w_7seg
,
output
wire
[
7
:
0
]
o_w_an
,
input
wire
[
3
:
0
]
i_w_in
,
input
wire
[
7
:
0
]
i_w_an
)
;
// Implementarea noastra
endmodule
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