module traffic (
    clock,
    red_a, green_a, yellow_a,
    red_b, green_b, yellow_b
);

    input clock;
    output red_a, green_a, yellow_a, red_b, green_b, yellow_b;

    reg o_red_a = 0;
    reg o_green_a = 1;
    reg o_yellow_a = 0;
    reg o_red_b = 1;
    reg o_green_b = 0;
    reg o_yellow_b  = 0;

    reg [7:0] counter = 0;

    always @(posedge clock) begin
        counter = counter + 1;

        if (counter == 20) begin
            o_green_a = !o_green_a;
            o_yellow_a = !o_yellow_a;
        end else if (counter == 40) begin
            o_red_b = !o_red_b;
            o_green_b = !o_green_b;
            o_red_a = !o_red_a;
            o_yellow_a = !o_yellow_a;
        end else if (counter == 60) begin
            o_green_a = !o_green_a;
            o_yellow_a = !o_yellow_a;
        end else if (counter == 80) begin
            o_red_b = !o_red_b;
            o_green_b = !o_green_b;
            o_red_a = !o_red_a;
            o_yellow_a = !o_yellow_a;
        end

        if (counter == 81) begin
            counter = 0;
        end
    end

    assign green_a = o_green_a;
    assign yellow_a = o_yellow_a;
    assign red_a = o_red_a;
    assign green_b = o_green_b;
    assign yellow_b = o_yellow_b;
    assign red_b = o_red_b;
endmodule