Musebook's custom FSBL first attempt

ROM: usb download handler
usb2d_initialize : enter
Controller Run
usb rst int
SETUP: 0x80 0x6 0x100
usb rst int
SETUP: 0x0 0x5 0xe
SETUP: 0x80 0x6 0x100
SETUP: 0x80 0x6 0x200
SETUP: 0x80 0x6 0x200
SETUP: 0x80 0x6 0x300
SETUP: 0x80 0x6 0x302
SETUP: 0x80 0x6 0x301
SETUP: 0x80 0x6 0x30a
SETUP: 0x0 0x9 0x1
usb_rx_bytes : len= 4096 pBuf= 0xc0838720
SETUP: 0x80 0x6 0x302
SETUP: 0x80 0x6 0x304
fastboot_handle_command: max-download-size
usb_tx_bytes : len= 65 pBuf= 0xc083fe88
usb_rx_bytes : len= 4096 pBuf= 0xc0838720
fastboot_handle_command: 0002a700
Starting download of 173824 bytes
usb_tx_bytes : len= 65 pBuf= 0xc083fe88
usb_rx_bytes : len= 173824 pBuf= 0xc0800000
usb_tx_bytes : len= 65 pBuf= 0xc083fe88
usb_rx_bytes : len= 4096 pBuf= 0xc0838720
fastboot_handle_command: continue
usb_tx_bytes : len= 65 pBuf= 0xc083fe88
j...

U-Boot SPL 2022.10spacemit-g7ee69ae6 (Aug 25 2024 - 07:23:02 +0200)
ADDR[0xc0000304]=0x00800400 !!!!
PHY INIT done
wait DRAM INIT
DRAM INIT done
DRAM Mode register Init done.....
ddr density: 16384 MB
DEBUG-ADDR[0xc0000200]:0x110001
DEBUG-ADDR[0xc0000204]:0x0
DEBUG-ADDR[0xc0000208]:0x110001
DEBUG-ADDR[0xc000020c]:0x2
DEBUG-ADDR[0xc0000220]:0x5030832
DEBUG-ADDR[0xc0000224]:0x5030832
ddr density: 16384 MB
enter self refresh start .....
enter self refresh start done .....
c0000000, 0, 2
Training start....
Training init....
dump margin and setting Before Training....
Write Leveling.....
Read Gate Training.....
Read_gate_training PASS!!
Read_gate_training PASS!!
read gate code[0xc0040070]=0x00017575
read gate code[0xc0040170]=0x00017373
read gate code[0xc0041070]=0x00016f6f
read gate code[0xc0041170]=0x00016f6f
Read Training.....
each RX Vref corresponding min margin = 22 23 23 24 24 24 24 24 23 23 22 21 20 17 16 14
 optimize Rx Vref adjust=3 ,corresponding best margin=24
Again!!! training optimize Fine Rx vref step = 3
Write Training.....
each TX Vref corresponding min margin = 24 24 24 24 24 24 24 24 24 23 23 23 23 23 23 23
 optimize Tx Vref adjust=21 ,corresponding best margin=24
Again!!! training optimize Fine Tx vref step = 21
Training status[0xC0058000]=0x00000000
change to 1600
frequency change done!!!!
enter self refresh start .....
enter self refresh start done .....
c0000000, 1, 2
Training start....
Training init....
dump margin and setting Before Training....
Write Leveling.....
Read Gate Training.....
Read_gate_training PASS!!
Read_gate_training PASS!!
read gate code[0xc0044070]=0x00016060
read gate code[0xc0044170]=0x00016161
read gate code[0xc0045070]=0x00015c5c
read gate code[0xc0045170]=0x00015b5b
Read Training.....
each RX Vref corresponding min margin = 16 16 16 17 17 18 18 17 16 16 15 15 14 10 8 6
 optimize Rx Vref adjust=5 ,corresponding best margin=18
Again!!! training optimize Fine Rx vref step = 5
Write Training.....
each TX Vref corresponding min margin = 17 17 17 17 17 17 17 17 17 16 16 16 16 16 16 16
 optimize Tx Vref adjust=21 ,corresponding best margin=17
Again!!! training optimize Fine Tx vref step = 21
Training status[0xC0058000]=0x00000000
change to 2400
frequency change done!!!!
enter self refresh start .....
enter self refresh start done .....
c0000000, 2, 2
Training start....
Training init....
dump margin and setting Before Training....
Write Leveling.....
Read Gate Training.....
Read_gate_training PASS!!
Read_gate_training PASS!!
read gate code[0xc0048070]=0x00014e4e
read gate code[0xc0048170]=0x00014e4e
read gate code[0xc0049070]=0x00014a4a
read gate code[0xc0049170]=0x00014a4a
Read Training.....
each RX Vref corresponding min margin = 8 9 9 10 10 10 10 9 9 8 7 7 5 0 0 0
 optimize Rx Vref adjust=3 ,corresponding best margin=10
Again!!! training optimize Fine Rx vref step = 3
Write Training.....
each TX Vref corresponding min margin = 9 9 10 10 10 10 10 10 10 10 10 10 10 10 9 9
 optimize Tx Vref adjust=23 ,corresponding best margin=10
Again!!! training optimize Fine Tx vref step = 23
Training status[0xC0058000]=0x00000000
change to 2400
frequency change done!!!!
lpddr4_silicon_init consume 283ms