synth.v

/* Generated by Yosys 0.31+6 (git sha1 0b8f72859, clang 10.0.0-4ubuntu1 -fPIC -Os) */

(* hdlname = "\\test" *)
(* top =  1  *)
(* src = "test.v:1.1-12.10" *)
module test(clk, rst_n);
  (* src = "test.v:3.6-3.10" *)
  wire STAR;
  (* src = "test.v:2.8-2.11" *)
  input clk;
  wire clk;
  (* src = "test.v:2.13-2.18" *)
  input rst_n;
  wire rst_n;
  assign STAR = 1'h0;
endmodule