LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity 1reg is
port( d : IN std_logic;
	c : IN std_logic;
	r : IN std_logic;
	q1 : OUT std_logic;
	q2 : OUT srd_logic);
end 1reg;
architecture behav of 1reg is
	signal q1t:std_logic;
	signal q2t:std_logic;
	signal d2:std_logic;
	signal d3:std_logic;
begin
process (d, c, r)
	begin
		if r = '0' then
			q1t <= '0';
			q2t <= '0';
			d2 <= '0';
			d3 <= '0';
		else
			if c = '1' then
				d2<=d;
				q1t<=q1t;
				d3<=q1t;
				q2t<=q2t;
			else
				d2<=d2;
				q1t<=d2;
				d3<=d3;
				q2t<=d3;
			end if;
		end if;
	end process;
q1<=q1t;
q2<=q2t;
end behav;
-------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY dv2reg IS

PORT
   (
     D  : IN STD_LOGIC;
     C1 : IN STD_LOGIC;
     C2 : IN STD_LOGIC;
     R  : IN STD_LOGIC;
     Q1 : OUT STD_LOGIC;
     Q2 : OUT STD_LOGIC
   );

END dv2reg;

ARCHITECTURE a OF dv2reg IS

   SIGNAL A1 : STD_LOGIC;
   SIGNAL A2 : STD_LOGIC;
   SIGNAL B1 : STD_LOGIC;
   SIGNAL B2 : STD_LOGIC;

 BEGIN

  PROCESS (D, R,C1,C2)
  BEGIN

    IF R = '0' THEN

     A2 <= '0';
     B2 <= '0';

    ELSE
        IF C1 = '1' THEN
          A1 <= D;
          B1 <= A2;
        ELSE
           A1<=A1;
           B1<=B1;
        END IF;

        If C2 = '1' then
            A2 <= A1;
            B2 <= B1;
        Else
            A2 <= A2;
            B2<= B2;
        END IF;
    END IF;

  END PROCESS;
  Q1<=A2;
  Q2<=B2;
END a;
----------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity dff_async is
port (data, clk, reset, preset : in std_logic;
 q : out std_logic);
end dff_async;
architecture behav of dff_async is
begin
process (clk, reset, preset) begin
 if (reset = '0') then
 q <= '0';
 elsif (preset = '0') then
 q <= '1';
 elsif (clk'event and clk = '1') then
 q <= data;
 end if;
end process;
end behav;
-----------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY dvreg IS

PORT
(
D: IN STD_LOGIC;
C : IN STD_LOGIC;
R : IN STD_LOGIC;
Q1 : OUT STD_LOGIC;
P1 : OUT STD_LOGIC;
Q2 : OUT STD_LOGIC;
P2 : OUT STD_LOGIC
);

END dvreg;

ARCHITECTURE a OF dvreg IS

SIGNAL A: STD_LOGIC;
SIGNAL B: STD_LOGIC;
SIGNAL B1: STD_LOGIC;
SIGNAL A1: STD_LOGIC;

BEGIN

PROCESS (D, C ,R)
BEGIN

IF R='0' THEN
A<='0';
B<='0';
B1<='0';
A1<='0';
ELSE
IF C='1' THEN
A<=D;
B<=B;
B1<=B;
A1<=A1;
ELSE
A<=A;
B<=A;
B1<=B1;
A1<=B1;
END IF;

END IF;


END PROCESS;

P1<=A;
Q1<=B;
P2<=B1;
Q2<=A1;

END a;
------------------------
-- MAX+plus II VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY 2reg IS

	PORT
	(
		D	: IN	STD_LOGIC;
		C1	: IN	STD_LOGIC;
		C2	: IN	STD_LOGIC;
		R	: IN	STD_LOGIC;
		Q1	: OUT 	STD_LOGIC;
		Q2	: OUT 	STD_LOGIC;
	);

END 2reg;

ARCHITECTURE a OF 2reg IS

	SIGNAL	A	: STD_LOGIC;
	SIGNAL	B	: STD_LOGIC;

BEGIN

	PROCESS (C1, C2, D, R)
	BEGIN

		IF R = '0' THEN

			A <= '0';
			B <= '0';

		ELSE

			IF C1 = '1' THEN A <= D;
			ELSE A<=A;
			END IF;


			IF C2 = '1' THEN B<=A;
			ELSE B<=B;
			END IF;

		END IF;

	END PROCESS;
		Q1<=A;
		Q2<=B;
END a;
--------------
-- MAX+plus II VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY regP IS
	PORT
	(X1	: IN	STD_LOGIC;
	 X2	: IN	STD_LOGIC;
	 X3	: IN	STD_LOGIC;
     X4 : IN	STD_LOGIC;
	 write : IN	STD_LOGIC;
     reset : IN	STD_LOGIC;
	 read  : IN	STD_LOGIC;
     Q1  : OUT STD_LOGIC;
     Q2  : OUT STD_LOGIC;
     Q3  : OUT STD_LOGIC;
     Q4  : OUT STD_LOGIC);
END regP;

ARCHITECTURE behav OF regP IS
	SIGNAL	A1: STD_LOGIC;
    SIGNAL	A2: STD_LOGIC;
    SIGNAL	A3: STD_LOGIC;
    SIGNAL	A4: STD_LOGIC;
    SIGNAL	B1: STD_LOGIC;
    SIGNAL	B2: STD_LOGIC;
    SIGNAL	B3: STD_LOGIC;
    SIGNAL	B4: STD_LOGIC;

BEGIN

	PROCESS (X1,X2,X3,X4,write,reset,read)
	BEGIN
	 IF  Reset = '0' THEN
         A1 <= '0';
         A2 <= '0';
         A3 <= '0';
         A4 <= '0';
     ELSE
         IF write = '1' THEN
            A1 <= X1;
            A2 <= X2;
            A3 <= X3;
            A4 <= X4;
         ELSE
			A1 <= A1;
            A2 <= A2;
            A3 <= A3;
            A4 <= A4;
		END IF;
  END IF;
    B1 <= A1 and read;
    B2 <= A2 and read;
    B3 <= A3 and read;
    B4 <= A4 and read;
	END PROCESS;
Q1 <= B1;
Q2 <= B2;
Q3 <= B3;
Q4 <= B4;
END behav;