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coreinfo report

_blAck_ Jul 1st, 2015 27 Never
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  1. Coreinfo v3.31 - Dump information on system CPU and memory topology
  2. Copyright (C) 2008-2014 Mark Russinovich
  3. Sysinternals - www.sysinternals.com
  4.  
  5. Intel(R) Xeon(R) CPU           X3360  @ 2.83GHz
  6. Intel64 Family 6 Model 23 Stepping 7, GenuineIntel
  7. Microcode signature: 00000705
  8. HTT             *       Hyperthreading enabled
  9. HYPERVISOR      -       Hypervisor is present
  10. VMX             *       Supports Intel hardware-assisted virtualization
  11. SVM             -       Supports AMD hardware-assisted virtualization
  12. X64             *       Supports 64-bit mode
  13.  
  14. SMX             *       Supports Intel trusted execution
  15. SKINIT          -       Supports AMD SKINIT
  16.  
  17. NX              *       Supports no-execute page protection
  18. SMEP            -       Supports Supervisor Mode Execution Prevention
  19. SMAP            -       Supports Supervisor Mode Access Prevention
  20. PAGE1GB         -       Supports 1 GB large pages
  21. PAE             *       Supports > 32-bit physical addresses
  22. PAT             *       Supports Page Attribute Table
  23. PSE             *       Supports 4 MB pages
  24. PSE36           *       Supports > 32-bit address 4 MB pages
  25. PGE             *       Supports global bit in page tables
  26. SS              *       Supports bus snooping for cache operations
  27. VME             *       Supports Virtual-8086 mode
  28. RDWRFSGSBASE    -       Supports direct GS/FS base access
  29.  
  30. FPU             *       Implements i387 floating point instructions
  31. MMX             *       Supports MMX instruction set
  32. MMXEXT          -       Implements AMD MMX extensions
  33. 3DNOW           -       Supports 3DNow! instructions
  34. 3DNOWEXT        -       Supports 3DNow! extension instructions
  35. SSE             *       Supports Streaming SIMD Extensions
  36. SSE2            *       Supports Streaming SIMD Extensions 2
  37. SSE3            *       Supports Streaming SIMD Extensions 3
  38. SSSE3           *       Supports Supplemental SIMD Extensions 3
  39. SSE4a           -       Supports Streaming SIMDR Extensions 4a
  40. SSE4.1          *       Supports Streaming SIMD Extensions 4.1
  41. SSE4.2          -       Supports Streaming SIMD Extensions 4.2
  42.  
  43. AES             -       Supports AES extensions
  44. AVX             -       Supports AVX intruction extensions
  45. FMA             -       Supports FMA extensions using YMM state
  46. MSR             *       Implements RDMSR/WRMSR instructions
  47. MTRR            *       Supports Memory Type Range Registers
  48. XSAVE           -       Supports XSAVE/XRSTOR instructions
  49. OSXSAVE         -       Supports XSETBV/XGETBV instructions
  50. RDRAND          -       Supports RDRAND instruction
  51. RDSEED          -       Supports RDSEED instruction
  52.  
  53. CMOV            *       Supports CMOVcc instruction
  54. CLFSH           *       Supports CLFLUSH instruction
  55. CX8             *       Supports compare and exchange 8-byte instructions
  56. CX16            *       Supports CMPXCHG16B instruction
  57. BMI1            -       Supports bit manipulation extensions 1
  58. BMI2            -       Supports bit manipulation extensions 2
  59. ADX             -       Supports ADCX/ADOX instructions
  60. DCA             -       Supports prefetch from memory-mapped device
  61. F16C            -       Supports half-precision instruction
  62. FXSR            *       Supports FXSAVE/FXSTOR instructions
  63. FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
  64. MONITOR         *       Supports MONITOR and MWAIT instructions
  65. MOVBE           -       Supports MOVBE instruction
  66. ERMSB           -       Supports Enhanced REP MOVSB/STOSB
  67. PCLMULDQ        -       Supports PCLMULDQ instruction
  68. POPCNT          -       Supports POPCNT instruction
  69. LZCNT           -       Supports LZCNT instruction
  70. SEP             *       Supports fast system call instructions
  71. LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
  72. HLE             -       Supports Hardware Lock Elision instructions
  73. RTM             -       Supports Restricted Transactional Memory instructions
  74.  
  75. DE              *       Supports I/O breakpoints including CR4.DE
  76. DTES64          *       Can write history of 64-bit branch addresses
  77. DS              *       Implements memory-resident debug buffer
  78. DS-CPL          *       Supports Debug Store feature with CPL
  79. PCID            -       Supports PCIDs and settable CR4.PCIDE
  80. INVPCID         -       Supports INVPCID instruction
  81. PDCM            *       Supports Performance Capabilities MSR
  82. RDTSCP          -       Supports RDTSCP instruction
  83. TSC             *       Supports RDTSC instruction
  84. TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
  85. TSC-INVARIANT   -       TSC runs at constant rate
  86. xTPR            *       Supports disabling task priority messages
  87.  
  88. EIST            *       Supports Enhanced Intel Speedstep
  89. ACPI            *       Implements MSR for power management
  90. TM              *       Implements thermal monitor circuitry
  91. TM2             *       Implements Thermal Monitor 2 control
  92. APIC            *       Implements software-accessible local APIC
  93. x2APIC          -       Supports x2APIC
  94.  
  95. CNXT-ID         -       L1 data cache mode adaptive or BIOS
  96.  
  97. MCE             *       Supports Machine Check, INT18 and CR4.MCE
  98. MCA             *       Implements Machine Check Architecture
  99. PBE             *       Supports use of FERR#/PBE# pin
  100.  
  101. PSN             -       Implements 96-bit processor serial number
  102.  
  103. PREFETCHW       *       Supports PREFETCHW instruction
  104.  
  105. Maximum implemented CPUID leaves: 0000000A (Basic), 80000008 (Extended).
  106.  
  107. Logical to Physical Processor Map:
  108. *---  Physical Processor 0
  109. -*--  Physical Processor 1
  110. --*-  Physical Processor 2
  111. ---*  Physical Processor 3
  112.  
  113. Logical Processor to Socket Map:
  114. ****  Socket 0
  115.  
  116. Logical Processor to NUMA Node Map:
  117. ****  NUMA Node 0
  118.  
  119. No NUMA nodes.
  120.  
  121. Logical Processor to Cache Map:
  122. *---  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
  123. *---  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
  124. -*--  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
  125. -*--  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
  126. **--  Unified Cache       0, Level 2,    6 MB, Assoc  24, LineSize  64
  127. --*-  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
  128. --*-  Instruction Cache   2, Level 1,   32 KB, Assoc   8, LineSize  64
  129. ---*  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
  130. ---*  Instruction Cache   3, Level 1,   32 KB, Assoc   8, LineSize  64
  131. --**  Unified Cache       1, Level 2,    6 MB, Assoc  24, LineSize  64
  132.  
  133. Logical Processor to Group Map:
  134. ****  Group 0
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