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JoshDreamland

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JoshDreamland
Apr 28th, 2012
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  1. <p>
  2. <span style="color:#ff0000"><b>OPCODE</b></span>(6b),
  3. <span style="color:#ff6600"><b>FORMAT</b></span>(1b),
  4. <span style="color:#009900"><b>IS_LITERAL</b></span>(1b),
  5. <span style="color:#339999"><b>SOURCE</b></span>(4b),
  6. <span style="color:#3333ff"><b>DESTINATION</b></span>(4b),
  7. <span style="color:#cc33cc"><b>DATA</b></span>(16b).
  8. </p>
  9.  
  10. <p>This structure allows for easy hand-assembly, as the only nybble sharing is between the opcode and format. For example, <tt>MOVD FR:1, DR:2;</tt> assembles to
  11. <span style="color:#ff0000">0</span><span style="color:#ff6600">0</span><span style="color:#339999">1</span><span style="color:#3333ff">2</span><span style="color:#cc33cc">0000</span>.</p>
  12.  
  13. The <span style="color:#339999"><b>SOURCE</b></span> and
  14. <span style="color:#3333ff"><b>DESTINATION</b></span> nybbles
  15. are identical; they are laid out as a single bit representing
  16. the type of the item followed by three bits for the register number.<br>
  17.  
  18. <ul>
  19.   <li><b>0</b> <i>000</i> - <b>0</b> <i>111</i> Are arithmetic registers 0 - 7, as specified in H3.1.</li>
  20.   <li><b>1</b> <i>001</i> - <b>1</b> <i>111</i> Are index registers, 1 - 7, as specified in H3.2.</li>
  21.   <li><b>1</b> <i>000</i> Is an invalid index register, and is used to indicate that the <span style="color:#cc33cc"><b>DATA</b></span> member is used.</li>
  22. </ul>
  23.  
  24. <p>The <span style="color:#cc33cc"><b>DATA</b></span> field is sixteen
  25. bits, and is only used as described in the points above. If the
  26. <span style="color:#009900"><b>IS_LITERAL</b></span> bit is set, all sixteen bits of the
  27. <span style="color:#cc33cc"><b>DATA</b></span> member are used as the literal,
  28. and the value can range from -32768 to 32767 as per specification H4. If the
  29. <span style="color:#009900"><b>IS_LITERAL</b></span> bit is not set, then the
  30. <span style="color:#cc33cc"><b>DATA</b></span> member is broken into an indexed
  31. address; the first nybble gives the index register, or zero for none, and the next
  32. three nybbles denote the address. Should the size of the memory for the machine grow,
  33. a bit can be removed from the first nybble and given to the second.</p>
  34.  
  35. An illustration of the breakdown of this format is given in the following table:
  36. <table>
  37.   <tr>
  38.     <th>Format</th>
  39.     <td colspan="6"><span style="color:#ff0000"><b>OPCODE</b></span>       </td>
  40.     <td colspan="1"><span style="color:#ff6600"><b>FORMAT</b></span>       </td>
  41.     <td colspan="1"><span style="color:#009900"><b>IS_LITERAL</b></span>   </td>
  42.     <td colspan="4"><span style="color:#339999"><b>SOURCE</b></span>       </td>
  43.     <td colspan="4"><span style="color:#3333ff"><b>DESTINATION</b></span>  </td>
  44.     <td colspan="16><span style="color:#cc33cc"><b>DATA</b></span>        </td>
  45.   </tr>
  46.   <tr>
  47.     <th rowspan="2">Memory</th>
  48.     <td colspan="6">OP Code</td>
  49.     <td colspan="2">Format</td>
  50.     <td colspan="1">Index?</td>
  51.     <td colspan="3">Register</td>
  52.     <td colspan="1">Index?</td>
  53.     <td colspan="3">Register</td>
  54.     <td colspan="3">IXR</td>
  55.     <td colspan="12">Memory address</td>
  56.   </tr>
  57.   <tr>
  58.     <td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
  59.     <td>0</td><td>0</td>
  60.     <td>1</td><td>0</td><td>0</td><td>0</td>
  61.     <td>0</td><td>0</td><td>0</td><td>0</td>
  62.     <td>0</td><td>0</td><td>0</td><td>0</td>
  63.     <td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
  64.   </tr>
  65.   <tr>
  66.     <th rowspan="2">Literal</th>
  67.     <td colspan="6">OP Code</td>
  68.     <td colspan="2">Format</td>
  69.     <td colspan="1">Index?</td>
  70.     <td colspan="3">Register</td>
  71.     <td colspan="1">Index?</td>
  72.     <td colspan="3">Register</td>
  73.     <td colspan="16">Literal</td>
  74.   </tr>
  75.   <tr>
  76.     <td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
  77.     <td>0</td><td>1</td>
  78.     <td>1</td><td>0</td><td>0</td><td>0</td>
  79.     <td>0</td><td>0</td><td>0</td><td>0</td>
  80.     <td>0</td><td>0</td><td>0</td><td>0</td>
  81.     <td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
  82.   </tr>
  83.   <tr>
  84.     <th rowspan="2">HLT/DMP</th>
  85.     <td colspan="6">OP Code</td>
  86.     <td colspan="2">Format</td>
  87.     <td colspan="4">Unused</td>
  88.     <td colspan="4">Unused</td>
  89.     <td colspan="16">Literal</td>
  90.   </tr>
  91.   <tr>
  92.     <td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
  93.     <td>0</td><td>1</td>
  94.     <td>0</td><td>0</td><td>0</td><td>0</td>
  95.     <td>0</td><td>0</td><td>0</td><td>0</td>
  96.     <td>0</td><td>0</td><td>0</td><td>0</td>
  97.     <td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
  98.   </tr>
  99.  
  100.  
  101.   <tr>
  102.     <th rowspan="2">Memory - Memory</th>
  103.     <td colspan="6">OP Code</td>
  104.     <td colspan="2">Format</td>
  105.     <td colspan="1">Index?</td>
  106.     <td colspan="3">Register</td>
  107.     <td colspan="1">Index?</td>
  108.     <td colspan="3">Register</td>
  109.     <td colspan="16">Literal</td>
  110.   </tr>
  111.   <tr>
  112.     <td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
  113.     <td>1</td><td>0</td>
  114.     <td>1</td><td>0</td><td>0</td><td>0</td>
  115.     <td>0</td><td>0</td><td>0</td><td>0</td>
  116.     <td>0</td><td>0</td><td>0</td><td>0</td>
  117.     <td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
  118.   </tr>
  119. </table>
  120.  
  121. Combinations that can not be used in the above formats include the following:<br>
  122. <ul>
  123.   <li>Indexed memory with memory: FM,DM,DX; <i>or</i> FM,FX,DM<br></li>
  124.   <li>Indexed memory with indexed memory: FM,FX,DM,DX;</li>
  125.   <li>Literal and indexed memory: FL,DM,DX;</li>
  126.   <li>Dual-destination transfers: FR,DR,DX; <i>or</i> FM,DR,DX<br></li>
  127. </ul>
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