`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.10.2018 18:59:12
// Design Name:
// Module Name: pll
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module pll(

  input clk,
  input ref_clk,
  output logic dac_sync,
  output logic dac_din
  );

// REF CLK DIV BY 125

logic ref_clk_div_out;

clk_odd_div(

.clk(ref_clk),
.reset(1'b0),
.clk_out(ref_clk_div_out)

);

//VCSO CLK DIV BY 3072

logic [11:0] clk_count;
logic clk_div_out;

always @ (posedge clk) begin
clk_count <= clk_count + 1;

 if(clk_count == 1536) begin
     clk_div_out <= !clk_div_out;
     clk_count <= 0;
 end
end


//PHASE DETECTOR

logic up, down;
logic reset, xored;

always @ (posedge ref_clk_div_out or posedge reset) begin
    if(reset) begin
        up <= 0;
    end else begin
        up <= 1;
    end
end

always @ (posedge clk_div_out or posedge reset) begin
    if(reset) begin
        down <= 0;
    end else begin
        down <= 1;
    end
end



always @ * begin

    reset <= up & down;
    xored <= up ^ down;

end

//ERR COUNTER
logic [15:0] vio;
logic [15:0] int_cnt;
logic int_clk;

always @ (posedge clk) begin
int_cnt <= int_cnt + 1;

 if(int_cnt == vio) begin
     int_clk <= !int_clk;
     int_cnt <= 0;
 end
end


logic [15:0] alpha;
logic [15:0] beta;
logic [15:0] dacd;

logic flagup;
logic flagdn;
logic [7:0] upcnt;
logic [7:0] dncnt;

logic [8:0] phase_err;

always @ (posedge int_clk) begin
    if(up) begin
        if(!flagup) begin
            upcnt <= 8'b1;
            flagup <= 1'b1;
        end else begin
            upcnt <= upcnt + 1;
        end
    end else begin
    flagup <= 1'b0;
    end
end

always @ (posedge int_clk) begin
    if(down) begin
        if(!flagdn) begin
            dncnt <= 8'b1;
            flagdn <= 1'b1;
        end else begin
            dncnt <= dncnt + 1;
        end
    end else begin
    flagdn <= 1'b0;
    end
end

always @ * phase_err <= upcnt - dncnt;



pll_filter_0 (
  .data_in(phase_err),    // input wire [15 : 0] data_in
  .beta(beta),        // input wire [15 : 0] betha
  .alpha(alpha),        // input wire [15 : 0] alpha
  .clk(dac_sync),            // input wire clk
  .data_out(dacd)  // output wire [15 : 0] data_out
);






 //DAC_SPI_TX
 ad5060 dac(
   .clk(ref_clk),
   .data(dacd),
   .dac_sync(dac_sync),
   .dac_din(dac_din)
 );

vio_0  (
  .clk(clk),                // input wire clk
  .probe_out0(vio),  // output wire [15 : 0] probe_out0
  .probe_out1(alpha),  // output wire [15 : 0] probe_out1
  .probe_out2(beta)  // output wire [15 : 0] probe_out2
);


ila_0(
     .clk(clk),

     .probe0(up),
     .probe1(down),
     .probe2(ref_clk_div_out),
     .probe3({7'b0,phase_err})
 );

endmodule