digital_lock_tb.sv

`timescale 1ns/1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/30/2024 02:37:20 PM
// Design Name:
// Module Name: digital_lock_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

task automatic pulse;
    ref reg clock;
    begin
        clock = 1'b1;
        #10;
        clock = 1'b0;
        #10;
    end
endtask

task automatic set_codes;
    input [3:0] codes [3:0];
    ref reg [3:0] code;
    ref reg clock;
    ref reg mode;
    integer i;
    begin
        mode = 1'b1;
        for (i = 0; i < 4; i = i + 1) begin
            code = codes[i];
            pulse(clock);
        end
    end
endtask

task automatic verify_codes(
        input [3:0] codes [3:0],
        ref reg [3:0] code,
        ref logic clock,
        ref reg mode
    );

    integer i;
    begin
        mode = 1'b0;
        for (i = 0; i < 4; i = i + 1) begin
            code = codes[i];
            pulse(clock);
        end
    end
endtask

module digital_lock_tb();
    reg clock;
    reg reset;
    reg [3:0] code;
    reg mode;
    wire unlock;
    wire error;

    initial begin
        // Initialize signals
        clock = 1'b0;
        reset = 1'b1;
        code = 4'b0000;
        mode = 1'b0;

        reset = 1'b0;
        #10;
        pulse(reset);

        // Verify sudo codes
        verify_codes({4'b0000, 4'b0000, 4'b0000, 4'b0000}, code, clock, mode);

        // Set codes
        set_codes({4'b0001, 4'b0010, 4'b0011, 4'b0100}, code, clock, mode);

        // One error
        verify_codes({4'b1010, 4'b1011, 4'b1100, 4'b1101}, code, clock, mode);

        // Verify user codes
        verify_codes({4'b0001, 4'b0010, 4'b0011, 4'b0100}, code, clock, mode);

        // Three error in a row
        verify_codes({4'b1010, 4'b1011, 4'b1100, 4'b1101}, code, clock, mode);
        verify_codes({4'b1010, 4'b1011, 4'b1100, 4'b1101}, code, clock, mode);
        verify_codes({4'b1010, 4'b1011, 4'b1100, 4'b1101}, code, clock, mode);

        // Test if user codes work
        verify_codes({4'b0001, 4'b0010, 4'b0011, 4'b0100}, code, clock, mode);

        // Reset when dead
        pulse(reset);

        // Test after reset
        verify_codes({4'b0001, 4'b0010, 4'b0011, 4'b0100}, code, clock, mode);

        // Test if sudo codes work
        verify_codes({4'b0000, 4'b0000, 4'b0000, 4'b0000}, code, clock, mode);

        // Finish simulation
        #100;
        $finish;
    end

    digital_lock uut(
        .clock(clock),
        .reset(reset),
        .code(code),
        .mode(mode),
        .unlock(unlock),
        .error(error)
    );

endmodule