library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY zbrajalo IS PORT(
	a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	oper: IN STD_LOGIC;
	r: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	cout: OUT STD_LOGIC
);
END zbrajalo;

ARCHITECTURE arch OF zbrajalo IS

SIGNAL i: STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN

fa1: entity work.primitiv PORT MAP(a(1 DOWNTO 0),b(1 DOWNTO 0),oper,oper,r(1 DOWNTO 0),i(0));
fa2: entity work.primitiv PORT MAP(a(3 DOWNTO 2),b(3 DOWNTO 2),oper,i(0),r(3 DOWNTO 2),i(1));
fa3: entity work.primitiv PORT MAP(a(5 DOWNTO 4),b(5 DOWNTO 4),oper,i(1),r(5 DOWNTO 4),i(2));
fa4: entity work.primitiv PORT MAP(a(7 DOWNTO 6),b(7 DOWNTO 6),oper,i(2),r(7 DOWNTO 6),cout);

END arch;