library ieee;
library altera_mf;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use altera_mf.altera_mf_components.all;
entity Pipeline is
    port(
        clock           : in std_logic;
        reset          : in std_logic;
		  IO_DATA		   : out std_logic_vector(31 downto 0);
		  IO_WRITE			: out std_logic;
		  dbg_fbufopcode : out std_logic_vector(31 downto 0);
		  dbg_dbufopcode : out std_logic_vector(6 downto 0);
		  dbg_ebufopcode : out std_logic_vector(6 downto 0);
		  dbg_mbufopcode : out std_logic_vector(6 downto 0)
    );
end Pipeline;

architecture a of Pipeline is

signal     exresult : std_logic_vector(31 downto 0);
signal     branchmux : std_logic;

signal     fetchPC : std_logic_vector(31 downto 0);
signal     fetchinstruction : std_logic_vector(31 downto 0);

signal     fbufPC : std_logic_vector(31 downto 0);
signal     fbufinstruction : std_logic_vector(31 downto 0);

signal     decodeopcode : std_logic_vector(6 downto 0);
signal     decoderd : std_logic_vector(4 downto 0);
signal     decoders1 : std_logic_vector(4 downto 0);
signal     decoders2 : std_logic_vector(4 downto 0);
signal     decodereadrs1 : std_logic_vector(31 downto 0);
signal     decodereadrs2 : std_logic_vector(31 downto 0);
signal     decodeimm : std_logic_vector(31 downto 0);
signal     decodefunct3 : std_logic_vector(2 downto 0);
signal     decodefunct7 : std_logic_vector(6 downto 0);

signal     dbufPC : std_logic_vector(31 downto 0);
signal     dbufopcode : std_logic_vector(6 downto 0);
signal     dbufrd : std_logic_vector(4 downto 0);
signal     dbufreadrs1 : std_logic_vector(31 downto 0);
signal     dbufreadrs2 : std_logic_vector(31 downto 0);
signal     dbufimm : std_logic_vector(31 downto 0);
signal     dbuffunct3 : std_logic_vector(2 downto 0);
signal     dbuffunct7 : std_logic_vector(6 downto 0);


signal     ebufopcode : std_logic_vector(6 downto 0);
signal     ebufrd : std_logic_vector(4 downto 0);
signal     ebufreadrs1 : std_logic_vector(31 downto 0);
signal     ebufreadrs2 : std_logic_vector(31 downto 0);
signal     ebufimm : std_logic_vector(31 downto 0);
signal     ebufresult : std_logic_vector(31 downto 0);
signal     ebuffunct3 : std_logic_vector(2 downto 0);
signal     ebuffunct7 : std_logic_vector(6 downto 0);

signal     memresult : std_logic_vector(31 downto 0);
signal     mbufopcode : std_logic_vector(6 downto 0);
signal     mbufrd : std_logic_vector(4 downto 0);
signal     mbufresult : std_logic_vector(31 downto 0);

signal     wren : std_logic;
signal     wrdata : std_logic_vector(31 downto 0);
signal     wraddress : std_logic_vector(4 downto 0);
	begin
	    IO_DATA <= exresult;

		dbg_fbufopcode <= fbufinstruction;
		dbg_dbufopcode <= dbufopcode;
		dbg_ebufopcode <= ebufopcode;
		dbg_mbufopcode <= mbufopcode;

        fetch : entity work.InstructionFetch
        PORT MAP (
            clock,
            reset,
            exresult,
            branchmux,
            fetchPC,
            fetchinstruction
        );

        fetchbuffer : entity work.FBUF
        PORT MAP (
            clock,
            reset,
            fetchPC,
            fetchinstruction,
            fbufPC,
            fbufinstruction
        );

        decode : entity work.InstructionDecode
        PORT MAP (
            fbufinstruction,
            decodeopcode,
            decoderd,
            decoders1,
            decoders2,
            decodeimm,
            decodefunct3,
            decodefunct7
        );

        dbuf : entity work.DBUF
        PORT MAP (
            clock,
            reset,
            fbufPC,
            decodeopcode,
            decoderd,
            decodereadrs1,
            decodereadrs2,
            decodeimm,
            decodefunct3,
            decodefunct7,
            dbufPC,
            dbufopcode,
            dbufrd,
            dbufreadrs1,
            dbufreadrs2,
            dbufimm,
            dbuffunct3,
            dbuffunct7
        );

        ex : entity work.Execute
        PORT MAP (
            dbufPC,
            dbufopcode,
            dbufrd,
            dbufreadrs1,
            dbufreadrs2,
            dbufimm,
            dbuffunct3,
            dbuffunct7,
            branchmux,
            exresult,
            IO_WRITE
        );

        ebuf : entity work.EBUF
        PORT MAP (
            clock,
            reset,
            dbufopcode,
            dbufrd,
            dbufreadrs1,
            dbufreadrs2,
            dbufimm,
            dbuffunct3,
            dbuffunct7,
            exresult,
            ebufopcode,
            ebufrd,
            ebufreadrs1,
            ebufreadrs2,
            ebufimm,
            ebufresult,
            ebuffunct3,
            ebuffunct7
        );

        mem : entity work.Memory
        PORT MAP (
            clock,
            reset,
            ebufopcode,
            ebuffunct3,
            ebufreadrs2,
            ebufresult,
            memresult
        );

        mbuf : entity work.MBUF
        PORT MAP (
            clock,
            reset,
            ebufopcode,
            ebufrd,
            memresult,
            mbufopcode,
            mbufrd,
            mbufresult
        );

        wb : entity work.Writeback
        PORT MAP (
            mbufopcode,
            mbufrd,
            mbufresult,
            wren,
            wrdata,
            wraddress
        );

        regfile : entity work.DPRF
        PORT MAP (
            clock,
            reset,
            wren,
            decoders1,
            decoders2,
            wraddress,
            wrdata,
            decodereadrs1,
            decodereadrs2
        );

end a;
library ieee;
library altera_mf;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use altera_mf.altera_mf_components.all;
entity InstructionFetch is
    port(
        clock           : in std_logic;
        reset          : in std_logic;
        branch          : in std_logic_vector(31 downto 0);
		branch_mux		: in std_logic;
        PC              : out std_logic_vector(31 downto 0);
        instruction     : out std_logic_vector(31 downto 0)
    );
end InstructionFetch;

architecture a of InstructionFetch is

    signal program_counter  : std_logic_vector(31 downto 0);
    signal data             : std_logic_vector(31 downto 0);
    signal wren             : std_logic;
	begin

        altsyncram_component : altsyncram
        GENERIC MAP (
            clock_enable_input_a => "BYPASS",
            clock_enable_output_a => "BYPASS",
            init_file => "program.mif",
            intended_device_family => "MAX 10",
            lpm_hint => "ENABLE_RUNTIME_MOD=NO",
            lpm_type => "altsyncram",
            numwords_a => 1024,
            operation_mode => "SINGLE_PORT",
            outdata_aclr_a => "CLEAR0",
            outdata_reg_a => "UNREGISTERED",
            power_up_uninitialized => "FALSE",
            read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
            widthad_a => 10,
            width_a => 32,
            width_byteena_a => 1
        )
        PORT MAP (
            aclr0 => reset,
            address_a => program_counter(9 downto 0),
            clock0 => clock,
            data_a => data,
            wren_a => wren,
            q_a => instruction
        );

        PC <= program_counter;

        process (clock, reset)
        begin
            if (rising_edge(clock)) then
				    if (reset = '1') then
						  program_counter <= (others => '0');
					 else
						 case branch_mux is
							  when '0' =>
									program_counter <= program_counter + 1;
							  when '1' =>
									program_counter <= branch;
						 end case;
					 end if;
            end if;
        end process;
end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FBUF is
    port(
        clock           : in std_logic;
        reset          : in std_logic;
        PCin              : in std_logic_vector(31 downto 0);
        instructionin     : in std_logic_vector(31 downto 0);
        PCout              : out std_logic_vector(31 downto 0);
        instructionout     : out std_logic_vector(31 downto 0)
    );
end FBUF;

architecture a of FBUF is

    signal PC : std_logic_vector(31 downto 0);
    signal instruction : std_logic_vector(31 downto 0);
	begin


        PCout <= PC;
        instructionout <= instruction;

        process (clock, reset)
        begin
            if (rising_edge(clock)) then
					 if (reset = '1') then
						PC <= (others => '0');
						instruction <= (others => '0');
                else
						PC <= PCin;
						instruction <= std_logic_vector(instructionin);
					 end if;
            end if;
        end process;
end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity InstructionDecode is
    port(
        instruction     : in std_logic_vector(31 downto 0);
        opcode          : out std_logic_vector(6 downto 0);
        rd              : out std_logic_vector(4 downto 0);
        rs1             : out std_logic_vector(4 downto 0);
        rs2             : out std_logic_vector(4 downto 0);
        imm             : out std_logic_vector(31 downto 0);
        funct3          : out std_logic_vector(2 downto 0);
        funct7          : out std_logic_vector(6 downto 0)
    );
end InstructionDecode;

architecture a of InstructionDecode is

	begin

        opcode <= instruction(6 downto 0);
        rd     <= instruction(11 downto 7);
        rs1    <= instruction(19 downto 15);
        rs2    <= instruction(24 downto 20);
        funct3 <= instruction(14 downto 12);
        funct7 <= instruction(31 downto 25);
        with instruction(6 downto 0) select
            imm <= instruction(31 downto 12) & (11 downto 0 => '0') when "0110111",
                   instruction(31 downto 12) & (11 downto 0 => '0') when "0010111",
                   (11 downto 0 => instruction(31)) & instruction(19 downto 12) & instruction(20) & instruction(30 downto 21) & '0' when "1101111",
                   (19 downto 0 => instruction(31)) & instruction(31 downto 20) when "1100111",
                   (19 downto 0 => instruction(31)) & instruction(7) & instruction(30 downto 25) & instruction(11 downto 8) & '0' when "1100011",
                   (19 downto 0 => instruction(31)) & instruction(31 downto 20) when "0000011",
                   (19 downto 0 => instruction(31)) & instruction(31 downto 25) & instruction(11 downto 7) when "0100011",
                   (19 downto 0 => instruction(31)) & instruction(31 downto 20) when "0010011",
                   (others => '0') when others;

end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DBUF is
    port(
        clock             : in std_logic;
        reset            : in std_logic;
        PCin              : in std_logic_vector(31 downto 0);
        opcodein          : in std_logic_vector(6 downto 0);
        rdin              : in std_logic_vector(4 downto 0);
        readrs1in         : in std_logic_vector(31 downto 0);
        readrs2in         : in std_logic_vector(31 downto 0);
        immin             : in std_logic_vector(31 downto 0);
        funct3in          : in std_logic_vector(2 downto 0);
        funct7in          : in std_logic_vector(6 downto 0);
        PCout              : out std_logic_vector(31 downto 0);
        opcodeout          : out std_logic_vector(6 downto 0);
        rdout              : out std_logic_vector(4 downto 0);
        readrs1out         : out std_logic_vector(31 downto 0);
        readrs2out         : out std_logic_vector(31 downto 0);
        immout             : out std_logic_vector(31 downto 0);
        funct3out          : out std_logic_vector(2 downto 0);
        funct7out          : out std_logic_vector(6 downto 0)
    );
end DBUF;

architecture a of DBUF is

    signal PC : std_logic_vector(31 downto 0);
    signal opcode : std_logic_vector(6 downto 0);
    signal rd : std_logic_vector(4 downto 0);
    signal readrs1 : std_logic_vector(31 downto 0);
    signal readrs2 : std_logic_vector(31 downto 0);
    signal imm : std_logic_vector(31 downto 0);
    signal funct3 : std_logic_vector(2 downto 0);
    signal funct7 : std_logic_vector(6 downto 0);

	begin

        PCout <= PC;
		  opcodeout <= opcode;
        rdout <= rd;
        readrs1out <= readrs1;
        readrs2out <= readrs2;
        immout <= imm;
        funct3out <= funct3;
        funct7out <= funct7;

        process (clock, reset)
        begin


            if (rising_edge(clock)) then
				    if (reset = '1') then
						 PC <= (others => '0');
						 opcode <= (others => '0');
						 rd <= (others => '0');
						 readrs1 <= (others => '0');
						 readrs2 <= (others => '0');
						 imm <= (others => '0');
						 funct3 <= (others => '0');
						 funct7 <= (others => '0');
					 else
						 PC <= PCin;
						 opcode <= opcodein;
						 rd <= rdin;
						 readrs1 <= readrs1in;
						 readrs2 <= readrs2in;
						 imm <= immin;
						 funct3 <= funct3in;
						 funct7 <= funct7in;
					 end if;
            end if;
        end process;

end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Execute is
    port(
		  PC					: in std_logic_vector(31 downto 0);
		  opcode          : in std_logic_vector(6 downto 0);
        rd              : in std_logic_vector(4 downto 0);
        readrs1,
        readrs2			: in std_logic_vector(31 downto 0);

        imm             : in std_logic_vector(31 downto 0);
        funct3          : in std_logic_vector(2 downto 0);
        funct7          : in std_logic_vector(6 downto 0);
		  branchmux       : out std_logic;
        result          : out std_logic_vector(31 downto 0);
		  IO_WRITE			: out std_logic
    );
end Execute;

architecture a of Execute is
    signal exresulti : std_logic_vector(31 downto 0);
    signal exresultr : std_logic_vector(31 downto 0);
	 signal subimm       : std_logic_vector(31 downto 0);
	 signal comparisonimm : std_logic;
	 signal subreg       : std_logic_vector(31 downto 0);
	 signal comparisonreg : std_logic;
	begin
		  subimm <= readrs1 - imm;
		  comparisonimm <= '1' when (unsigned(readrs1) < unsigned(imm)) else '0';
		  subreg <= readrs1 - readrs2;
		  comparisonreg <= '1' when (unsigned(readrs1) < unsigned(readrs2)) else '0';
        exresulti <=  (readrs1 + imm) when funct3 = "000" else
                      (30 downto 0 => '0') & subimm(31) when funct3 = "010" else
                      (30 downto 0 => '0') & comparisonimm when funct3 = "011" else
                      (readrs1 xor imm) when funct3 = "100" else
                      (readrs1 or imm) when funct3 = "110" else
                      (readrs1 and imm) when funct3 = "111" else
                      std_logic_vector(shift_left(unsigned(readrs1), to_integer(unsigned(imm(4 downto 0))))) when funct3 = "001" else
                      std_logic_vector(shift_right(unsigned(readrs1), to_integer(unsigned(imm(4 downto 0))))) when funct7(5) = '1' and funct3 = "101" else
                      std_logic_vector(shift_right(signed(readrs1), to_integer(unsigned(imm(4 downto 0))))) when funct7(5) = '0' and funct3 = "101" else
                      (others => '0');

        exresultr <=  (readrs1 + readrs2) when funct3 = "000" and funct7(5) = '0' else
                      subreg when funct3 = "000" and funct7(5) = '1' else
                      std_logic_vector(shift_left(unsigned(readrs1), to_integer(unsigned(readrs2(4 downto 0))))) when funct3 = "001" else
                      (30 downto 0 => '0') & subreg(31) when funct3 = "010" else
                      (30 downto 0 => '0') & comparisonreg when funct3 = "011" else
                      (readrs1 xor readrs2) when funct3 = "100" else
                      std_logic_vector(shift_right(unsigned(readrs1), to_integer(unsigned(readrs2)))) when funct3 = "101" and funct7(5) = '0' else
                      std_logic_vector(shift_right(signed(readrs1), to_integer(unsigned(readrs2)))) when funct3 = "101" and funct7(5) = '1' else
                      (readrs1 or readrs2) when funct3 = "110" else
                      (readrs1 and readrs2) when funct3 = "111" else
                      (others => '0');
		  branchmux <= '1' when opcode = "1101111" or opcode = "1100111" or opcode = "1100011" else '0';
		  IO_WRITE <= '1' when opcode = "0000001" else '0';
        with opcode select
            result <= imm when "0110111",
                      imm + PC when "0010111",
                      imm + PC when "1101111",
                      readrs1 + imm when "1100111",
                      readrs2 - readrs1 when "1100011",
                      readrs1 + imm when "0000011",
                      readrs1 + imm when "0100011",

                      exresulti when "0010011",
                      exresultr when "0110011",
							 readrs1 when "0000001",
                      (others => '0') when others;

end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity EBUF is
    port(
        clock             : in std_logic;
        reset            : in std_logic;
        opcodein          : in std_logic_vector(6 downto 0);
        rdin              : in std_logic_vector(4 downto 0);
        readrs1in         : in std_logic_vector(31 downto 0);
        readrs2in         : in std_logic_vector(31 downto 0);
        immin             : in std_logic_vector(31 downto 0);

        funct3in          : in std_logic_vector(2 downto 0);
        funct7in          : in std_logic_vector(6 downto 0);
		  exresultin        : in std_logic_vector(31 downto 0);
        opcodeout          : out std_logic_vector(6 downto 0);
        rdout              : out std_logic_vector(4 downto 0);
        readrs1out         : out std_logic_vector(31 downto 0);
        readrs2out         : out std_logic_vector(31 downto 0);
        immout             : out std_logic_vector(31 downto 0);
        exresultout        : out std_logic_vector(31 downto 0);
        funct3out          : out std_logic_vector(2 downto 0);
        funct7out          : out std_logic_vector(6 downto 0)
    );
end EBUF;

architecture a of EBUF is

    signal PC : std_logic_vector(31 downto 0);
    signal opcode : std_logic_vector(6 downto 0) := "0000000";
    signal rd : std_logic_vector(4 downto 0);
    signal readrs1 : std_logic_vector(31 downto 0);
    signal readrs2 : std_logic_vector(31 downto 0);
    signal imm : std_logic_vector(31 downto 0);
    signal exresult : std_logic_vector(31 downto 0);
    signal funct3 : std_logic_vector(2 downto 0);
    signal funct7 : std_logic_vector(6 downto 0);

	begin

 		  opcodeout <= opcode;
        rdout <= rd;
        readrs1out <= readrs1;
        readrs2out <= readrs2;
        immout <= imm;
        exresultout <= exresult;
        funct3out <= funct3;
        funct7out <= funct7;

        process (clock, reset)
        begin


            if (rising_edge(clock)) then
				    if (reset = '1') then
						 opcode <= (others => '0');
						 rd <= (others => '0');
						 readrs1 <= (others => '0');
						 readrs2 <= (others => '0');
						 imm <= (others => '0');
						 exresult <= (others => '0');
						 funct3 <= (others => '0');
						 funct7 <= (others => '0');
					 else
						 opcode <= opcodein;
						 rd <= rdin;
						 readrs1 <= readrs1in;
						 readrs2 <= readrs2in;
						 imm <= immin;
						 exresult <= exresultin;
						 funct3 <= funct3in;
						 funct7 <= funct7in;
					 end if;
            end if;
        end process;

end a;
library ieee;
library altera_mf;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use altera_mf.altera_mf_components.all;
entity Memory is
    port(
        clock           : in std_logic;
        reset          : in std_logic;
        opcode          : in std_logic_vector(6 downto 0);
        funct3          : in std_logic_vector(2 downto 0);
        readrs2         : in std_logic_vector(31 downto 0);
        ex_result       : in std_logic_vector(31 downto 0);
        mem_result      : out std_logic_vector(31 downto 0)
    );
end Memory;

architecture a of Memory is

    signal read_data        : std_logic_vector(31 downto 0);
    signal mem_out          : std_logic_vector(31 downto 0);
    signal byteena          : std_logic_vector(3 downto 0);
    signal wren             : std_logic;
	begin


	altsyncram_component : altsyncram
	GENERIC MAP (
		byte_size => 8,
		clock_enable_input_a => "BYPASS",
		clock_enable_output_a => "BYPASS",
		init_file => "memory.mif",
		intended_device_family => "MAX 10",
		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
		lpm_type => "altsyncram",
		numwords_a => 1024,
		operation_mode => "SINGLE_PORT",
		outdata_aclr_a => "CLEAR0",
		outdata_reg_a => "UNREGISTERED",
		power_up_uninitialized => "FALSE",
		read_during_write_mode_port_a => "OLD_DATA",
		widthad_a => 10,
		width_a => 32,
		width_byteena_a => 4
	)
	PORT MAP (
		aclr0 => reset,
		address_a => ex_result(9 downto 0),
		byteena_a => byteena,
		clock0 => clock,
		data_a => readrs2,
		wren_a => wren,
		q_a => read_data
	);
        wren <= '1' when opcode = "0100011" else '0';

        byteena <= "0001" when funct3(1 downto 0) = "00" else
                   "0011" when funct3(1 downto 0) = "01" else
                   "1111" when funct3(1 downto 0) = "10" else
                   "0000";

        mem_out <= (31 downto 8 => read_data(7) and (not funct3(2))) & read_data(7 downto 0) when funct3(1 downto 0) = "00" else
                   (31 downto 16 => read_data(7) and (not funct3(2))) & read_data(15 downto 0) when funct3(1 downto 0) = "01" else
                   read_data;

        mem_result <= mem_out when opcode = "0000011" else
                      ex_result;
end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MBUF is
    port(
        clock             : in std_logic;
        reset            : in std_logic;
        opcodein          : in std_logic_vector(6 downto 0);
        rdin              : in std_logic_vector(4 downto 0);
        memresultin        : in std_logic_vector(31 downto 0);
        opcodeout          : out std_logic_vector(6 downto 0);
        rdout              : out std_logic_vector(4 downto 0);
        memresultout        : out std_logic_vector(31 downto 0)
    );
end MBUF;

architecture a of MBUF is

    signal opcode : std_logic_vector(6 downto 0);
    signal rd : std_logic_vector(4 downto 0);
    signal memresult : std_logic_vector(31 downto 0);

	begin

        opcodeout <= opcode;
        rdout <= rd;
        memresultout <= memresult;

        process (clock, reset)
        begin
            if (rising_edge(clock)) then
				    if (reset = '1') then
						 opcode <= (others => '0');
						 rd <= (others => '0');
						 memresult <= (others => '0');
					 else
						 opcode <= opcodein;
						 rd <= rdin;
						 memresult <= memresultin;
					 end if;
            end if;
        end process;

end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Writeback is
    port(
        opcode          : in std_logic_vector(6 downto 0);
        rd              : in std_logic_vector(4 downto 0);

		  mem_result      : in std_logic_vector(31 downto 0);
        wren            : out std_logic;
        wrdata          : out std_logic_vector(31 downto 0);
        wraddress       : out std_logic_vector(4 downto 0)
    );
end Writeback;

architecture a of Writeback is

	begin

        wrdata <= mem_result;
        wraddress <= rd;
        wren <= '1' when opcode = "0110111" or
                         opcode = "0010111" or
                         opcode = "1101111" or
                         opcode = "1100111" or
                         opcode = "0000011" or
                         opcode = "0010011" or
                         opcode = "0110011" else
                '0';


end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity DPRF is
    port(
        clock           : in std_logic;
        reset          : in std_logic;
        wren            : in std_logic;
        rs1             : in std_logic_vector(4 downto 0);
        rs2             : in std_logic_vector(4 downto 0);
        wraddress       : in std_logic_vector(4 downto 0);
        wrdata          : in std_logic_vector(31 downto 0);
        readrs1         : out std_logic_vector(31 downto 0);
        readrs2         : out std_logic_vector(31 downto 0)
    );
end DPRF;

architecture a of DPRF is

    type RegisterFile is array (31 downto 0) of std_logic_vector(31 downto 0);
    signal registers : RegisterFile;
	 begin
    readrs1 <= registers(to_integer(unsigned(rs1)));
    readrs2 <= registers(to_integer(unsigned(rs2)));

    process (clock, reset)
    begin
        if (reset = '1') then
            for i in registers'range loop
                registers(i) <= (others => '0');
            end loop;
        elsif (rising_edge(clock) and wren = '1' and wraddress /= "00000") then
            registers(to_integer(unsigned(wraddress))) <= wrdata;
        end if;
    end process;

end a;