class CRG(Module):
    def __init__(self, platform, sys_clk_freq):
        self.rst = Signal()
        self.clock_domains.cd_sys       = ClockDomain()

        # Clk/Rst
        clk_in = platform.request("dram0_refclk")

        # PLL
        self.submodules.pll = pll = USMMCM(speedgrade=-1)
        pll.register_clkin(clk_in, 300e6)
        pll.create_clkout(self.cd_sys, sys_clk_freq)
        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.