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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 15:24:12 12/07/2015
- // Design Name:
- // Module Name: lab8fig2
- // Project Name:
- // Target Devices:
- // Tool versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- /*module test_circuit;
- reg [3:0] A;
- reg [3:0] B;
- reg [2:0] M;
- //reg [3:0] _V;
- wire [3:0] Sout;
- //wire [3:0] sub_S;
- wire V;
- _4bit_adder add(Sout, V, A, B, M);
- //lab8fig2(Ei_out, S0_in, S1_in, Ai_in, Bi_in);
- initial begin
- M = 3'b0;
- A = 4'b0111;
- B = 4'b0110;
- #50
- A = 4'b1000;
- B = 4'b1001;
- #50
- M = 3'b1;
- A = 4'b1100;
- B = 4'b1000;
- #50
- A = 4'b0101;
- B = 4'b1010;
- #50
- A = 4'b0000;
- B = 4'b0001;
- B = 4'b0000;
- #50 M = 3'b010; //increment
- #50 M = 3'b011; //decrement
- #50 M = 3'b100; //xfer
- end
- endmodule*/
- //Description of 4-bit adder (see Fig 4-9)
- module _4bit_adder(Sout, V, _A, _B, C0);
- input [3:0] _A, _B;
- input C0; //C0 is M
- output [3:0] Sout;
- output V; //overflow
- wire C1, C2, C3;
- fulladdersub FA0 (Sout[0],C1,_A[0],_B[0],C0,C0),
- FA1 (Sout[1],C2,_A[1],_B[1],C1,C0),
- FA2 (Sout[2],C3,_A[2],_B[2],C2,C0),
- FA3 (Sout[3],C4,_A[3],_B[3],C3,C0);
- xor (V,C3,C4);
- endmodule
- module fulladdersub (Sout, Cout, A, B, Cin, M);
- output Sout, Cout;
- input Cin, M, A, B;
- wire w1;
- // xor (w1,b,m);
- Multiplexor mux(w1,M,B|((~B) << 1)|(1 << 3));
- fulladder fa(Sout,Cout,A,w1,Cin);
- endmodule
- module Multiplexor(O,S,I);
- parameter S00 = 3'b0000,S01 = 3'b0001,S10 = 3'b0010,S11=3'b0011;
- output reg O;
- input [2:0] S;
- input [3:0] I;
- always @ (S,I)
- case(S)
- S00:O<=I[0];
- S01:O<=I[1];
- S10:O<=I[2];
- S11:O<=I[3];
- //default: O <= O;
- default O<=3'b000;
- endcase
- endmodule
- //4x1 MUX
- module mux41_bh(MUXout, i0, i1, i2, i3, s1, s0);
- //port declarations
- input i0, i1, i2, i3;
- input s1, s0;
- output reg MUXout;
- //using basic and, or, not logic operators
- always @(i0 or i1 or i2 or i3 or s1 or s0)
- MUXout = (~s1 & ~s0 & i0) |
- (~s1 & s0 & i1) |
- (s1 & ~ s0 & i2) |
- (s1 & s0 & i3);
- endmodule
- //Description of full adder (see Fig 4-8)
- module fulladder (Sout, Cout, x_in, y_in, z);
- input x_in, y_in, z;
- output Sout, Cout;
- wire S1, D1, D2; //Outputs of first XOR and two AND gates
- //Instantiate the halfadder
- halfadder HA1 (S1, D1, x_in, y_in),
- HA2 (Sout, D2, S1, z);
- or g1(Cout, D2, D1);
- endmodule
- module halfadder (S_out, C_out, x_in, y_in);
- input x_in, y_in;
- output S_out, C_out;
- //Instantiate primitive gates
- xor g5(S_out, x_in, y_in);
- and g6(C_out, x_in, y_in);
- endmodule
- module lab8fig2(Ei_out, S0_in, S1_in, Ai_in, Bi_in);
- input S0_in, S1_in, Ai_in, Bi_in;
- output Ei_out;
- and g1(w1, Ai_in, Bi_in);
- or g2 (w2, Ai_in, Bi_in);
- xor g3 (w3, Ai_in, Bi_in);
- not g4 (w4, Ai_in, Bi_in);
- //use one mux
- mux41_bh mux1 (Ei_out, S0_in, S1_in, w1, w2, w3, w4);
- endmodule
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