Lab5

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    14:04:54 07/27/2021
// Design Name:
// Module Name:    johnsonveri
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module a25hzclk(input clk,
                    input reset,
                    output a25clk
                    );
reg [24:0]ctr;
assign a25clk=ctr[24];

always@(posedge clk)
begin
if (reset) ctr=0;
else ctr=ctr+1;
end
endmodule

module a100hzclk(input clk,
                    input reset,
                    output a100clk
                    );
reg [20:0]ctr;
assign a100clk=ctr[17];

always@(posedge clk)
begin
if (reset) ctr=0;
else ctr=ctr+1;
end
endmodule


module johnson1(input clk,
                     input reset,
                     input reset1,
                     input reset2,
                     output reg [3:0] jctr,
                     output a25clk,
                     output a100clk,
                     output reg [3:0] x,
                     output reg [6:0] y
                     );

a25hzclk a25 (.clk(clk),.reset(reset),.a25clk(a25clk));

a100hzclk a100 (.clk(clk),.reset(reset2),.a100clk(a100clk));


reg [3:0] jc;
reg of1;
reg [15:0] sseg;
reg [1:0] ctr;



always@(posedge a25clk)
begin
if (reset1==1) begin
jctr=0;
end
else begin
/*{of1,jc}=jctr<<1;
jctr={jc[3],jc[2],jc[1],(~of1)};
*/
{jctr[3:1],jctr[0]}={jctr[2:0],~(jctr[3])};
{sseg[15:12],sseg[11:8],sseg[7:4],sseg[3:0]}={sseg[11:8],sseg[7:4],sseg[3:0],jctr};
end
end

always@(posedge a100clk)
begin
if (reset1==1) begin
x=4'b0111;
ctr=2'b0;
end

else begin
{x[3],x[2:0]}={x[0],x[3:1]};
ctr=ctr+1;

if (ctr==0)
begin
case(sseg[15:12])
0:y=7'b0000001;
1:y=7'b1001111;
3:y=7'b0000110;
7:y=7'b0001111;
8:y=7'b0000000;
12:y=7'b0110001;
14:y=7'b0110000;
15:y=7'b0111000;
endcase
end
else if (ctr==2'b01)
begin
case(sseg[11:8])
0:y=7'b0000001;
1:y=7'b1001111;
3:y=7'b0000110;
7:y=7'b0001111;
8:y=7'b0000000;
12:y=7'b0110001;
14:y=7'b0110000;
15:y=7'b0111000;
endcase
end
else if (ctr==2'b10)
begin
case(sseg[7:4])
0:y=7'b0000001;
1:y=7'b1001111;
3:y=7'b0000110;
7:y=7'b0001111;
8:y=7'b0000000;
12:y=7'b0110001;
14:y=7'b0110000;
15:y=7'b0111000;
endcase
end
else if (ctr==2'b11)
begin
case(sseg[3:0])
0:y=7'b0000001;
1:y=7'b1001111;
3:y=7'b0000110;
7:y=7'b0001111;
8:y=7'b0000000;
12:y=7'b0110001;
14:y=7'b0110000;
15:y=7'b0111000;
endcase
end
end
end
endmodule