DEVICE TREE EDITS FOR DISPLAY PORT ON ULTRAZED

#DEVICE TREE EDITS FOR DISPLAY PORT ON ULTRAZED

&xlnx_dp {
	status = "okay";
	phy-names = "dp-phy0", "dp-phy1";
	phys = 	<&lane3 PHY_TYPE_DP 0 3 27000000>,
			<&lane2 PHY_TYPE_DP 1 3 27000000>;
};
&xlnx_dp_sub {
	status = "okay";
	xlnx,gfx-fmt = "argb8888";
};
&xlnx_dpdma {
	status = "okay";
};
&xilinx_drm {
	status = "okay";
	clocks = <&vc5 4>;
	planes {
		xlnx,pixel-format = "argb8888";
	};
};

&i2c1 {
	clock-frequency = <100000>;
	status = "okay";

	i2cswitch@70 {
		compatible = "nxp,pca9542";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			eeprom@52 {
				compatible = "at,24c08";
				reg = <0x52>;
			};
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			vc5: clock-generator@6a {
				compatible = "idt,5p49v5935";
				reg = <0x6a>;
				#clock-cells = <1>;
			};

		};
	};
};