****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source digilent_nexys4ddr.tcl
# create_project -force -name digilent_nexys4ddr -part xc7a100t-CSG324-1
# set_msg_config -id {Common 17-55} -new_severity {Warning}
# read_verilog {/home/somlo/LITEX/pythondata-cpu-rocket/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.v}
# read_verilog {/home/somlo/LITEX/pythondata-cpu-rocket/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.behav_srams.v}
# read_verilog {/home/somlo/LITEX/pythondata-cpu-rocket/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v}
# read_verilog {/home/somlo/LITEX/pythondata-cpu-rocket/pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v}
# read_verilog {/home/somlo/LITEX/pythondata-cpu-rocket/pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v}
# read_verilog {/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v}
# read_xdc digilent_nexys4ddr.xdc
# set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4ddr.xdc]
# synth_design -directive default -top digilent_nexys4ddr -part xc7a100t-CSG324-1
Command: synth_design -directive default -top digilent_nexys4ddr -part xc7a100t-CSG324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 1677886
WARNING: [Synth 8-2292] literal value truncated to fit in 5 bits [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:576]
ERROR: [Synth 8-2715] syntax error near basesoc_rocketrv64_mmio_a2w_axi2axi_lite_source_payload_addr [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:4693]
ERROR: [Synth 8-2715] syntax error near ) [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:4693]
ERROR: [Synth 8-2715] syntax error near basesoc_write_aw_buffer_source_payload_addr [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:8525]
ERROR: [Synth 8-2715] syntax error near ) [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:8525]
ERROR: [Synth 8-2715] syntax error near basesoc_read_ar_buffer_source_payload_addr [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:8703]
ERROR: [Synth 8-2715] syntax error near ) [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:8703]
ERROR: [Synth 8-2715] syntax error near basesoc_rocketrv64_mmio_a2w_axi2axi_lite_beat_size [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:14429]
ERROR: [Synth 8-2715] syntax error near basesoc_rocketrv64_mmio_a2w_axi2axi_lite_beat_wrap [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:14434]
ERROR: [Synth 8-2715] syntax error near basesoc_write_beat_size [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:15835]
ERROR: [Synth 8-2715] syntax error near basesoc_write_beat_wrap [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:15840]
ERROR: [Synth 8-2715] syntax error near basesoc_read_beat_size [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:15926]
ERROR: [Synth 8-2715] syntax error near basesoc_read_beat_wrap [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:15931]
WARNING: [Synth 8-2292] literal value truncated to fit in 5 bits [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:17289]
INFO: [Synth 8-2350] module digilent_nexys4ddr ignored due to previous errors [/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v:4]
Failed to read verilog '/home/somlo/LITEX/build/digilent_nexys4ddr/gateware/digilent_nexys4ddr.v'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 13 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Fri Oct 15 10:32:59 2021...
Traceback (most recent call last):
  File "/home/somlo/LITEX/litex-boards/litex_boards/targets/digilent_nexys4ddr.py", line 147, in <module>
    main()
  File "/home/somlo/LITEX/litex-boards/litex_boards/targets/digilent_nexys4ddr.py", line 140, in main
    builder.build(run=args.build)
  File "/home/somlo/LITEX/litex/litex/soc/integration/builder.py", line 315, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/somlo/LITEX/litex/litex/soc/integration/soc.py", line 1138, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/somlo/LITEX/litex/litex/build/xilinx/platform.py", line 55, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/somlo/LITEX/litex/litex/build/xilinx/vivado.py", line 372, in build
    _run_script(script)
  File "/home/somlo/LITEX/litex/litex/build/xilinx/vivado.py", line 101, in _run_script
    raise OSError("Error occured during Vivado's script execution.")
OSError: Error occured during Vivado's script execution.