// Stump ALU
// Implement your Stump ALU here
//
// Created by Paul W Nutter, Feb 2015
//
// This an Stump ALU verilog implementation by Mircea Peia
// I've implemented every instruction in a case in a single always block
//

`include "src/Stump/Stump_definitions.v"

// 'include' definitions of function codes etc.
// e.g. can use "`ADD" instead of "'h0" to aid readability
// Substitute your own definitions if you prefer by
// modifying Stump_definitions.v

/*----------------------------------------------------------------------------*/

module Stump_ALU (input  wire [15:0] operand_A,		// First operand
                  input  wire [15:0] operand_B,		// Second operand
		  input  wire [ 2:0] func,		// Function specifier
		  input  wire        c_in,		// Carry input
		  input  wire        csh,  		// Carry from shifter
		  output reg  [15:0] result,		// ALU output
		  output reg  [ 3:0] flags_out);	// Flags {N, Z, V, C}

// func is the function code
// operand_A is the first operand(the one we shift)
// operand_B is the seocnd operand
//c_in is the carry in may be 1 or 0
//csh carry from shifter
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
/* Declarations of any internal signals and buses used                        */
  reg [16:0] intmResult;
  reg [15:0] invOpB;
  assign invC_in = ~ c_in;
  reg [ 3:0] intmFlags;




/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/

/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
/* Verilog code */

always @ (*)
begin

  //inverting operand B for SUB/SBC
  invOpB[0] = ~ operand_B[0];
  invOpB[1] = ~ operand_B[1];
  invOpB[2] = ~ operand_B[2];
  invOpB[3] = ~ operand_B[3];
  invOpB[4] = ~ operand_B[4];
  invOpB[5] = ~ operand_B[5];
  invOpB[6] = ~ operand_B[6];
  invOpB[7] = ~ operand_B[7];
  invOpB[8] = ~ operand_B[8];
  invOpB[9] = ~ operand_B[9];
  invOpB[10] = ~ operand_B[10];
  invOpB[11] = ~ operand_B[11];
  invOpB[12] = ~ operand_B[12];
  invOpB[13] = ~ operand_B[13];
  invOpB[14] = ~ operand_B[14];
  invOpB[15] = ~ operand_B[15];

  //determining what instruction to do thorugh case
  case (func)

    3'b000: //Addition
      begin
        //calculte the sum
        intmResult = operand_A + operand_B;
        //set the corresponding flags
        intmFlags[3] = intmResult[15];
        intmFlags[2] = (intmResult[15:0] == 0);
        intmFlags[1] = (operand_A[15] == operand_B[15] && operand_A[15] != intmResult[15]);
        intmFlags[0] = intmResult[16];
      end

    3'b001: //Addition w. carry_in
      begin
        //calculte the sum
        intmResult = operand_A + operand_B;
        intmResult = intmResult + c_in;
        //set the corresponding flags
        intmFlags[3] = intmResult[15];
        intmFlags[2] =(intmResult[15:0] == 0);
        intmFlags[1] = (operand_A[15] == operand_B[15] && operand_A[15] != intmResult[15]);
        intmFlags[0] = intmResult[16];
      end

    3'b010: //Subtraction
      begin
        //perform the calculation
        intmResult = operand_A + invOpB;
        intmResult = intmResult + 17'b1;
        //set the corresponding flags
        intmFlags[3] = intmResult[15];
        intmFlags[2] =(intmResult[15:0] == 0);
        intmFlags[1] = (operand_A[15] != operand_B[15] && operand_A[15] != intmResult[15]);
        intmFlags[0] = ~intmResult[16];
      end

    3'b011: //Subtraction w. carry_in
      begin
        //perform the calculation
        intmResult = operand_A + invOpB;
        intmResult = intmResult + invC_in;
        //set the corresponding flags
        intmFlags[3] = intmResult[15];
        intmFlags[2] = (intmResult[15:0] == 0);
        intmFlags[1] = (operand_A[15] != operand_B[15] && operand_A[15] != intmResult[15]);
        intmFlags[0] = ~intmResult[16];
      end

    3'b100: //BitWise AND
      begin
        //perform the logical function
        intmResult[15:0] = operand_A & operand_B;
        //set bit to don't care so no warnings appear
        intmResult[16]= 1'bX;
        //set the corresponding flags
        intmFlags[3] = intmResult[15];
        intmFlags[2] = (intmResult[15:0] == 0);
        intmFlags[1] = 0;
        intmFlags[0] = csh;
      end

    3'b101: //BitWise OR
      begin
        //perform the logical function
        intmResult[15:0] = operand_A | operand_B;
        //set bit to don't care so no warnings appear
        intmResult[16]= 1'bX;
        //set the corresponding flags
        intmFlags[3] = intmResult[15];
        intmFlags[2] =(intmResult[15:0] == 0);
        intmFlags[1] = 0;
        intmFlags[0] = csh;
      end

    3'b110: //LD or ST
      begin
        //perform the logical function
        intmResult = operand_A + operand_B;
        intmFlags[3] = 1'bX;
        intmFlags[2] = 1'bX;
        intmFlags[1] = 1'bX;
        intmFlags[0] = 1'bX;
      end

    3'b111: //Branch
      begin
        //perform the logical function
        intmResult = operand_A + operand_B;
        intmFlags[3] = 1'bX;
        intmFlags[2] = 1'bX;
        intmFlags[1] = 1'bX;
        intmFlags[0] = 1'bX;
      end

    default: // Does nothing
      begin
      intmResult = 17'bX;
      intmFlags[3] = 1'bX;
      intmFlags[2] = 1'bX;
      intmFlags[1] = 1'bX;
      intmFlags[0] = 1'bX;
      end

  endcase
    //set actual result from the internal variable
    result = intmResult[15:0];
    flags_out = intmFlags;

end



/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/

/*----------------------------------------------------------------------------*/



endmodule

/*============================================================================*/