`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/01/2018 06:01:15 PM
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
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// Dependencies:
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// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

//Memory Matrix Width and Memory Matrix Depth - Aka max chars per word and max words per line
`define MMW 16
`define MMD 2048
`define MMWB (`MMW*8)
//`define MMDB (`MMD*8)


module keygen(
    input clock_keygen,
    output reg [9:0] out_word_addr[5:0],
    (* mark_debug = "true" *) /*(* dont_touch = "true" *)*/ output reg [511:0] curr_pass,
    input reg ram_we[5:0],
    input wire [9:0] in_word_addr_w[5:0],
    input wire [511:0] in_word_w[5:0],
    input reset,
    output reg done
    );

    reg [9:0] out_word_addr_r1[5:0];
    reg [9:0] out_word_addr_r2[5:0];
    reg [9:0] out_word_addr_r3[5:0];

    wire [9:0] in_word_addr_reg[5:0];
    reg [9:0] in_word_addr[5:0];

    reg [9:0] in_word_cnt[5:0];
    wire [`MMWB-1:0] in_word[5:0];
    (* mark_debug = "true" *) reg [511:0] in_shift[5:0];
    reg [7:0] cnt_to[6:0];

    initial done = 1'b0;


    reg [255:0]pt =  256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;

    wire [`MMWB-1:0]ram_d[5:0];
    genvar k;

    generate
        for(k = 0; k < 6; k = k + 1) begin: BLKMEM


          blk_mem_gen_0 block_mem_gen_0_local
          (
              .clka(clock_keygen),
              .wea(ram_we[k]),
              .addra(in_word_addr_reg[k]),
              .dina(in_word_w[k]),
              .douta(in_word[k])
            );


        end
    endgenerate



    initial in_shift[0] = 0;
    initial in_shift[1] = 0;
    initial in_shift[2] = 0;
    initial in_shift[3] = 0;
    initial in_shift[4] = 0;
    initial in_shift[5] = 0;


    assign in_word_addr_reg = reset ? in_word_addr_w : in_word_addr;

    reg [511:0] jt;

    always @ (posedge clock_keygen)
    begin

        if(reset)
            begin
                /*in_word_cnt[0] = 9'd1;
                in_word_cnt[1] = 9'd5;
                in_word_cnt[2] = 9'd4;
                in_word_cnt[3] = 9'd4;
                in_word_cnt[4] = 9'd4;
                in_word_cnt[5] = 9'd4;
                */

                in_word_cnt[0] = 9'd27;
                in_word_cnt[1] = 9'd27;
                in_word_cnt[2] = 9'd27;
                in_word_cnt[3] = 9'd27;
                in_word_cnt[4] = 9'd27;
                in_word_cnt[5] = 9'd27;

                in_word_addr[0] <= 9'd0;
                in_word_addr[1] <= 9'd0;
                in_word_addr[2] <= 9'd0;
                in_word_addr[3] <= 9'd0;
                in_word_addr[4] <= 9'd0;
                in_word_addr[5] <= 9'd0;

                 curr_pass <= 511'b0;
                /*

                */
                done = 1'b0;
            end
        else
            begin
            if (in_word_cnt[5] == in_word_addr[5] && in_word_cnt[4] == in_word_addr[4] && in_word_cnt[3] == in_word_addr[3] && in_word_cnt[2] == in_word_addr[2] && in_word_cnt[1] == in_word_addr[1] && in_word_cnt[0] == in_word_addr[0])
                begin
                    //done

                    /*
                    in_word_addr[0] <= 0;
                    in_word_addr[1] <= 0;
                    in_word_addr[2] <= 0;
                    in_word_addr[3] <= 0;
                    in_word_addr[4] <= 0;
                    in_word_addr[5] <= 0;
                    */

                    done = 1'b1;
                end
            else if(in_word_cnt[5] == in_word_addr[5] && in_word_cnt[4] == in_word_addr[4] && in_word_cnt[3] == in_word_addr[3] && in_word_cnt[2] == in_word_addr[2] && in_word_cnt[1] == in_word_addr[1])
                begin
                    in_word_addr[0] <= in_word_addr[0] + 1;
                    in_word_addr[1] <= 0;
                    in_word_addr[2] <= 0;
                    in_word_addr[3] <= 0;
                    in_word_addr[4] <= 0;
                    in_word_addr[5] <= 0;
                end
            else if(in_word_cnt[5] == in_word_addr[5] && in_word_cnt[4] == in_word_addr[4] && in_word_cnt[3] == in_word_addr[3] && in_word_cnt[2] == in_word_addr[2])
                begin
                    in_word_addr[1] <= in_word_addr[1] + 1;
                    in_word_addr[2] <= 0;
                    in_word_addr[3] <= 0;
                    in_word_addr[4] <= 0;
                    in_word_addr[5] <= 0;
                end
            else if(in_word_cnt[5] == in_word_addr[5] && in_word_cnt[4] == in_word_addr[4] && in_word_cnt[3] == in_word_addr[3])
                begin
                    in_word_addr[2] <= in_word_addr[2] + 1;
                    in_word_addr[3] <= 0;
                    in_word_addr[4] <= 0;
                    in_word_addr[5] <= 0;
                end
            else if(in_word_cnt[5] == in_word_addr[5] && in_word_cnt[4] == in_word_addr[4])
                begin
                    in_word_addr[3] <= in_word_addr[3] + 1;
                    in_word_addr[4] <= 0;
                    in_word_addr[5] <= 0;
                end
            else if(in_word_cnt[5] == in_word_addr[5])
                begin
                    in_word_addr[4] <= in_word_addr[4] + 1;
                    in_word_addr[5] <= 0;
                end
            else
                begin
                    in_word_addr[5] <= in_word_addr[5] + 1;
                end
            end



        cnt_to[0] = 8'd0;
        cnt_to[1] = in_word[0][7:0];
        cnt_to[2] = in_word[0][7:0] + in_word[1][7:0];
        cnt_to[3] = in_word[0][7:0] + in_word[1][7:0] + in_word[2][7:0];
        cnt_to[4] = in_word[0][7:0] + in_word[1][7:0] + in_word[2][7:0] + in_word[3][7:0];
        cnt_to[5] = in_word[0][7:0] + in_word[1][7:0] + in_word[2][7:0] + in_word[3][7:0] + in_word[4][7:0];
        cnt_to[6] = in_word[0][7:0] + in_word[1][7:0] + in_word[2][7:0] + in_word[3][7:0] + in_word[4][7:0] + in_word[5][7:0];


        in_shift[0] = in_word[0][`MMWB-8:8];
        in_shift[1][(cnt_to[1] * 8) +: `MMWB-8] = in_word[1][`MMWB-1:8];
        in_shift[2][(cnt_to[2] * 8) +: `MMWB-8] = in_word[2][`MMWB-1:8];
        in_shift[3][(cnt_to[3] * 8) +: `MMWB-8] = in_word[3][`MMWB-1:8];
        in_shift[4][(cnt_to[4] * 8) +: `MMWB-8] = in_word[4][`MMWB-1:8];
        in_shift[5][(cnt_to[5] * 8) +: `MMWB-8] = in_word[5][`MMWB-1:8];

        out_word_addr_r2 <= in_word_addr;
        out_word_addr_r1 <= out_word_addr_r2;
        out_word_addr <= out_word_addr_r1;

        curr_pass = (in_shift[0] | in_shift[1] | in_shift[2] | in_shift[3] | in_shift[4] | in_shift[5]) ;

    end
endmodule