xynta

`timescale 1ns / 1ps

interface xynta_if #(
    COUNTER_WIDTH=8
) (
    input logic clk,
    input logic resetn
);
    logic ready;
    logic valid;
    logic [COUNTER_WIDTH-1:0] data;
endinterface

class xynta_driver #(
    parameter COUNTER_WIDTH=8
);
    integer xynta_counter;
    rand bit xynta_valid;
    virtual xynta_if drv_to_dut;

    function new (virtual xynta_if drv_to_dut);
        this.drv_to_dut = drv_to_dut;
    endfunction

    task drive_valid;
        forever begin
            this.randomize();
            this.drv_to_dut.valid <= this.xynta_valid;
            @(posedge this.drv_to_dut.clk);
        end
    endtask

    task drive_data;
        this.xynta_counter = 0;
        forever begin
            this.drv_to_dut.data <= this.xynta_counter;
            this.xynta_counter++;

            // DOESN'T WORK
            @(posedge this.drv_to_dut.clk iff
                (   this.drv_to_dut.ready &&
                    this.drv_to_dut.valid )     );

//            // hack
//            @(negedge this.drv_to_dut.clk iff
//                (   this.drv_to_dut.ready &&
//                    this.drv_to_dut.valid )     );
//            @(posedge this.drv_to_dut.clk );
        end
    endtask

    task main;
        fork
            drive_valid();
            drive_data();
        join_any
    endtask

endclass

class xynta_test_environment #(
    parameter COUNTER_WIDTH=8
);
    virtual xynta_if drv_to_dut;
    xynta_driver #(COUNTER_WIDTH) driver;

    function new (virtual xynta_if drv_to_dut);
        this.drv_to_dut = drv_to_dut;
        this.driver = new(drv_to_dut);
    endfunction

    task run;
        this.driver.main();
    endtask
endclass

program xynta_test(xynta_if drv_to_dut);
    xynta_test_environment env;

    initial begin
        env = new(drv_to_dut);
        env.run();
    end
endprogram

module xynta #(
    COUNTER_WIDTH=8
) (
    input wire clk,
    input wire resetn,
    // slave if
    input wire [COUNTER_WIDTH-1:0] s_data,
    input wire s_valid,
    output wire s_ready,
    // master if
    output wire [COUNTER_WIDTH-1:0] m_data,
    output wire m_valid,
    input wire m_ready
);
    assign m_data = s_data;
    assign m_valid = s_valid;
    assign s_ready = m_ready;
endmodule

module xynta_tb(
);
    localparam COUNTER_WIDTH = 8;
    reg clk;
    reg resetn;
    reg ready;
    wire [COUNTER_WIDTH-1:0] data;
    wire valid;

    xynta_if drv_to_dut(clk, resetn);
    xynta_test test_inst(drv_to_dut);

    xynta #(COUNTER_WIDTH) xynta_dut (
        .clk(clk),
        .resetn(resetn),
        .s_data(drv_to_dut.data),
        .s_valid(drv_to_dut.valid),
        .s_ready(drv_to_dut.ready),
        .m_data(data),
        .m_valid(valid),
        .m_ready(ready)
    );

    initial begin
        clk = 1;
        forever #5 clk = !clk;
    end

    initial begin
            resetn = 1;
            ready = 0;
        #10 resetn <= 0;
        #10 resetn <= 1;
        #10;
        forever begin
            ready <= $random % 3 != 0;
            // hack
            //ready <= #1 $random % 3 != 0;
            @(posedge clk);
        end
    end
endmodule