module FSM (input clk, reset, NB, SB, output reg fsm_TR, fsm_TY, fsm_TG, fsm_PR, fsm_PG);
  reg[1:0] currentState, nextState;
  reg[2:0] count;
  reg[3:0] count_1;
  reg previous_State;
  reg neg_P_req;
  wire P_req;
  parameter StateA = 3'b000, StateB = 3'b001, StateC = 3'b010, StateD = 3'b011, StateE = 3'b100, StateF = 3'b101;
  assign P_req = NB || SB;
  always @ (posedge clk) begin
    if (reset == 1'b1)begin
      currentState <= StateA;
    previous_State <= StateA;
    end
    else
      currentState <= nextState;
  end
  always @ (*) begin
    case(currentState)
      StateA: begin
        if (P_req == 1'b1)
         	nextState <= StateB;
        else if (count_1[3] == 1 && count_1[2] == 1 && count_1[1] == 0 && count_1[0] == 0 && neg_P_req == 1'b1)
          	nextState <= StateA;
        else
          nextState <= StateA;
      end
      StateB:
        if (count[2:0] <= 3'b010)
          nextState <= StateC;
      	else begin
          nextState <= StateB;
          count[2:0] <= 3'b000;
        end
      StateC:
        if (count[2:0] <= 3'b010)
          nextState <= StateD;
      	else begin
          nextState <= StateC;
          count[2:0] <= 3'b000;
        end
      StateD:
        if (count[2:0] <= 3'b110)
          nextState <= StateD;
        else begin
          nextState <= StateE;
          count[2:0] <= 3'b000;
        end
      StateE:
        if (count[2:0] <= 3'b110)
          nextState <= StateE;
        else begin
          nextState <= StateF;
          count[2:0] <= 3'b000;
        end
      StateF:
        if (count[2:0] <= 3'b010)
          nextState <= StateF;
      else begin
        nextState <= StateA;
        count[2:0] <= 3'b000;
        previous_State <= StateF;
      end
    endcase
  end
  always @ (*) begin
    case(currentState)
      StateA: begin
        fsm_TR = 1'b0;
        fsm_TY = 1'b0;
        fsm_TG = 1'b1;
        fsm_PR = 1'b1;
        fsm_PG = 1'b0;
      end
      StateB: begin
        fsm_TR = 1'b0;
        fsm_TY = 1'b1;
        fsm_TG = 1'b0;
        fsm_PR = 1'b1;
        fsm_PG = 1'b0;
      end
      StateC: begin
        fsm_TR = 1'b1;
        fsm_TY = 1'b0;
        fsm_TG = 1'b0;
        fsm_PR = 1'b1;
        fsm_PG = 1'b0;
      end
      StateD: begin
        if (count[2:0] <= 3'b110)begin
          fsm_TR = 1'b1;
          fsm_TY = 1'b0;
          fsm_TG = 1'b0;
          fsm_PR = 1'b0;
          fsm_PG = 1'b1;
        end
        else begin
          fsm_TR = 1'b1;
          fsm_TY = 1'b0;
          fsm_TG = 1'b0;
          fsm_PR = 1'b0;
          fsm_PG = 1'b0;
        end
      end
      StateE: begin
        fsm_TR = 1'b1;
        fsm_TY = 1'b0;
        fsm_TG = 1'b0;
        fsm_PR = 1'b0;
        if (count[2:0] <= 3'b110) begin
          if (count[0] == 0)
            fsm_PG = 1'b1;
          else
            fsm_PG = 1'b0;
        end
      end
      StateF: begin
        	fsm_TR = 1'b1;
        	fsm_TY = 1'b0;
        	fsm_TG = 1'b0;
        	fsm_PR = 1'b1;
        	fsm_PG = 1'b0;
        end
    endcase
  end
endmodule
module counter (input clk, reset, output reg [2:0] count);
  always @ (posedge clk) begin
    if (reset == 1'b1)
      count <= 3'b000;
    else
      count <= count + 3'b001;
  end
endmodule
module controller (input clk, reset, NB, SB, output reg TR, TY, TG, PR, PG);
  wire [2:0]counter_count;
  reg neg_P_req;
  reg [3:0]count_1;
  wire fsm_P_req;
  reg previous_State;
  wire fsm_TR, fsm_TY, fsm_TG, fsm_PR, fsm_PG;
  counter M1 (.clk(clk), .reset(reset), .count(counter_count));
  FSM M2 (.clk(clk), .reset(reset), .NB(NB), .SB(SB), .fsm_TR(fsm_TR), .fsm_TY(fsm_TY), .fsm_TG(fsm_TG), .fsm_PR(fsm_PR), .fsm_PG(fsm_PG));
  always @ (posedge clk)begin
    if (reset == 1'b1) begin
      count_1 <= 4'b0000;
      neg_P_req <= 1'b0;
    end
    else begin
      if (M2.currentState == M2.StateA && count_1[3] == 1 && count_1[2] == 1 && count_1[1] == 0 && count_1[0] == 0 && M2.P_req == 1'b1 && M2.previous_State == M2.StateF)
        neg_P_req <= ~M2.P_req;
      if (M2.currentState == M2.StateA && M2.previous_State == M2.StateF)
        count_1 <= count_1 + 4'b0001;
    end
  end
  assign fsm_P_req = M2.P_req;
  always @(posedge clk) begin
    TR <= fsm_TR;
    TY <= fsm_TY;
    TG <= fsm_TG;
    PR <= fsm_PR;
    PG <= fsm_PG;
  end
endmodule