API tools faq
paste
Advertisement
Guest User

fdt_Colibri_missing_boot_module

a guest
Sep 9th, 2020
206
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 129.86 KB | None | 0 0
raw download clone embed print report
  1. Colibri iMX8X # fdt print
  2. / {
  3. model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3";
  4. compatible = "toradex,colibri-imx8qxp-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp";
  5. interrupt-parent = <0x00000001>;
  6. #address-cells = <0x00000002>;
  7. #size-cells = <0x00000002>;
  8. cpus {
  9. #address-cells = <0x00000002>;
  10. #size-cells = <0x00000000>;
  11. cpu@0 {
  12. device_type = "cpu";
  13. compatible = "arm,cortex-a35";
  14. reg = <0x00000000 0x00000000>;
  15. enable-method = "psci";
  16. next-level-cache = <0x00000002>;
  17. operating-points = <0x00124f80 0x00000000 0x000dbba0 0x00000000>;
  18. clocks = <0x00000003 0x00000149>;
  19. clock-latency = <0x0000ee6c>;
  20. #cooling-cells = <0x00000002>;
  21. linux,phandle = <0x00000004>;
  22. phandle = <0x00000004>;
  23. };
  24. cpu@1 {
  25. device_type = "cpu";
  26. compatible = "arm,cortex-a35";
  27. reg = <0x00000000 0x00000001>;
  28. enable-method = "psci";
  29. next-level-cache = <0x00000002>;
  30. linux,phandle = <0x00000005>;
  31. phandle = <0x00000005>;
  32. };
  33. cpu@2 {
  34. device_type = "cpu";
  35. compatible = "arm,cortex-a35";
  36. reg = <0x00000000 0x00000002>;
  37. enable-method = "psci";
  38. next-level-cache = <0x00000002>;
  39. linux,phandle = <0x00000006>;
  40. phandle = <0x00000006>;
  41. };
  42. cpu@3 {
  43. device_type = "cpu";
  44. compatible = "arm,cortex-a35";
  45. reg = <0x00000000 0x00000003>;
  46. enable-method = "psci";
  47. next-level-cache = <0x00000002>;
  48. linux,phandle = <0x00000007>;
  49. phandle = <0x00000007>;
  50. };
  51. l2-cache0 {
  52. compatible = "cache";
  53. linux,phandle = <0x00000002>;
  54. phandle = <0x00000002>;
  55. };
  56. idle-states {
  57. entry-method = "psci";
  58. cpu-sleep {
  59. compatible = "arm,idle-state";
  60. arm,psci-suspend-param = <0x00010000>;
  61. local-timer-stop;
  62. entry-latency-us = <0x000001f4>;
  63. exit-latency-us = <0x000001f4>;
  64. min-residency-us = <0x00001388>;
  65. };
  66. cluster-sleep {
  67. compatible = "arm,idle-state";
  68. arm,psci-suspend-param = <0x00010033>;
  69. local-timer-stop;
  70. entry-latency-us = <0x000001f4>;
  71. exit-latency-us = <0x000008fc>;
  72. min-residency-us = <0x000036b0>;
  73. };
  74. };
  75. };
  76. pmu {
  77. compatible = "arm,armv8-pmuv3";
  78. interrupts = <0x00000001 0x00000007 0x00003f04>;
  79. interrupt-affinity = <0x00000004 0x00000005 0x00000006 0x00000007>;
  80. };
  81. psci {
  82. compatible = "arm,psci-1.0";
  83. method = "smc";
  84. cpu_suspend = <0xc4000001>;
  85. cpu_off = <0xc4000002>;
  86. cpu_on = <0xc4000003>;
  87. };
  88. aliases {
  89. csi0 = "/camera/csi@58227000";
  90. dpu0 = "/dpu@56180000";
  91. ethernet0 = "/ethernet@5b040000";
  92. ethernet1 = "/ethernet@5b050000";
  93. dsi_phy0 = "/dsi_phy@56228300";
  94. dsi_phy1 = "/dsi_phy@56248300";
  95. mipi_dsi0 = "/mipi_dsi@56228000";
  96. mipi_dsi1 = "/mipi_dsi@56248000";
  97. ldb0 = "/ldb@562210e0";
  98. ldb1 = "/ldb@562410e0";
  99. isi0 = "/camera/isi@58100000";
  100. isi1 = "/camera/isi@58110000";
  101. isi2 = "/camera/isi@58120000";
  102. isi3 = "/camera/isi@58130000";
  103. isi4 = "/camera/isi@58140000";
  104. isi5 = "/camera/isi@58150000";
  105. isi6 = "/camera/isi@58160000";
  106. isi7 = "/camera/isi@58170000";
  107. serial0 = "/serial@5a060000";
  108. serial1 = "/serial@5a070000";
  109. serial2 = "/serial@5a080000";
  110. serial3 = "/serial@5a090000";
  111. mmc0 = "/usdhc@5b010000";
  112. mmc1 = "/usdhc@5b020000";
  113. mmc2 = "/usdhc@5b030000";
  114. can0 = "/can@5a8d0000";
  115. can1 = "/can@5a8e0000";
  116. can2 = "/can@5a8f0000";
  117. i2c1 = "/i2c-rpbus-1";
  118. i2c5 = "/i2c-rpbus-5";
  119. i2c12 = "/i2c-rpbus-12";
  120. i2c13 = "/i2c-rpbus-13";
  121. i2c14 = "/i2c-rpbus-14";
  122. i2c15 = "/i2c-rpbus-15";
  123. rtc0 = "/i2c@5a810000/rtc@68";
  124. rtc1 = "/rtc";
  125. };
  126. memory@80000000 {
  127. #address-cells = <0x00000002>;
  128. #size-cells = <0x00000002>;
  129. device_type = "memory";
  130. reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
  131. };
  132. reserved-memory {
  133. #address-cells = <0x00000002>;
  134. #size-cells = <0x00000002>;
  135. ranges;
  136. decoder_boot@0x84000000 {
  137. no-map;
  138. reg = <0x00000000 0x84000000 0x00000000 0x02000000>;
  139. linux,phandle = <0x0000011e>;
  140. phandle = <0x0000011e>;
  141. };
  142. encoder_boot@0x86000000 {
  143. no-map;
  144. reg = <0x00000000 0x86000000 0x00000000 0x00200000>;
  145. linux,phandle = <0x00000120>;
  146. phandle = <0x00000120>;
  147. };
  148. rpmsg@0x90000000 {
  149. no-map;
  150. reg = <0x00000000 0x90000000 0x00000000 0x00400000>;
  151. linux,phandle = <0x00000117>;
  152. phandle = <0x00000117>;
  153. };
  154. rpmsg_dma@0x90400000 {
  155. compatible = "shared-dma-pool";
  156. no-map;
  157. reg = <0x00000000 0x90400000 0x00000000 0x01c00000>;
  158. linux,phandle = <0x00000125>;
  159. phandle = <0x00000125>;
  160. };
  161. decoder_rpc@0x92000000 {
  162. no-map;
  163. reg = <0x00000000 0x92000000 0x00000000 0x00200000>;
  164. linux,phandle = <0x0000011f>;
  165. phandle = <0x0000011f>;
  166. };
  167. encoder_rpc@0x92200000 {
  168. no-map;
  169. reg = <0x00000000 0x92200000 0x00000000 0x00200000>;
  170. linux,phandle = <0x00000121>;
  171. phandle = <0x00000121>;
  172. };
  173. dsp@0x92400000 {
  174. no-map;
  175. reg = <0x00000000 0x92400000 0x00000000 0x02000000>;
  176. linux,phandle = <0x00000110>;
  177. phandle = <0x00000110>;
  178. };
  179. encoder_reserved@0x94400000 {
  180. no-map;
  181. reg = <0x00000000 0x94400000 0x00000000 0x00800000>;
  182. linux,phandle = <0x00000122>;
  183. phandle = <0x00000122>;
  184. };
  185. linux,cma {
  186. compatible = "shared-dma-pool";
  187. reusable;
  188. size = <0x00000000 0x3c000000>;
  189. alloc-ranges = <0x00000000 0x96000000 0x00000000 0x3c000000>;
  190. linux,cma-default;
  191. };
  192. };
  193. interrupt-controller@51a00000 {
  194. compatible = "arm,gic-v3";
  195. reg = <0x00000000 0x51a00000 0x00000000 0x00010000 0x00000000 0x51b00000 0x00000000 0x000c0000>;
  196. #interrupt-cells = <0x00000003>;
  197. interrupt-controller;
  198. interrupts = <0x00000001 0x00000009 0x00003f04>;
  199. interrupt-parent = <0x00000001>;
  200. linux,phandle = <0x00000001>;
  201. phandle = <0x00000001>;
  202. };
  203. mu@5d1c0000 {
  204. compatible = "fsl,imx8-mu";
  205. reg = <0x00000000 0x5d1c0000 0x00000000 0x00010000>;
  206. interrupts = <0x00000000 0x000000b1 0x00000004>;
  207. interrupt-parent = <0x00000001>;
  208. fsl,scu_ap_mu_id = <0x00000000>;
  209. status = "okay";
  210. };
  211. mu@31560000 {
  212. compatible = "fsl,imx8-seco-mu";
  213. reg = <0x00000000 0x31560000 0x00000000 0x00010000>;
  214. power-domains = <0x00000008>;
  215. interrupts = <0x00000000 0x000001c0 0x00000004>;
  216. fsl,seco_mu_id = <0x00000001>;
  217. fsl,seco_max_users = <0x00000004>;
  218. status = "okay";
  219. };
  220. mu@31570000 {
  221. compatible = "fsl,imx8-seco-mu";
  222. reg = <0x00000000 0x31570000 0x00000000 0x00010000>;
  223. power-domains = <0x00000009>;
  224. interrupts = <0x00000000 0x000001c1 0x00000004>;
  225. fsl,seco_mu_id = <0x00000002>;
  226. fsl,seco_max_users = <0x00000002>;
  227. status = "okay";
  228. };
  229. mu@31580000 {
  230. compatible = "fsl,imx8-seco-mu";
  231. reg = <0x00000000 0x31580000 0x00000000 0x00010000>;
  232. power-domains = <0x0000000a>;
  233. interrupts = <0x00000000 0x000001c2 0x00000004>;
  234. fsl,seco_mu_id = <0x00000003>;
  235. fsl,seco_max_users = <0x00000002>;
  236. status = "okay";
  237. };
  238. mu13@5d280000 {
  239. compatible = "fsl,imx8-mu-dsp";
  240. reg = <0x00000000 0x5d280000 0x00000000 0x00010000>;
  241. interrupts = <0x00000000 0x000000c0 0x00000004>;
  242. fsl,dsp_ap_mu_id = <0x0000000d>;
  243. status = "okay";
  244. };
  245. mu_m4@37440000 {
  246. compatible = "fsl,imx8-mu0-vpu-m4";
  247. reg = <0x00000000 0x37440000 0x00000000 0x00010000>;
  248. interrupts = <0x00000000 0x00000010 0x00000004>;
  249. fsl,vpu_ap_mu_id = <0x0000000f>;
  250. status = "okay";
  251. };
  252. mu_m0@2d000000 {
  253. compatible = "fsl,imx8-mu0-vpu-m0";
  254. reg = <0x00000000 0x2d000000 0x00000000 0x00020000>;
  255. interrupts = <0x00000000 0x000001d5 0x00000004>;
  256. fsl,vpu_ap_mu_id = <0x00000010>;
  257. status = "okay";
  258. };
  259. mu1_m0@2d020000 {
  260. compatible = "fsl,imx8-mu1-vpu-m0";
  261. reg = <0x00000000 0x2d020000 0x00000000 0x00020000>;
  262. interrupts = <0x00000000 0x000001d6 0x00000004>;
  263. fsl,vpu_ap_mu_id = <0x00000011>;
  264. status = "okay";
  265. };
  266. clk {
  267. compatible = "fsl,imx8qxp-clk";
  268. #clock-cells = <0x00000001>;
  269. linux,phandle = <0x00000003>;
  270. phandle = <0x00000003>;
  271. };
  272. iomuxc {
  273. compatible = "fsl,imx8qxp-iomuxc";
  274. pinctrl-names = "default";
  275. pinctrl-0 = <0x0000000b 0x0000000c 0x0000000d 0x0000000e 0x0000000f>;
  276. colibri-imx8qxp {
  277. ad7879-int {
  278. fsl,pins = <0x00000098 0x00000004 0x00000021>;
  279. linux,phandle = <0x0000008e>;
  280. phandle = <0x0000008e>;
  281. };
  282. adc0grp {
  283. fsl,pins = <0x00000064 0x00000000 0x00000060 0x00000063 0x00000000 0x00000060 0x00000068 0x00000000 0x00000060 0x00000067 0x00000000 0x00000060>;
  284. linux,phandle = <0x00000083>;
  285. phandle = <0x00000083>;
  286. };
  287. can-int-grp {
  288. fsl,pins = <0x000000a0 0x00000004 0x00000040>;
  289. linux,phandle = <0x000000bb>;
  290. phandle = <0x000000bb>;
  291. };
  292. csictlgrp {
  293. fsl,pins = <0x000000a1 0x00000004 0x00000020 0x000000a2 0x00000004 0x00000020>;
  294. linux,phandle = <0x0000007f>;
  295. phandle = <0x0000007f>;
  296. };
  297. gpiokeysgrp {
  298. fsl,pins = <0x0000009d 0x00000004 0x06700041>;
  299. linux,phandle = <0x00000133>;
  300. phandle = <0x00000133>;
  301. };
  302. lpuart0grp {
  303. fsl,pins = <0x0000006f 0x00000000 0x06000020 0x00000070 0x00000000 0x06000020 0x00000069 0x00000002 0x06000020 0x0000006a 0x00000002 0x06000020>;
  304. linux,phandle = <0x000000c0>;
  305. phandle = <0x000000c0>;
  306. };
  307. lpuart2grp {
  308. fsl,pins = <0x00000072 0x00000000 0x06000020 0x00000071 0x00000000 0x06000020>;
  309. linux,phandle = <0x000000c3>;
  310. phandle = <0x000000c3>;
  311. };
  312. lpuart3grp {
  313. fsl,pins = <0x0000006d 0x00000002 0x06000020 0x0000006e 0x00000002 0x06000020>;
  314. linux,phandle = <0x000000c5>;
  315. phandle = <0x000000c5>;
  316. };
  317. lpuart3ctrlgrp {
  318. fsl,pins = * 0x000000009300184c [0x00000048];
  319. linux,phandle = <0x000000c6>;
  320. phandle = <0x000000c6>;
  321. };
  322. fec1grp {
  323. fsl,pins = * 0x00000000930018d0 [0x00000090];
  324. linux,phandle = <0x0000010a>;
  325. phandle = <0x0000010a>;
  326. };
  327. fec1-sleep-grp {
  328. fsl,pins = * 0x00000000930019a4 [0x00000078];
  329. linux,phandle = <0x0000010b>;
  330. phandle = <0x0000010b>;
  331. };
  332. gpio-bl-on {
  333. fsl,pins = <0x0000009f 0x00000004 0x00000060>;
  334. linux,phandle = <0x00000129>;
  335. phandle = <0x00000129>;
  336. };
  337. hog0grp {
  338. fsl,pins = <0x00000044 0x00000000 0x000514a0>;
  339. linux,phandle = <0x0000000b>;
  340. phandle = <0x0000000b>;
  341. };
  342. hog1grp {
  343. fsl,pins = * 0x0000000093001aec [0x00000120];
  344. linux,phandle = <0x0000000c>;
  345. phandle = <0x0000000c>;
  346. };
  347. hog2grp {
  348. fsl,pins = <0x00000093 0x00000004 0x00000020 0x000000a3 0x00000004 0x00000020>;
  349. linux,phandle = <0x0000000d>;
  350. phandle = <0x0000000d>;
  351. };
  352. hogscfwgrp {
  353. fsl,pins = <0x00000081 0x00000004 0x00000020>;
  354. };
  355. i2c0grp {
  356. fsl,pins = <0x0000009b 0x00000001 0x06000021 0x0000009a 0x00000001 0x06000021>;
  357. linux,phandle = <0x00000086>;
  358. phandle = <0x00000086>;
  359. };
  360. i2c1grp {
  361. fsl,pins = <0x00000076 0x00000001 0x06000021 0x00000077 0x00000001 0x06000021>;
  362. linux,phandle = <0x00000090>;
  363. phandle = <0x00000090>;
  364. };
  365. flexcan0grp {
  366. fsl,pins = <0x0000006a 0x00000000 0x00000021 0x00000069 0x00000000 0x00000021>;
  367. linux,phandle = <0x00000098>;
  368. phandle = <0x00000098>;
  369. };
  370. flexcan1grp {
  371. fsl,pins = <0x0000006c 0x00000000 0x00000021 0x0000006b 0x00000000 0x00000021>;
  372. linux,phandle = <0x0000009a>;
  373. phandle = <0x0000009a>;
  374. };
  375. flexcan2grp {
  376. fsl,pins = <0x0000006e 0x00000000 0x00000021 0x0000006d 0x00000000 0x00000021>;
  377. linux,phandle = <0x0000009c>;
  378. phandle = <0x0000009c>;
  379. };
  380. pciebgrp {
  381. fsl,pins = <0x00000001 0x00000004 0x04000061 0x00000002 0x00000004 0x04000061 0x00000000 0x00000004 0x00000060>;
  382. linux,phandle = <0x0000011a>;
  383. phandle = <0x0000011a>;
  384. };
  385. pwma {
  386. fsl,pins = <0x0000008d 0x00000000 0x00000061 0x00000060 0x00000003 0x00000060>;
  387. linux,phandle = <0x00000058>;
  388. phandle = <0x00000058>;
  389. };
  390. pwmb {
  391. fsl,pins = <0x0000004d 0x00000001 0x00000060>;
  392. linux,phandle = <0x000000aa>;
  393. phandle = <0x000000aa>;
  394. };
  395. pwmc {
  396. fsl,pins = <0x0000004e 0x00000001 0x00000060>;
  397. linux,phandle = <0x000000ac>;
  398. phandle = <0x000000ac>;
  399. };
  400. pwmd {
  401. fsl,pins = <0x0000008c 0x00000000 0x00000061 0x0000004f 0x00000001 0x00000060>;
  402. linux,phandle = <0x000000ae>;
  403. phandle = <0x000000ae>;
  404. };
  405. sai0grp {
  406. fsl,pins = <0x0000005e 0x00000001 0x06000040 0x00000061 0x00000001 0x06000040 0x0000005d 0x00000001 0x06000040 0x0000005f 0x00000001 0x06000040>;
  407. linux,phandle = <0x000000f2>;
  408. phandle = <0x000000f2>;
  409. };
  410. sgtl5000 {
  411. fsl,pins = <0x00000099 0x00000004 0x00000041>;
  412. linux,phandle = <0x0000008b>;
  413. phandle = <0x0000008b>;
  414. };
  415. sgtl5000-usb-clk {
  416. fsl,pins = <0x00000065 0x00000003 0x00000021>;
  417. linux,phandle = <0x00000087>;
  418. phandle = <0x00000087>;
  419. };
  420. usb3503a-grp {
  421. fsl,pins = <0x00000097 0x00000004 0x00000061>;
  422. linux,phandle = <0x00000088>;
  423. phandle = <0x00000088>;
  424. };
  425. usbc-det {
  426. fsl,pins = <0x00000033 0x00000004 0x06000040>;
  427. linux,phandle = <0x00000132>;
  428. phandle = <0x00000132>;
  429. };
  430. ext-io0 {
  431. fsl,pins = <0x00000031 0x00000004 0x06000040>;
  432. linux,phandle = <0x0000000e>;
  433. phandle = <0x0000000e>;
  434. };
  435. lcdif-pins {
  436. fsl,pins = * 0x0000000093002208 [0x0000012c];
  437. linux,phandle = <0x00000055>;
  438. phandle = <0x00000055>;
  439. };
  440. usbh1-reg {
  441. fsl,pins = <0x00000004 0x00000004 0x06000040>;
  442. linux,phandle = <0x0000012d>;
  443. phandle = <0x0000012d>;
  444. };
  445. usdhc1grp {
  446. fsl,pins = * 0x00000000930023c0 [0x00000090];
  447. linux,phandle = <0x000000fe>;
  448. phandle = <0x000000fe>;
  449. };
  450. usdhc1grp100mhz {
  451. fsl,pins = * 0x0000000093002494 [0x00000090];
  452. linux,phandle = <0x000000ff>;
  453. phandle = <0x000000ff>;
  454. };
  455. usdhc1grp200mhz {
  456. fsl,pins = * 0x0000000093002568 [0x00000090];
  457. linux,phandle = <0x00000100>;
  458. phandle = <0x00000100>;
  459. };
  460. usdhc2gpiogrp {
  461. fsl,pins = <0x0000009c 0x00000004 0x06000021>;
  462. linux,phandle = <0x00000103>;
  463. phandle = <0x00000103>;
  464. };
  465. usdhc2gpioslpgrp {
  466. fsl,pins = <0x0000009c 0x00000004 0x00000060>;
  467. linux,phandle = <0x00000107>;
  468. phandle = <0x00000107>;
  469. };
  470. usdhc2grp {
  471. fsl,pins = * 0x00000000930026dc [0x00000054];
  472. linux,phandle = <0x00000102>;
  473. phandle = <0x00000102>;
  474. };
  475. usdhc2grp100mhz {
  476. fsl,pins = * 0x0000000093002774 [0x00000054];
  477. linux,phandle = <0x00000104>;
  478. phandle = <0x00000104>;
  479. };
  480. usdhc2grp200mhz {
  481. fsl,pins = * 0x000000009300280c [0x00000054];
  482. linux,phandle = <0x00000105>;
  483. phandle = <0x00000105>;
  484. };
  485. usdhc2slpgrp {
  486. fsl,pins = * 0x00000000930028a4 [0x00000054];
  487. linux,phandle = <0x00000106>;
  488. phandle = <0x00000106>;
  489. };
  490. mipi_lvds0_i2c0_grp {
  491. fsl,pins = <0x00000074 0x00000000 0xc6000020 0x00000075 0x00000000 0xc6000020>;
  492. linux,phandle = <0x00000068>;
  493. phandle = <0x00000068>;
  494. };
  495. mipi_lvds1_i2c0_grp {
  496. fsl,pins = <0x00000078 0x00000000 0xc6000020 0x00000079 0x00000000 0xc6000020>;
  497. linux,phandle = <0x0000007e>;
  498. phandle = <0x0000007e>;
  499. };
  500. lpspi2 {
  501. fsl,pins = <0x00000059 0x00000004 0x00000021 0x0000005a 0x00000000 0x06000040 0x0000005b 0x00000000 0x06000040 0x0000005c 0x00000000 0x06000040>;
  502. linux,phandle = <0x000000b9>;
  503. phandle = <0x000000b9>;
  504. };
  505. wifigrp {
  506. fsl,pins = <0x00000087 0x00000003 0x00000020>;
  507. linux,phandle = <0x0000011b>;
  508. phandle = <0x0000011b>;
  509. };
  510. mxt-ts {
  511. fsl,pins = <0x000000a8 0x00000004 0x00000020 0x000000ac 0x00000004 0x00000020>;
  512. linux,phandle = <0x0000000f>;
  513. phandle = <0x0000000f>;
  514. };
  515. };
  516. };
  517. rtc {
  518. compatible = "fsl,imx-sc-rtc";
  519. };
  520. secvio {
  521. compatible = "fsl,imx-sc-secvio";
  522. };
  523. timer {
  524. compatible = "arm,armv8-timer";
  525. interrupts = <0x00000001 0x0000000d 0x00003f08 0x00000001 0x0000000e 0x00003f08 0x00000001 0x0000000b 0x00003f08 0x00000001 0x0000000a 0x00003f08>;
  526. clock-frequency = <0x007a1200>;
  527. interrupt-parent = <0x00000001>;
  528. };
  529. imx8qx-pm {
  530. #address-cells = <0x00000001>;
  531. #size-cells = <0x00000000>;
  532. lsio_power_domain {
  533. compatible = "nxp,imx8-pd";
  534. reg = <0x0000fff0>;
  535. #power-domain-cells = <0x00000000>;
  536. #address-cells = <0x00000001>;
  537. #size-cells = <0x00000000>;
  538. linux,phandle = <0x00000010>;
  539. phandle = <0x00000010>;
  540. lsio_pwm0 {
  541. reg = <0x000000bf>;
  542. #power-domain-cells = <0x00000000>;
  543. power-domains = <0x00000010>;
  544. linux,phandle = <0x000000a9>;
  545. phandle = <0x000000a9>;
  546. };
  547. lsio_pwm1 {
  548. reg = <0x000000c0>;
  549. #power-domain-cells = <0x00000000>;
  550. power-domains = <0x00000010>;
  551. linux,phandle = <0x000000ab>;
  552. phandle = <0x000000ab>;
  553. };
  554. lsio_pwm2 {
  555. reg = <0x000000c1>;
  556. #power-domain-cells = <0x00000000>;
  557. power-domains = <0x00000010>;
  558. linux,phandle = <0x000000ad>;
  559. phandle = <0x000000ad>;
  560. };
  561. lsio_pwm3 {
  562. reg = <0x000000c2>;
  563. #power-domain-cells = <0x00000000>;
  564. power-domains = <0x00000010>;
  565. linux,phandle = <0x000000af>;
  566. phandle = <0x000000af>;
  567. };
  568. lsio_pwm4 {
  569. reg = <0x000000c3>;
  570. #power-domain-cells = <0x00000000>;
  571. power-domains = <0x00000010>;
  572. linux,phandle = <0x000000b0>;
  573. phandle = <0x000000b0>;
  574. };
  575. lsio_pwm5 {
  576. reg = <0x000000c4>;
  577. #power-domain-cells = <0x00000000>;
  578. power-domains = <0x00000010>;
  579. linux,phandle = <0x000000b1>;
  580. phandle = <0x000000b1>;
  581. };
  582. lsio_pwm6 {
  583. reg = <0x000000c5>;
  584. #power-domain-cells = <0x00000000>;
  585. power-domains = <0x00000010>;
  586. linux,phandle = <0x000000b2>;
  587. phandle = <0x000000b2>;
  588. };
  589. lsio_pwm7 {
  590. reg = <0x000000c6>;
  591. #power-domain-cells = <0x00000000>;
  592. power-domains = <0x00000010>;
  593. linux,phandle = <0x000000b3>;
  594. phandle = <0x000000b3>;
  595. };
  596. lsio_kpp {
  597. reg = <0x000000d4>;
  598. #power-domain-cells = <0x00000000>;
  599. power-domains = <0x00000010>;
  600. };
  601. lsio_gpio0 {
  602. reg = <0x000000c7>;
  603. #power-domain-cells = <0x00000000>;
  604. power-domains = <0x00000010>;
  605. linux,phandle = <0x000000a1>;
  606. phandle = <0x000000a1>;
  607. };
  608. lsio_gpio1 {
  609. reg = <0x000000c8>;
  610. #power-domain-cells = <0x00000000>;
  611. power-domains = <0x00000010>;
  612. linux,phandle = <0x000000a2>;
  613. phandle = <0x000000a2>;
  614. };
  615. lsio_gpio2 {
  616. reg = <0x000000c9>;
  617. #power-domain-cells = <0x00000000>;
  618. power-domains = <0x00000010>;
  619. linux,phandle = <0x000000a3>;
  620. phandle = <0x000000a3>;
  621. };
  622. lsio_gpio3 {
  623. reg = <0x000000ca>;
  624. #power-domain-cells = <0x00000000>;
  625. power-domains = <0x00000010>;
  626. linux,phandle = <0x000000a4>;
  627. phandle = <0x000000a4>;
  628. };
  629. lsio_gpio4 {
  630. reg = <0x000000cb>;
  631. #power-domain-cells = <0x00000000>;
  632. power-domains = <0x00000010>;
  633. linux,phandle = <0x000000a5>;
  634. phandle = <0x000000a5>;
  635. };
  636. lsio_gpio5 {
  637. reg = <0x000000cc>;
  638. #power-domain-cells = <0x00000000>;
  639. power-domains = <0x00000010>;
  640. linux,phandle = <0x000000a6>;
  641. phandle = <0x000000a6>;
  642. };
  643. lsio_gpio6 {
  644. reg = <0x000000cd>;
  645. #power-domain-cells = <0x00000000>;
  646. power-domains = <0x00000010>;
  647. linux,phandle = <0x000000a7>;
  648. phandle = <0x000000a7>;
  649. };
  650. lsio_gpio7 {
  651. reg = <0x000000ce>;
  652. #power-domain-cells = <0x00000000>;
  653. power-domains = <0x00000010>;
  654. linux,phandle = <0x000000a8>;
  655. phandle = <0x000000a8>;
  656. };
  657. lsio_gpt0 {
  658. reg = <0x000000cf>;
  659. #power-domain-cells = <0x00000000>;
  660. power-domains = <0x00000010>;
  661. linux,phandle = <0x0000010f>;
  662. phandle = <0x0000010f>;
  663. };
  664. lsio_gpt1 {
  665. reg = <0x000000d0>;
  666. #power-domain-cells = <0x00000000>;
  667. power-domains = <0x00000010>;
  668. };
  669. lsio_gpt2 {
  670. reg = <0x000000d1>;
  671. #power-domain-cells = <0x00000000>;
  672. power-domains = <0x00000010>;
  673. };
  674. lsio_gpt3 {
  675. reg = <0x000000d2>;
  676. #power-domain-cells = <0x00000000>;
  677. power-domains = <0x00000010>;
  678. };
  679. lsio_gpt4 {
  680. reg = <0x000000d3>;
  681. #power-domain-cells = <0x00000000>;
  682. power-domains = <0x00000010>;
  683. };
  684. lsio_fspi0 {
  685. reg = <0x000000ed>;
  686. #power-domain-cells = <0x00000000>;
  687. power-domains = <0x00000010>;
  688. linux,phandle = <0x00000114>;
  689. phandle = <0x00000114>;
  690. };
  691. lsio_fspi1 {
  692. reg = <0x000000ee>;
  693. #power-domain-cells = <0x00000000>;
  694. power-domains = <0x00000010>;
  695. };
  696. lsio_mu5a {
  697. reg = <0x000000da>;
  698. #power-domain-cells = <0x00000000>;
  699. power-domains = <0x00000010>;
  700. linux,phandle = <0x00000124>;
  701. phandle = <0x00000124>;
  702. };
  703. };
  704. PD_SECO_MU {
  705. compatible = "nxp,imx8-pd";
  706. reg = <0x0000fff0>;
  707. #power-domain-cells = <0x00000000>;
  708. #address-cells = <0x00000001>;
  709. #size-cells = <0x00000000>;
  710. linux,phandle = <0x00000011>;
  711. phandle = <0x00000011>;
  712. PD_SECO_MU_2 {
  713. reg = <0x000001f7>;
  714. #power-domain-cells = <0x00000000>;
  715. power-domains = <0x00000011>;
  716. linux,phandle = <0x00000008>;
  717. phandle = <0x00000008>;
  718. };
  719. PD_SECO_MU_3 {
  720. reg = <0x000001f8>;
  721. #power-domain-cells = <0x00000000>;
  722. power-domains = <0x00000011>;
  723. linux,phandle = <0x00000009>;
  724. phandle = <0x00000009>;
  725. };
  726. PD_SECO_MU_4 {
  727. reg = <0x000001f9>;
  728. #power-domain-cells = <0x00000000>;
  729. power-domains = <0x00000011>;
  730. linux,phandle = <0x0000000a>;
  731. phandle = <0x0000000a>;
  732. };
  733. };
  734. connectivity_power_domain {
  735. compatible = "nxp,imx8-pd";
  736. reg = <0x0000fff0>;
  737. #power-domain-cells = <0x00000000>;
  738. #address-cells = <0x00000001>;
  739. #size-cells = <0x00000000>;
  740. linux,phandle = <0x00000012>;
  741. phandle = <0x00000012>;
  742. conn_usb0 {
  743. reg = <0x00000103>;
  744. #power-domain-cells = <0x00000000>;
  745. power-domains = <0x00000012>;
  746. #address-cells = <0x00000001>;
  747. #size-cells = <0x00000000>;
  748. wakeup-irq = <0x0000010b>;
  749. linux,phandle = <0x00000013>;
  750. phandle = <0x00000013>;
  751. conn_usb0_phy {
  752. reg = <0x00000105>;
  753. #power-domain-cells = <0x00000000>;
  754. power-domains = <0x00000013>;
  755. wakeup-irq = <0x0000010b>;
  756. linux,phandle = <0x00000093>;
  757. phandle = <0x00000093>;
  758. };
  759. };
  760. conn_usb1 {
  761. reg = <0x00000104>;
  762. #power-domain-cells = <0x00000000>;
  763. power-domains = <0x00000012>;
  764. };
  765. conn_usb2 {
  766. reg = <0x00000106>;
  767. #power-domain-cells = <0x00000000>;
  768. #address-cells = <0x00000001>;
  769. #size-cells = <0x00000000>;
  770. power-domains = <0x00000012>;
  771. wakeup-irq = <0x0000010f>;
  772. linux,phandle = <0x00000014>;
  773. phandle = <0x00000014>;
  774. conn_usb2_phy {
  775. reg = <0x00000107>;
  776. #power-domain-cells = <0x00000000>;
  777. power-domains = <0x00000014>;
  778. wakeup-irq = <0x0000010f>;
  779. linux,phandle = <0x0000009f>;
  780. phandle = <0x0000009f>;
  781. };
  782. };
  783. conn_sdhc0 {
  784. reg = <0x000000f8>;
  785. #power-domain-cells = <0x00000000>;
  786. power-domains = <0x00000012>;
  787. linux,phandle = <0x000000fd>;
  788. phandle = <0x000000fd>;
  789. };
  790. conn_sdhc1 {
  791. reg = <0x000000f9>;
  792. #power-domain-cells = <0x00000000>;
  793. power-domains = <0x00000012>;
  794. linux,phandle = <0x00000101>;
  795. phandle = <0x00000101>;
  796. };
  797. conn_sdhc2 {
  798. reg = <0x000000fa>;
  799. #power-domain-cells = <0x00000000>;
  800. power-domains = <0x00000012>;
  801. linux,phandle = <0x00000108>;
  802. phandle = <0x00000108>;
  803. };
  804. conn_enet0 {
  805. reg = <0x000000fb>;
  806. #power-domain-cells = <0x00000000>;
  807. power-domains = <0x00000012>;
  808. wakeup-irq = <0x00000102>;
  809. linux,phandle = <0x00000109>;
  810. phandle = <0x00000109>;
  811. };
  812. conn_enet1 {
  813. reg = <0x000000fc>;
  814. #power-domain-cells = <0x00000000>;
  815. power-domains = <0x00000012>;
  816. fsl,wakeup_irq = <0x00000106>;
  817. linux,phandle = <0x0000010d>;
  818. phandle = <0x0000010d>;
  819. };
  820. conn_nand {
  821. reg = <0x00000109>;
  822. #power-domain-cells = <0x00000000>;
  823. power-domains = <0x00000012>;
  824. linux,phandle = <0x0000009d>;
  825. phandle = <0x0000009d>;
  826. };
  827. conn_mlb0 {
  828. reg = <0x000000fd>;
  829. #power-domain-cells = <0x00000000>;
  830. power-domains = <0x00000012>;
  831. linux,phandle = <0x0000010e>;
  832. phandle = <0x0000010e>;
  833. };
  834. conn_dma4_ch0 {
  835. reg = <0x00000174>;
  836. #power-domain-cells = <0x00000000>;
  837. power-domains = <0x00000012>;
  838. };
  839. conn_dma4_ch1 {
  840. reg = <0x00000175>;
  841. #power-domain-cells = <0x00000000>;
  842. power-domains = <0x00000012>;
  843. };
  844. conn_dma4_ch2 {
  845. reg = <0x00000176>;
  846. #power-domain-cells = <0x00000000>;
  847. power-domains = <0x00000012>;
  848. };
  849. conn_dma4_ch3 {
  850. reg = <0x00000177>;
  851. #power-domain-cells = <0x00000000>;
  852. power-domains = <0x00000012>;
  853. };
  854. conn_dma4_ch4 {
  855. reg = <0x00000178>;
  856. #power-domain-cells = <0x00000000>;
  857. power-domains = <0x00000012>;
  858. };
  859. };
  860. audio_power_domain {
  861. compatible = "nxp,imx8-pd";
  862. reg = <0x0000fff0>;
  863. #power-domain-cells = <0x00000000>;
  864. #address-cells = <0x00000001>;
  865. #size-cells = <0x00000000>;
  866. linux,phandle = <0x00000015>;
  867. phandle = <0x00000015>;
  868. PD_ASRC_0_RXA {
  869. reg = <0x00000040>;
  870. power-domains = <0x00000015>;
  871. #power-domain-cells = <0x00000000>;
  872. linux,phandle = <0x000000d7>;
  873. phandle = <0x000000d7>;
  874. };
  875. PD_ASRC_0_RXB {
  876. reg = <0x00000041>;
  877. power-domains = <0x00000015>;
  878. #power-domain-cells = <0x00000000>;
  879. linux,phandle = <0x000000d8>;
  880. phandle = <0x000000d8>;
  881. };
  882. PD_ASRC_0_RXC {
  883. reg = <0x00000042>;
  884. power-domains = <0x00000015>;
  885. #power-domain-cells = <0x00000000>;
  886. linux,phandle = <0x000000d9>;
  887. phandle = <0x000000d9>;
  888. };
  889. PD_ASRC_0_TXA {
  890. reg = <0x00000043>;
  891. power-domains = <0x00000015>;
  892. #power-domain-cells = <0x00000000>;
  893. linux,phandle = <0x000000da>;
  894. phandle = <0x000000da>;
  895. };
  896. PD_ASRC_0_TXB {
  897. reg = <0x00000044>;
  898. power-domains = <0x00000015>;
  899. #power-domain-cells = <0x00000000>;
  900. linux,phandle = <0x000000db>;
  901. phandle = <0x000000db>;
  902. };
  903. PD_ASRC_0_TXC {
  904. reg = <0x00000045>;
  905. power-domains = <0x00000015>;
  906. #power-domain-cells = <0x00000000>;
  907. linux,phandle = <0x000000dc>;
  908. phandle = <0x000000dc>;
  909. };
  910. PD_ASRC_1_RXA {
  911. reg = <0x0000006c>;
  912. power-domains = <0x00000015>;
  913. #power-domain-cells = <0x00000000>;
  914. linux,phandle = <0x000000e7>;
  915. phandle = <0x000000e7>;
  916. };
  917. PD_ASRC_1_RXB {
  918. reg = <0x0000006d>;
  919. power-domains = <0x00000015>;
  920. #power-domain-cells = <0x00000000>;
  921. linux,phandle = <0x000000e8>;
  922. phandle = <0x000000e8>;
  923. };
  924. PD_ASRC_1_RXC {
  925. reg = <0x0000006e>;
  926. power-domains = <0x00000015>;
  927. #power-domain-cells = <0x00000000>;
  928. linux,phandle = <0x000000e9>;
  929. phandle = <0x000000e9>;
  930. };
  931. PD_ASRC_1_TXA {
  932. reg = <0x0000006f>;
  933. power-domains = <0x00000015>;
  934. #power-domain-cells = <0x00000000>;
  935. linux,phandle = <0x000000ea>;
  936. phandle = <0x000000ea>;
  937. };
  938. PD_ASRC_1_TXB {
  939. reg = <0x00000070>;
  940. power-domains = <0x00000015>;
  941. #power-domain-cells = <0x00000000>;
  942. linux,phandle = <0x000000eb>;
  943. phandle = <0x000000eb>;
  944. };
  945. PD_ASRC_1_TXC {
  946. reg = <0x00000071>;
  947. power-domains = <0x00000015>;
  948. #power-domain-cells = <0x00000000>;
  949. linux,phandle = <0x000000ec>;
  950. phandle = <0x000000ec>;
  951. };
  952. PD_ESAI_0_RX {
  953. reg = <0x00000046>;
  954. power-domains = <0x00000015>;
  955. #power-domain-cells = <0x00000000>;
  956. linux,phandle = <0x000000dd>;
  957. phandle = <0x000000dd>;
  958. };
  959. PD_ESAI_0_TX {
  960. reg = <0x00000047>;
  961. power-domains = <0x00000015>;
  962. #power-domain-cells = <0x00000000>;
  963. linux,phandle = <0x000000de>;
  964. phandle = <0x000000de>;
  965. };
  966. PD_SPDIF_0_RX {
  967. reg = <0x00000048>;
  968. power-domains = <0x00000015>;
  969. #power-domain-cells = <0x00000000>;
  970. linux,phandle = <0x000000df>;
  971. phandle = <0x000000df>;
  972. };
  973. PD_SPDIF_0_TX {
  974. reg = <0x00000049>;
  975. power-domains = <0x00000015>;
  976. #power-domain-cells = <0x00000000>;
  977. linux,phandle = <0x000000e0>;
  978. phandle = <0x000000e0>;
  979. };
  980. PD_SAI_0_RX {
  981. reg = <0x0000004c>;
  982. power-domains = <0x00000015>;
  983. #power-domain-cells = <0x00000000>;
  984. linux,phandle = <0x000000e1>;
  985. phandle = <0x000000e1>;
  986. };
  987. PD_SAI_0_TX {
  988. reg = <0x0000004d>;
  989. power-domains = <0x00000015>;
  990. #power-domain-cells = <0x00000000>;
  991. linux,phandle = <0x000000e2>;
  992. phandle = <0x000000e2>;
  993. };
  994. PD_SAI_1_RX {
  995. reg = <0x0000004e>;
  996. power-domains = <0x00000015>;
  997. #power-domain-cells = <0x00000000>;
  998. linux,phandle = <0x000000e3>;
  999. phandle = <0x000000e3>;
  1000. };
  1001. PD_SAI_1_TX {
  1002. reg = <0x0000004f>;
  1003. power-domains = <0x00000015>;
  1004. #power-domain-cells = <0x00000000>;
  1005. linux,phandle = <0x000000e4>;
  1006. phandle = <0x000000e4>;
  1007. };
  1008. PD_SAI_2_RX {
  1009. reg = <0x00000050>;
  1010. power-domains = <0x00000015>;
  1011. #power-domain-cells = <0x00000000>;
  1012. linux,phandle = <0x000000e5>;
  1013. phandle = <0x000000e5>;
  1014. };
  1015. PD_SAI_3_RX {
  1016. reg = <0x00000051>;
  1017. power-domains = <0x00000015>;
  1018. #power-domain-cells = <0x00000000>;
  1019. linux,phandle = <0x000000e6>;
  1020. phandle = <0x000000e6>;
  1021. };
  1022. PD_SAI_4_RX {
  1023. reg = <0x00000074>;
  1024. power-domains = <0x00000015>;
  1025. #power-domain-cells = <0x00000000>;
  1026. linux,phandle = <0x000000ed>;
  1027. phandle = <0x000000ed>;
  1028. };
  1029. PD_SAI_4_TX {
  1030. reg = <0x00000075>;
  1031. power-domains = <0x00000015>;
  1032. #power-domain-cells = <0x00000000>;
  1033. linux,phandle = <0x000000ee>;
  1034. phandle = <0x000000ee>;
  1035. };
  1036. PD_SAI_5_TX {
  1037. reg = <0x00000076>;
  1038. power-domains = <0x00000015>;
  1039. #power-domain-cells = <0x00000000>;
  1040. linux,phandle = <0x000000ef>;
  1041. phandle = <0x000000ef>;
  1042. };
  1043. audio_audiopll0 {
  1044. reg = <0x00000145>;
  1045. power-domains = <0x00000015>;
  1046. #power-domain-cells = <0x00000000>;
  1047. #address-cells = <0x00000001>;
  1048. #size-cells = <0x00000000>;
  1049. linux,phandle = <0x00000016>;
  1050. phandle = <0x00000016>;
  1051. audio_audiopll1 {
  1052. reg = <0x000001ec>;
  1053. power-domains = <0x00000016>;
  1054. #power-domain-cells = <0x00000000>;
  1055. #address-cells = <0x00000001>;
  1056. #size-cells = <0x00000000>;
  1057. linux,phandle = <0x00000017>;
  1058. phandle = <0x00000017>;
  1059. audio_audioclk0 {
  1060. reg = <0x000001ed>;
  1061. power-domains = <0x00000017>;
  1062. #power-domain-cells = <0x00000000>;
  1063. #address-cells = <0x00000001>;
  1064. #size-cells = <0x00000000>;
  1065. linux,phandle = <0x00000018>;
  1066. phandle = <0x00000018>;
  1067. audio_audioclk1 {
  1068. reg = <0x000001ee>;
  1069. #power-domain-cells = <0x00000000>;
  1070. power-domains = <0x00000018>;
  1071. #address-cells = <0x00000001>;
  1072. #size-cells = <0x00000000>;
  1073. linux,phandle = <0x00000019>;
  1074. phandle = <0x00000019>;
  1075. audio_asrc0 {
  1076. reg = <0x0000019e>;
  1077. #power-domain-cells = <0x00000000>;
  1078. power-domains = <0x00000019>;
  1079. linux,phandle = <0x000000fa>;
  1080. phandle = <0x000000fa>;
  1081. };
  1082. audio_asrc1 {
  1083. reg = <0x000001c6>;
  1084. #power-domain-cells = <0x00000000>;
  1085. power-domains = <0x00000019>;
  1086. linux,phandle = <0x000000fb>;
  1087. phandle = <0x000000fb>;
  1088. };
  1089. audio_esai0 {
  1090. reg = <0x0000019f>;
  1091. #power-domain-cells = <0x00000000>;
  1092. power-domains = <0x00000019>;
  1093. linux,phandle = <0x00000112>;
  1094. phandle = <0x00000112>;
  1095. };
  1096. audio_spdif0 {
  1097. reg = <0x000001a0>;
  1098. #power-domain-cells = <0x00000000>;
  1099. power-domains = <0x00000019>;
  1100. linux,phandle = <0x00000113>;
  1101. phandle = <0x00000113>;
  1102. };
  1103. audio_sai0 {
  1104. reg = <0x0000013e>;
  1105. #power-domain-cells = <0x00000000>;
  1106. power-domains = <0x00000019>;
  1107. linux,phandle = <0x000000f1>;
  1108. phandle = <0x000000f1>;
  1109. };
  1110. audio_sai1 {
  1111. reg = <0x0000013f>;
  1112. #power-domain-cells = <0x00000000>;
  1113. power-domains = <0x00000019>;
  1114. linux,phandle = <0x000000f3>;
  1115. phandle = <0x000000f3>;
  1116. };
  1117. audio_sai2 {
  1118. reg = <0x00000140>;
  1119. #power-domain-cells = <0x00000000>;
  1120. power-domains = <0x00000019>;
  1121. linux,phandle = <0x000000f4>;
  1122. phandle = <0x000000f4>;
  1123. };
  1124. audio_sai3 {
  1125. reg = <0x000001a2>;
  1126. #power-domain-cells = <0x00000000>;
  1127. power-domains = <0x00000019>;
  1128. linux,phandle = <0x000000f5>;
  1129. phandle = <0x000000f5>;
  1130. };
  1131. audio_sai4 {
  1132. reg = <0x000001a3>;
  1133. #power-domain-cells = <0x00000000>;
  1134. power-domains = <0x00000019>;
  1135. linux,phandle = <0x000000f7>;
  1136. phandle = <0x000000f7>;
  1137. };
  1138. audio_sai5 {
  1139. reg = <0x000001a4>;
  1140. #power-domain-cells = <0x00000000>;
  1141. power-domains = <0x00000019>;
  1142. linux,phandle = <0x000000f8>;
  1143. phandle = <0x000000f8>;
  1144. };
  1145. audio_gpt5 {
  1146. reg = <0x000001a5>;
  1147. #power-domain-cells = <0x00000000>;
  1148. power-domains = <0x00000019>;
  1149. };
  1150. audio_gpt6 {
  1151. reg = <0x000001a6>;
  1152. #power-domain-cells = <0x00000000>;
  1153. power-domains = <0x00000019>;
  1154. };
  1155. audio_gpt7 {
  1156. reg = <0x000001a7>;
  1157. #power-domain-cells = <0x00000000>;
  1158. power-domains = <0x00000019>;
  1159. };
  1160. audio_gpt8 {
  1161. reg = <0x000001a8>;
  1162. #power-domain-cells = <0x00000000>;
  1163. power-domains = <0x00000019>;
  1164. };
  1165. audio_gpt9 {
  1166. reg = <0x000001a9>;
  1167. #power-domain-cells = <0x00000000>;
  1168. power-domains = <0x00000019>;
  1169. };
  1170. audio_gpt10 {
  1171. reg = <0x000001aa>;
  1172. #power-domain-cells = <0x00000000>;
  1173. power-domains = <0x00000019>;
  1174. };
  1175. audio_amix {
  1176. reg = <0x000001ca>;
  1177. #power-domain-cells = <0x00000000>;
  1178. power-domains = <0x00000019>;
  1179. linux,phandle = <0x000000f9>;
  1180. phandle = <0x000000f9>;
  1181. };
  1182. audio_mqs0 {
  1183. reg = <0x000001cb>;
  1184. #power-domain-cells = <0x00000000>;
  1185. power-domains = <0x00000019>;
  1186. linux,phandle = <0x000000fc>;
  1187. phandle = <0x000000fc>;
  1188. };
  1189. audio_mclkout0 {
  1190. reg = <0x000001ef>;
  1191. #power-domain-cells = <0x00000000>;
  1192. power-domains = <0x00000019>;
  1193. linux,phandle = <0x00000089>;
  1194. phandle = <0x00000089>;
  1195. };
  1196. audio_mclkout1 {
  1197. reg = <0x000001f0>;
  1198. #power-domain-cells = <0x00000000>;
  1199. power-domains = <0x00000019>;
  1200. };
  1201. };
  1202. };
  1203. };
  1204. };
  1205. PD_DSP_MU_A {
  1206. reg = <0x000000e2>;
  1207. #power-domain-cells = <0x00000000>;
  1208. power-domains = <0x00000015>;
  1209. #address-cells = <0x00000001>;
  1210. #size-cells = <0x00000000>;
  1211. linux,phandle = <0x0000001a>;
  1212. phandle = <0x0000001a>;
  1213. PD_DSP_MU_B {
  1214. reg = <0x000000eb>;
  1215. #power-domain-cells = <0x00000000>;
  1216. power-domains = <0x0000001a>;
  1217. #address-cells = <0x00000001>;
  1218. #size-cells = <0x00000000>;
  1219. linux,phandle = <0x0000001b>;
  1220. phandle = <0x0000001b>;
  1221. audio_ocram {
  1222. reg = <0x00000201>;
  1223. #power-domain-cells = <0x00000000>;
  1224. power-domains = <0x0000001b>;
  1225. #address-cells = <0x00000001>;
  1226. #size-cells = <0x00000000>;
  1227. linux,phandle = <0x0000001c>;
  1228. phandle = <0x0000001c>;
  1229. audio_dsp {
  1230. reg = <0x00000200>;
  1231. #power-domain-cells = <0x00000000>;
  1232. power-domains = <0x0000001c>;
  1233. linux,phandle = <0x00000111>;
  1234. phandle = <0x00000111>;
  1235. };
  1236. };
  1237. };
  1238. };
  1239. };
  1240. dma_power_domain {
  1241. compatible = "nxp,imx8-pd";
  1242. reg = <0x0000fff0>;
  1243. #power-domain-cells = <0x00000000>;
  1244. #address-cells = <0x00000001>;
  1245. #size-cells = <0x00000000>;
  1246. linux,phandle = <0x0000001d>;
  1247. phandle = <0x0000001d>;
  1248. dma_elcdif_pll {
  1249. reg = <0x00000143>;
  1250. #power-domain-cells = <0x00000000>;
  1251. power-domains = <0x0000001d>;
  1252. #address-cells = <0x00000001>;
  1253. #size-cells = <0x00000000>;
  1254. linux,phandle = <0x0000001e>;
  1255. phandle = <0x0000001e>;
  1256. dma_lcd0 {
  1257. reg = <0x000000bb>;
  1258. #power-domain-cells = <0x00000000>;
  1259. power-domains = <0x0000001e>;
  1260. linux,phandle = <0x00000054>;
  1261. phandle = <0x00000054>;
  1262. };
  1263. };
  1264. dma_flexcan0 {
  1265. reg = <0x00000069>;
  1266. #power-domain-cells = <0x00000000>;
  1267. power-domains = <0x0000001d>;
  1268. wakeup-irq = <0x000000eb>;
  1269. #address-cells = <0x00000001>;
  1270. #size-cells = <0x00000000>;
  1271. linux,phandle = <0x0000001f>;
  1272. phandle = <0x0000001f>;
  1273. dma_flexcan1 {
  1274. reg = <0x0000006a>;
  1275. #power-domain-cells = <0x00000000>;
  1276. power-domains = <0x0000001f>;
  1277. wakeup-irq = <0x000000ec>;
  1278. linux,phandle = <0x00000099>;
  1279. phandle = <0x00000099>;
  1280. };
  1281. dma_flexcan2 {
  1282. reg = <0x0000006b>;
  1283. #power-domain-cells = <0x00000000>;
  1284. power-domains = <0x0000001f>;
  1285. wakeup-irq = <0x000000ed>;
  1286. linux,phandle = <0x0000009b>;
  1287. phandle = <0x0000009b>;
  1288. };
  1289. };
  1290. dma_ftm0 {
  1291. reg = <0x00000067>;
  1292. #power-domain-cells = <0x00000000>;
  1293. power-domains = <0x0000001d>;
  1294. };
  1295. dma_ftm1 {
  1296. reg = <0x00000068>;
  1297. #power-domain-cells = <0x00000000>;
  1298. power-domains = <0x0000001d>;
  1299. };
  1300. dma_adc0 {
  1301. reg = <0x00000065>;
  1302. #power-domain-cells = <0x00000000>;
  1303. power-domains = <0x0000001d>;
  1304. linux,phandle = <0x00000082>;
  1305. phandle = <0x00000082>;
  1306. };
  1307. dma_lpi2c0 {
  1308. reg = <0x00000060>;
  1309. #power-domain-cells = <0x00000000>;
  1310. power-domains = <0x0000001d>;
  1311. linux,phandle = <0x00000085>;
  1312. phandle = <0x00000085>;
  1313. };
  1314. dma_lpi2c1 {
  1315. reg = <0x00000061>;
  1316. #power-domain-cells = <0x00000000>;
  1317. power-domains = <0x0000001d>;
  1318. linux,phandle = <0x0000008f>;
  1319. phandle = <0x0000008f>;
  1320. };
  1321. dma_lpi2c2 {
  1322. reg = <0x00000062>;
  1323. #power-domain-cells = <0x00000000>;
  1324. power-domains = <0x0000001d>;
  1325. linux,phandle = <0x00000091>;
  1326. phandle = <0x00000091>;
  1327. };
  1328. dma_lpi2c3 {
  1329. reg = <0x00000063>;
  1330. #power-domain-cells = <0x00000000>;
  1331. power-domains = <0x0000001d>;
  1332. linux,phandle = <0x00000092>;
  1333. phandle = <0x00000092>;
  1334. };
  1335. dma_lpuart0 {
  1336. reg = <0x00000039>;
  1337. #power-domain-cells = <0x00000000>;
  1338. power-domains = <0x0000001d>;
  1339. wakeup-irq = <0x00000159>;
  1340. linux,phandle = <0x000000bf>;
  1341. phandle = <0x000000bf>;
  1342. };
  1343. PD_UART0_RX {
  1344. reg = <0x000001ae>;
  1345. power-domains = <0x0000001d>;
  1346. #power-domain-cells = <0x00000000>;
  1347. linux,phandle = <0x000000cf>;
  1348. phandle = <0x000000cf>;
  1349. };
  1350. PD_UART0_TX {
  1351. reg = <0x000001af>;
  1352. power-domains = <0x0000001d>;
  1353. #power-domain-cells = <0x00000000>;
  1354. linux,phandle = <0x000000d0>;
  1355. phandle = <0x000000d0>;
  1356. };
  1357. dma_lpuart1 {
  1358. reg = <0x0000003a>;
  1359. #power-domain-cells = <0x00000000>;
  1360. power-domains = <0x0000001d>;
  1361. wakeup-irq = <0x0000015a>;
  1362. linux,phandle = <0x000000c1>;
  1363. phandle = <0x000000c1>;
  1364. };
  1365. PD_UART1_RX {
  1366. reg = <0x000001b0>;
  1367. power-domains = <0x0000001d>;
  1368. #power-domain-cells = <0x00000000>;
  1369. linux,phandle = <0x000000d1>;
  1370. phandle = <0x000000d1>;
  1371. };
  1372. PD_UART1_TX {
  1373. reg = <0x000001b1>;
  1374. power-domains = <0x0000001d>;
  1375. #power-domain-cells = <0x00000000>;
  1376. linux,phandle = <0x000000d2>;
  1377. phandle = <0x000000d2>;
  1378. };
  1379. dma_lpuart2 {
  1380. reg = <0x0000003b>;
  1381. #power-domain-cells = <0x00000000>;
  1382. power-domains = <0x0000001d>;
  1383. wakeup-irq = <0x0000015b>;
  1384. linux,phandle = <0x000000c2>;
  1385. phandle = <0x000000c2>;
  1386. };
  1387. PD_UART2_RX {
  1388. reg = <0x000001b2>;
  1389. power-domains = <0x0000001d>;
  1390. #power-domain-cells = <0x00000000>;
  1391. linux,phandle = <0x000000d3>;
  1392. phandle = <0x000000d3>;
  1393. };
  1394. PD_UART2_TX {
  1395. reg = <0x000001b3>;
  1396. power-domains = <0x0000001d>;
  1397. #power-domain-cells = <0x00000000>;
  1398. linux,phandle = <0x000000d4>;
  1399. phandle = <0x000000d4>;
  1400. };
  1401. dma_lpuart3 {
  1402. reg = <0x0000003c>;
  1403. #power-domain-cells = <0x00000000>;
  1404. power-domains = <0x0000001d>;
  1405. wakeup-irq = <0x0000015c>;
  1406. debug_console;
  1407. linux,phandle = <0x000000c4>;
  1408. phandle = <0x000000c4>;
  1409. };
  1410. PD_UART3_RX {
  1411. reg = <0x000001b4>;
  1412. power-domains = <0x0000001d>;
  1413. #power-domain-cells = <0x00000000>;
  1414. linux,phandle = <0x000000d5>;
  1415. phandle = <0x000000d5>;
  1416. };
  1417. PD_UART3_TX {
  1418. reg = <0x000001b5>;
  1419. power-domains = <0x0000001d>;
  1420. #power-domain-cells = <0x00000000>;
  1421. linux,phandle = <0x000000d6>;
  1422. phandle = <0x000000d6>;
  1423. };
  1424. dma_spi0 {
  1425. reg = <0x00000035>;
  1426. #power-domain-cells = <0x00000000>;
  1427. power-domains = <0x0000001d>;
  1428. wakeup-irq = <0x00000150>;
  1429. linux,phandle = <0x000000b6>;
  1430. phandle = <0x000000b6>;
  1431. };
  1432. PD_LPSPI0_RX {
  1433. reg = <0x000000fe>;
  1434. power-domains = <0x0000001d>;
  1435. #power-domain-cells = <0x00000000>;
  1436. linux,phandle = <0x000000c7>;
  1437. phandle = <0x000000c7>;
  1438. };
  1439. PD_LPSPI0_TX {
  1440. reg = <0x000000ff>;
  1441. power-domains = <0x0000001d>;
  1442. #power-domain-cells = <0x00000000>;
  1443. linux,phandle = <0x000000c8>;
  1444. phandle = <0x000000c8>;
  1445. };
  1446. dma_spi1 {
  1447. reg = <0x00000036>;
  1448. #power-domain-cells = <0x00000000>;
  1449. power-domains = <0x0000001d>;
  1450. };
  1451. PD_LPSPI1_RX {
  1452. reg = <0x00000100>;
  1453. power-domains = <0x0000001d>;
  1454. #power-domain-cells = <0x00000000>;
  1455. linux,phandle = <0x000000c9>;
  1456. phandle = <0x000000c9>;
  1457. };
  1458. PD_LPSPI1_TX {
  1459. reg = <0x00000101>;
  1460. power-domains = <0x0000001d>;
  1461. #power-domain-cells = <0x00000000>;
  1462. linux,phandle = <0x000000ca>;
  1463. phandle = <0x000000ca>;
  1464. };
  1465. dma_spi2 {
  1466. reg = <0x00000037>;
  1467. #power-domain-cells = <0x00000000>;
  1468. power-domains = <0x0000001d>;
  1469. wakeup-irq = <0x00000152>;
  1470. linux,phandle = <0x000000b8>;
  1471. phandle = <0x000000b8>;
  1472. };
  1473. PD_LPSPI2_RX {
  1474. reg = <0x00000102>;
  1475. power-domains = <0x0000001d>;
  1476. #power-domain-cells = <0x00000000>;
  1477. linux,phandle = <0x000000cb>;
  1478. phandle = <0x000000cb>;
  1479. };
  1480. PD_LPSPI2_TX {
  1481. reg = <0x000001ab>;
  1482. power-domains = <0x0000001d>;
  1483. #power-domain-cells = <0x00000000>;
  1484. linux,phandle = <0x000000cc>;
  1485. phandle = <0x000000cc>;
  1486. };
  1487. dma_spi3 {
  1488. reg = <0x00000038>;
  1489. #power-domain-cells = <0x00000000>;
  1490. power-domains = <0x0000001d>;
  1491. };
  1492. PD_LPSPI3_RX {
  1493. reg = <0x000001ac>;
  1494. power-domains = <0x0000001d>;
  1495. #power-domain-cells = <0x00000000>;
  1496. linux,phandle = <0x000000cd>;
  1497. phandle = <0x000000cd>;
  1498. };
  1499. PD_LPSPI3_TX {
  1500. reg = <0x000001ad>;
  1501. power-domains = <0x0000001d>;
  1502. #power-domain-cells = <0x00000000>;
  1503. linux,phandle = <0x000000ce>;
  1504. phandle = <0x000000ce>;
  1505. };
  1506. dma_pwm0 {
  1507. reg = <0x000000bc>;
  1508. #power-domain-cells = <0x00000000>;
  1509. power-domains = <0x0000001d>;
  1510. linux,phandle = <0x00000057>;
  1511. phandle = <0x00000057>;
  1512. };
  1513. };
  1514. gpu-power-domain {
  1515. compatible = "nxp,imx8-pd";
  1516. reg = <0x0000fff0>;
  1517. #power-domain-cells = <0x00000000>;
  1518. #address-cells = <0x00000001>;
  1519. #size-cells = <0x00000000>;
  1520. linux,phandle = <0x00000020>;
  1521. phandle = <0x00000020>;
  1522. gpu0 {
  1523. reg = <0x00000090>;
  1524. #power-domain-cells = <0x00000000>;
  1525. power-domains = <0x00000020>;
  1526. #address-cells = <0x00000001>;
  1527. #size-cells = <0x00000000>;
  1528. linux,phandle = <0x000000b4>;
  1529. phandle = <0x000000b4>;
  1530. };
  1531. };
  1532. vpu-power-domain {
  1533. compatible = "nxp,imx8-pd";
  1534. reg = <0x0000021c>;
  1535. #power-domain-cells = <0x00000000>;
  1536. #address-cells = <0x00000001>;
  1537. #size-cells = <0x00000000>;
  1538. linux,phandle = <0x00000021>;
  1539. phandle = <0x00000021>;
  1540. VPU_ENC_MU {
  1541. reg = <0x00000218>;
  1542. #power-domain-cells = <0x00000000>;
  1543. power-domains = <0x00000021>;
  1544. #address-cells = <0x00000001>;
  1545. #size-cells = <0x00000000>;
  1546. linux,phandle = <0x00000022>;
  1547. phandle = <0x00000022>;
  1548. VPU_ENC {
  1549. reg = <0x00000206>;
  1550. #power-domain-cells = <0x00000000>;
  1551. power-domains = <0x00000022>;
  1552. linux,phandle = <0x00000123>;
  1553. phandle = <0x00000123>;
  1554. };
  1555. };
  1556. VPU_DEC_MU {
  1557. reg = <0x00000217>;
  1558. #power-domain-cells = <0x00000000>;
  1559. power-domains = <0x00000021>;
  1560. #address-cells = <0x00000001>;
  1561. #size-cells = <0x00000000>;
  1562. linux,phandle = <0x00000023>;
  1563. phandle = <0x00000023>;
  1564. VPU_DEC {
  1565. reg = <0x00000205>;
  1566. #power-domain-cells = <0x00000000>;
  1567. power-domains = <0x00000023>;
  1568. linux,phandle = <0x0000011d>;
  1569. phandle = <0x0000011d>;
  1570. };
  1571. };
  1572. };
  1573. hsio-power-domain {
  1574. compatible = "nxp,imx8-pd";
  1575. reg = <0x0000fff0>;
  1576. #power-domain-cells = <0x00000000>;
  1577. #address-cells = <0x00000001>;
  1578. #size-cells = <0x00000000>;
  1579. linux,phandle = <0x00000024>;
  1580. phandle = <0x00000024>;
  1581. hsio_gpio {
  1582. reg = <0x000000ac>;
  1583. #power-domain-cells = <0x00000000>;
  1584. power-domains = <0x00000024>;
  1585. #address-cells = <0x00000001>;
  1586. #size-cells = <0x00000000>;
  1587. linux,phandle = <0x00000025>;
  1588. phandle = <0x00000025>;
  1589. hsio_serdes_1 {
  1590. reg = <0x000000ab>;
  1591. #power-domain-cells = <0x00000000>;
  1592. power-domains = <0x00000025>;
  1593. #address-cells = <0x00000001>;
  1594. #size-cells = <0x00000000>;
  1595. linux,phandle = <0x00000026>;
  1596. phandle = <0x00000026>;
  1597. hsio_pcie1 {
  1598. reg = <0x000000a9>;
  1599. #power-domain-cells = <0x00000000>;
  1600. power-domains = <0x00000026>;
  1601. linux,phandle = <0x00000118>;
  1602. phandle = <0x00000118>;
  1603. };
  1604. };
  1605. };
  1606. };
  1607. cm40_power_domain {
  1608. compatible = "nxp,imx8-pd";
  1609. reg = <0x0000fff0>;
  1610. #power-domain-cells = <0x00000000>;
  1611. #address-cells = <0x00000001>;
  1612. #size-cells = <0x00000000>;
  1613. linux,phandle = <0x00000027>;
  1614. phandle = <0x00000027>;
  1615. cm40_i2c {
  1616. reg = <0x00000120>;
  1617. #power-domain-cells = <0x00000000>;
  1618. power-domains = <0x00000027>;
  1619. linux,phandle = <0x0000003b>;
  1620. phandle = <0x0000003b>;
  1621. };
  1622. cm40_intmux {
  1623. reg = <0x00000121>;
  1624. #power-domain-cells = <0x00000000>;
  1625. power-domains = <0x00000027>;
  1626. linux,phandle = <0x00000039>;
  1627. phandle = <0x00000039>;
  1628. };
  1629. };
  1630. dc0_power_domain {
  1631. compatible = "nxp,imx8-pd";
  1632. reg = <0x00000020>;
  1633. #power-domain-cells = <0x00000000>;
  1634. #address-cells = <0x00000001>;
  1635. #size-cells = <0x00000000>;
  1636. linux,phandle = <0x00000028>;
  1637. phandle = <0x00000028>;
  1638. dc0_pll0 {
  1639. reg = <0x00000022>;
  1640. #power-domain-cells = <0x00000000>;
  1641. power-domains = <0x00000028>;
  1642. #address-cells = <0x00000001>;
  1643. #size-cells = <0x00000000>;
  1644. linux,phandle = <0x00000029>;
  1645. phandle = <0x00000029>;
  1646. dc0_pll1 {
  1647. reg = <0x00000023>;
  1648. #power-domain-cells = <0x00000000>;
  1649. power-domains = <0x00000029>;
  1650. linux,phandle = <0x00000046>;
  1651. phandle = <0x00000046>;
  1652. };
  1653. };
  1654. mipi0_dsi_power_domain {
  1655. reg = <0x00000189>;
  1656. #power-domain-cells = <0x00000000>;
  1657. power-domains = <0x00000028>;
  1658. #address-cells = <0x00000001>;
  1659. #size-cells = <0x00000000>;
  1660. linux,phandle = <0x0000002a>;
  1661. phandle = <0x0000002a>;
  1662. lvds0_power_domain {
  1663. reg = <0x0000010a>;
  1664. #power-domain-cells = <0x00000000>;
  1665. power-domains = <0x0000002a>;
  1666. linux,phandle = <0x0000005f>;
  1667. phandle = <0x0000005f>;
  1668. };
  1669. PD_AUX_LVDS0 {
  1670. reg = <0x0000010a>;
  1671. #power-domain-cells = <0x00000000>;
  1672. power-domains = <0x0000002a>;
  1673. #address-cells = <0x00000001>;
  1674. #size-cells = <0x00000000>;
  1675. linux,phandle = <0x0000002b>;
  1676. phandle = <0x0000002b>;
  1677. PD_DUAL_LVDS1 {
  1678. reg = <0x0000010e>;
  1679. #power-domain-cells = <0x00000000>;
  1680. power-domains = <0x0000002b>;
  1681. };
  1682. };
  1683. mipi0_dsi_i2c0 {
  1684. reg = <0x0000018b>;
  1685. #power-domain-cells = <0x00000000>;
  1686. power-domains = <0x0000002a>;
  1687. linux,phandle = <0x00000067>;
  1688. phandle = <0x00000067>;
  1689. };
  1690. mipi0_dsi_i2c1 {
  1691. reg = <0x0000018c>;
  1692. #power-domain-cells = <0x00000000>;
  1693. power-domains = <0x0000002a>;
  1694. };
  1695. mipi0_dsi_pwm0 {
  1696. reg = <0x0000018a>;
  1697. #power-domain-cells = <0x00000000>;
  1698. power-domains = <0x0000002a>;
  1699. linux,phandle = <0x00000066>;
  1700. phandle = <0x00000066>;
  1701. };
  1702. };
  1703. mipi1_dsi_power_domain {
  1704. reg = <0x0000018d>;
  1705. #power-domain-cells = <0x00000000>;
  1706. power-domains = <0x00000028>;
  1707. #address-cells = <0x00000001>;
  1708. #size-cells = <0x00000000>;
  1709. linux,phandle = <0x0000002c>;
  1710. phandle = <0x0000002c>;
  1711. lvds1_power_domain {
  1712. reg = <0x0000010e>;
  1713. #power-domain-cells = <0x00000000>;
  1714. power-domains = <0x0000002c>;
  1715. linux,phandle = <0x0000006f>;
  1716. phandle = <0x0000006f>;
  1717. };
  1718. PD_AUX_LVDS1 {
  1719. reg = <0x0000010e>;
  1720. #power-domain-cells = <0x00000000>;
  1721. power-domains = <0x0000002c>;
  1722. #address-cells = <0x00000001>;
  1723. #size-cells = <0x00000000>;
  1724. linux,phandle = <0x0000002d>;
  1725. phandle = <0x0000002d>;
  1726. PD_DUAL_LVDS0 {
  1727. reg = <0x0000010a>;
  1728. #power-domain-cells = <0x00000000>;
  1729. power-domains = <0x0000002d>;
  1730. };
  1731. };
  1732. mipi1_dsi_i2c0 {
  1733. reg = <0x0000018f>;
  1734. #power-domain-cells = <0x00000000>;
  1735. power-domains = <0x0000002c>;
  1736. linux,phandle = <0x0000007d>;
  1737. phandle = <0x0000007d>;
  1738. };
  1739. mipi1_dsi_i2c1 {
  1740. reg = <0x00000190>;
  1741. #power-domain-cells = <0x00000000>;
  1742. power-domains = <0x0000002c>;
  1743. };
  1744. mipi1_dsi_pwm0 {
  1745. reg = <0x0000018e>;
  1746. #power-domain-cells = <0x00000000>;
  1747. power-domains = <0x0000002c>;
  1748. linux,phandle = <0x0000007c>;
  1749. phandle = <0x0000007c>;
  1750. };
  1751. };
  1752. };
  1753. imaging_power_domain {
  1754. compatible = "nxp,imx8-pd";
  1755. reg = <0x00000179>;
  1756. #power-domain-cells = <0x00000000>;
  1757. #address-cells = <0x00000001>;
  1758. #size-cells = <0x00000000>;
  1759. linux,phandle = <0x0000002e>;
  1760. phandle = <0x0000002e>;
  1761. mipi_csi0_power_domain {
  1762. reg = <0x00000191>;
  1763. #power-domain-cells = <0x00000000>;
  1764. #address-cells = <0x00000001>;
  1765. #size-cells = <0x00000000>;
  1766. power-domains = <0x0000002e>;
  1767. linux,phandle = <0x0000002f>;
  1768. phandle = <0x0000002f>;
  1769. mipi_csi0_i2c0 {
  1770. reg = <0x00000193>;
  1771. #power-domain-cells = <0x00000000>;
  1772. power-domains = <0x0000002f>;
  1773. linux,phandle = <0x00000038>;
  1774. phandle = <0x00000038>;
  1775. };
  1776. mipi_csi0_pwm {
  1777. reg = <0x00000192>;
  1778. #power-domain-cells = <0x00000000>;
  1779. power-domains = <0x0000002f>;
  1780. };
  1781. };
  1782. parallel_csi_power_domain {
  1783. reg = <0x00000146>;
  1784. #power-domain-cells = <0x00000000>;
  1785. #address-cells = <0x00000001>;
  1786. #size-cells = <0x00000000>;
  1787. power-domains = <0x0000002e>;
  1788. linux,phandle = <0x00000030>;
  1789. phandle = <0x00000030>;
  1790. parallel_csi_i2c {
  1791. reg = <0x00000149>;
  1792. #power-domain-cells = <0x00000000>;
  1793. power-domains = <0x00000030>;
  1794. };
  1795. parallel_csi_pwm {
  1796. reg = <0x00000147>;
  1797. #power-domain-cells = <0x00000000>;
  1798. power-domains = <0x00000030>;
  1799. };
  1800. parallel_csi_pll {
  1801. reg = <0x0000014a>;
  1802. #power-domain-cells = <0x00000000>;
  1803. power-domains = <0x00000030>;
  1804. };
  1805. };
  1806. imaging_pdma1 {
  1807. reg = <0x0000017a>;
  1808. #power-domain-cells = <0x00000000>;
  1809. power-domains = <0x0000002e>;
  1810. linux,phandle = <0x00000072>;
  1811. phandle = <0x00000072>;
  1812. };
  1813. imaging_pdma2 {
  1814. reg = <0x0000017b>;
  1815. #power-domain-cells = <0x00000000>;
  1816. power-domains = <0x0000002e>;
  1817. linux,phandle = <0x00000073>;
  1818. phandle = <0x00000073>;
  1819. };
  1820. imaging_pdma3 {
  1821. reg = <0x0000017c>;
  1822. #power-domain-cells = <0x00000000>;
  1823. power-domains = <0x0000002e>;
  1824. linux,phandle = <0x00000074>;
  1825. phandle = <0x00000074>;
  1826. };
  1827. imaging_pdma4 {
  1828. reg = <0x0000017d>;
  1829. #power-domain-cells = <0x00000000>;
  1830. power-domains = <0x0000002e>;
  1831. linux,phandle = <0x00000075>;
  1832. phandle = <0x00000075>;
  1833. };
  1834. imaging_pdma5 {
  1835. reg = <0x0000017e>;
  1836. #power-domain-cells = <0x00000000>;
  1837. power-domains = <0x0000002e>;
  1838. linux,phandle = <0x00000076>;
  1839. phandle = <0x00000076>;
  1840. };
  1841. imaging_pdma6 {
  1842. reg = <0x0000017f>;
  1843. #power-domain-cells = <0x00000000>;
  1844. power-domains = <0x0000002e>;
  1845. linux,phandle = <0x00000077>;
  1846. phandle = <0x00000077>;
  1847. };
  1848. imaging_pdma7 {
  1849. reg = <0x00000180>;
  1850. #power-domain-cells = <0x00000000>;
  1851. power-domains = <0x0000002e>;
  1852. linux,phandle = <0x00000078>;
  1853. phandle = <0x00000078>;
  1854. };
  1855. PD_JPEG_DEC_MP {
  1856. reg = <0x00000214>;
  1857. #power-domain-cells = <0x00000000>;
  1858. power-domains = <0x0000002e>;
  1859. #address-cells = <0x00000001>;
  1860. #size-cells = <0x00000000>;
  1861. linux,phandle = <0x00000031>;
  1862. phandle = <0x00000031>;
  1863. imaging_jpeg_dec {
  1864. reg = <0x00000181>;
  1865. #power-domain-cells = <0x00000000>;
  1866. power-domains = <0x00000031>;
  1867. linux,phandle = <0x0000007a>;
  1868. phandle = <0x0000007a>;
  1869. };
  1870. };
  1871. PD_JPEG_ENC_MP {
  1872. reg = <0x00000215>;
  1873. #power-domain-cells = <0x00000000>;
  1874. power-domains = <0x0000002e>;
  1875. #address-cells = <0x00000001>;
  1876. #size-cells = <0x00000000>;
  1877. linux,phandle = <0x00000032>;
  1878. phandle = <0x00000032>;
  1879. imaging_jpeg_enc {
  1880. reg = <0x00000185>;
  1881. #power-domain-cells = <0x00000000>;
  1882. power-domains = <0x00000032>;
  1883. linux,phandle = <0x0000007b>;
  1884. phandle = <0x0000007b>;
  1885. };
  1886. };
  1887. };
  1888. caam_power_domain {
  1889. compatible = "nxp,imx8-pd";
  1890. reg = <0x0000fff0>;
  1891. #power-domain-cells = <0x00000000>;
  1892. #address-cells = <0x00000001>;
  1893. #size-cells = <0x00000000>;
  1894. linux,phandle = <0x00000033>;
  1895. phandle = <0x00000033>;
  1896. caam_job_ring1 {
  1897. reg = <0x000001f4>;
  1898. #power-domain-cells = <0x00000000>;
  1899. power-domains = <0x00000033>;
  1900. linux,phandle = <0x00000126>;
  1901. phandle = <0x00000126>;
  1902. };
  1903. caam_job_ring2 {
  1904. reg = <0x000001f5>;
  1905. #power-domain-cells = <0x00000000>;
  1906. power-domains = <0x00000033>;
  1907. linux,phandle = <0x00000127>;
  1908. phandle = <0x00000127>;
  1909. };
  1910. caam_job_ring3 {
  1911. reg = <0x000001f6>;
  1912. #power-domain-cells = <0x00000000>;
  1913. power-domains = <0x00000033>;
  1914. linux,phandle = <0x00000128>;
  1915. phandle = <0x00000128>;
  1916. };
  1917. };
  1918. };
  1919. thermal-sensor {
  1920. compatible = "nxp,imx8qxp-sc-tsens";
  1921. tsens-num = <0x00000003>;
  1922. #thermal-sensor-cells = <0x00000001>;
  1923. linux,phandle = <0x00000034>;
  1924. phandle = <0x00000034>;
  1925. };
  1926. thermal-zones {
  1927. cpu-thermal0 {
  1928. polling-delay-passive = <0x000000fa>;
  1929. polling-delay = <0x000007d0>;
  1930. thermal-sensors = <0x00000034 0x00000000>;
  1931. trips {
  1932. trip0 {
  1933. temperature = <0x0001a1f8>;
  1934. hysteresis = <0x000007d0>;
  1935. type = "passive";
  1936. linux,phandle = <0x00000035>;
  1937. phandle = <0x00000035>;
  1938. };
  1939. trip1 {
  1940. temperature = <0x0001f018>;
  1941. hysteresis = <0x000007d0>;
  1942. type = "critical";
  1943. };
  1944. };
  1945. cooling-maps {
  1946. map0 {
  1947. trip = <0x00000035>;
  1948. cooling-device = <0x00000004 0xffffffff 0xffffffff>;
  1949. };
  1950. };
  1951. };
  1952. drc-thermal0 {
  1953. polling-delay-passive = <0x000000fa>;
  1954. polling-delay = <0x000007d0>;
  1955. thermal-sensors = <0x00000034 0x00000001>;
  1956. status = "disabled";
  1957. trips {
  1958. trip0 {
  1959. temperature = <0x0001a1f8>;
  1960. hysteresis = <0x000007d0>;
  1961. type = "passive";
  1962. };
  1963. trip1 {
  1964. temperature = <0x0001f018>;
  1965. hysteresis = <0x000007d0>;
  1966. type = "critical";
  1967. };
  1968. };
  1969. };
  1970. pmic-thermal0 {
  1971. polling-delay-passive = <0x000000fa>;
  1972. polling-delay = <0x000007d0>;
  1973. thermal-sensors = <0x00000034 0x00000002>;
  1974. trips {
  1975. trip0 {
  1976. temperature = <0x00013880>;
  1977. hysteresis = <0x000007d0>;
  1978. type = "passive";
  1979. linux,phandle = <0x00000036>;
  1980. phandle = <0x00000036>;
  1981. };
  1982. trip1 {
  1983. temperature = <0x0001e848>;
  1984. hysteresis = <0x000007d0>;
  1985. type = "critical";
  1986. };
  1987. };
  1988. cooling-maps {
  1989. map0 {
  1990. trip = <0x00000036>;
  1991. cooling-device = <0x00000004 0xffffffff 0xffffffff>;
  1992. };
  1993. };
  1994. };
  1995. };
  1996. irqsteer@58220000 {
  1997. compatible = "nxp,imx-irqsteer";
  1998. reg = <0x00000000 0x58220000 0x00000000 0x00001000>;
  1999. interrupts = <0x00000000 0x00000140 0x00000004>;
  2000. interrupt-controller;
  2001. interrupt-parent = <0x00000001>;
  2002. #interrupt-cells = <0x00000002>;
  2003. clocks = <0x00000003 0x00000000>;
  2004. clock-names = "ipg";
  2005. power-domains = <0x0000002f>;
  2006. linux,phandle = <0x00000037>;
  2007. phandle = <0x00000037>;
  2008. };
  2009. i2c@58226000 {
  2010. compatible = "fsl,imx8qm-lpi2c";
  2011. reg = <0x00000000 0x58226000 0x00000000 0x00001000>;
  2012. interrupts = <0x00000008 0x00000004>;
  2013. interrupt-parent = <0x00000037>;
  2014. clocks = <0x00000003 0x00000139 0x00000003 0x00000138>;
  2015. clock-names = "per", "ipg";
  2016. assigned-clocks = <0x00000003 0x00000139>;
  2017. assigned-clock-rates = <0x016e3600>;
  2018. power-domains = <0x00000038>;
  2019. status = "disabled";
  2020. };
  2021. intmux@37400000 {
  2022. compatible = "nxp,imx-intmux";
  2023. reg = <0x00000000 0x37400000 0x00000000 0x00001000>;
  2024. interrupts = * 0x0000000093008240 [0x00000060];
  2025. interrupt-controller;
  2026. interrupt-parent = <0x00000001>;
  2027. #interrupt-cells = <0x00000002>;
  2028. clocks = <0x00000003 0x000001e5>;
  2029. clock-names = "ipg";
  2030. power-domains = <0x00000039>;
  2031. status = "disabled";
  2032. linux,phandle = <0x0000003a>;
  2033. phandle = <0x0000003a>;
  2034. };
  2035. i2c@37230000 {
  2036. compatible = "fsl,imx8qm-lpi2c";
  2037. reg = <0x00000000 0x37230000 0x00000000 0x00001000>;
  2038. interrupts = <0x00000009 0x00000004>;
  2039. interrupt-parent = <0x0000003a>;
  2040. clocks = <0x00000003 0x000001e7 0x00000003 0x000001e8>;
  2041. clock-names = "per", "ipg";
  2042. assigned-clocks = <0x00000003 0x000001e7>;
  2043. assigned-clock-rates = <0x016e3600>;
  2044. power-domains = <0x0000003b>;
  2045. status = "disabled";
  2046. };
  2047. dpu_intsteer@56000000 {
  2048. compatible = "fsl,imx8qxp-dpu-intsteer", "syscon";
  2049. reg = <0x00000000 0x56000000 0x00000000 0x00010000>;
  2050. linux,phandle = <0x00000045>;
  2051. phandle = <0x00000045>;
  2052. };
  2053. pixel-combiner@56020000 {
  2054. compatible = "fsl,imx8qxp-pixel-combiner";
  2055. reg = <0x00000000 0x56020000 0x00000000 0x00010000>;
  2056. power-domains = <0x00000028>;
  2057. status = "okay";
  2058. linux,phandle = <0x0000004d>;
  2059. phandle = <0x0000004d>;
  2060. };
  2061. prg@56040000 {
  2062. compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
  2063. reg = <0x00000000 0x56040000 0x00000000 0x00010000>;
  2064. clocks = <0x00000003 0x000000fb 0x00000003 0x000000fa>;
  2065. clock-names = "apb", "rtram";
  2066. power-domains = <0x00000028>;
  2067. status = "okay";
  2068. linux,phandle = <0x0000003c>;
  2069. phandle = <0x0000003c>;
  2070. };
  2071. prg@56050000 {
  2072. compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
  2073. reg = <0x00000000 0x56050000 0x00000000 0x00010000>;
  2074. clocks = <0x00000003 0x000000fd 0x00000003 0x000000fc>;
  2075. clock-names = "apb", "rtram";
  2076. power-domains = <0x00000028>;
  2077. status = "okay";
  2078. linux,phandle = <0x0000003d>;
  2079. phandle = <0x0000003d>;
  2080. };
  2081. prg@56060000 {
  2082. compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
  2083. reg = <0x00000000 0x56060000 0x00000000 0x00010000>;
  2084. clocks = <0x00000003 0x000000ff 0x00000003 0x000000fe>;
  2085. clock-names = "apb", "rtram";
  2086. power-domains = <0x00000028>;
  2087. status = "okay";
  2088. linux,phandle = <0x0000003e>;
  2089. phandle = <0x0000003e>;
  2090. };
  2091. prg@56070000 {
  2092. compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
  2093. reg = <0x00000000 0x56070000 0x00000000 0x00010000>;
  2094. clocks = <0x00000003 0x00000101 0x00000003 0x00000100>;
  2095. clock-names = "apb", "rtram";
  2096. power-domains = <0x00000028>;
  2097. status = "okay";
  2098. linux,phandle = <0x0000003f>;
  2099. phandle = <0x0000003f>;
  2100. };
  2101. prg@56080000 {
  2102. compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
  2103. reg = <0x00000000 0x56080000 0x00000000 0x00010000>;
  2104. clocks = <0x00000003 0x00000103 0x00000003 0x00000102>;
  2105. clock-names = "apb", "rtram";
  2106. power-domains = <0x00000028>;
  2107. status = "okay";
  2108. linux,phandle = <0x00000040>;
  2109. phandle = <0x00000040>;
  2110. };
  2111. prg@56090000 {
  2112. compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
  2113. reg = <0x00000000 0x56090000 0x00000000 0x00010000>;
  2114. clocks = <0x00000003 0x00000105 0x00000003 0x00000104>;
  2115. clock-names = "apb", "rtram";
  2116. power-domains = <0x00000028>;
  2117. status = "okay";
  2118. linux,phandle = <0x00000041>;
  2119. phandle = <0x00000041>;
  2120. };
  2121. prg@560a0000 {
  2122. compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
  2123. reg = <0x00000000 0x560a0000 0x00000000 0x00010000>;
  2124. clocks = <0x00000003 0x00000107 0x00000003 0x00000106>;
  2125. clock-names = "apb", "rtram";
  2126. power-domains = <0x00000028>;
  2127. status = "okay";
  2128. linux,phandle = <0x00000042>;
  2129. phandle = <0x00000042>;
  2130. };
  2131. prg@560b0000 {
  2132. compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
  2133. reg = <0x00000000 0x560b0000 0x00000000 0x00010000>;
  2134. clocks = <0x00000003 0x00000109 0x00000003 0x00000108>;
  2135. clock-names = "apb", "rtram";
  2136. power-domains = <0x00000028>;
  2137. status = "okay";
  2138. linux,phandle = <0x00000043>;
  2139. phandle = <0x00000043>;
  2140. };
  2141. prg@560c0000 {
  2142. compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
  2143. reg = <0x00000000 0x560c0000 0x00000000 0x00010000>;
  2144. clocks = <0x00000003 0x0000010b 0x00000003 0x0000010a>;
  2145. clock-names = "apb", "rtram";
  2146. power-domains = <0x00000028>;
  2147. status = "okay";
  2148. linux,phandle = <0x00000044>;
  2149. phandle = <0x00000044>;
  2150. };
  2151. dpr-channel@560d0000 {
  2152. compatible = "fsl,imx8qxp-dpr-channel", "fsl,imx8qm-dpr-channel";
  2153. reg = <0x00000000 0x560d0000 0x00000000 0x00010000>;
  2154. fsl,sc-resource = <0x00000013>;
  2155. fsl,prgs = <0x0000003c>;
  2156. clocks = <0x00000003 0x0000010c 0x00000003 0x0000010d 0x00000003 0x0000010e>;
  2157. clock-names = "apb", "b", "rtram";
  2158. power-domains = <0x00000028>;
  2159. status = "okay";
  2160. linux,phandle = <0x00000047>;
  2161. phandle = <0x00000047>;
  2162. };
  2163. dpr-channel@560e0000 {
  2164. compatible = "fsl,imx8qxp-dpr-channel", "fsl,imx8qm-dpr-channel";
  2165. reg = <0x00000000 0x560e0000 0x00000000 0x00010000>;
  2166. fsl,sc-resource = <0x00000014>;
  2167. fsl,prgs = <0x0000003d 0x0000003c>;
  2168. clocks = <0x00000003 0x0000010c 0x00000003 0x0000010d 0x00000003 0x0000010e>;
  2169. clock-names = "apb", "b", "rtram";
  2170. power-domains = <0x00000028>;
  2171. status = "okay";
  2172. linux,phandle = <0x00000048>;
  2173. phandle = <0x00000048>;
  2174. };
  2175. dpr-channel@560f0000 {
  2176. compatible = "fsl,imx8qxp-dpr-channel", "fsl,imx8qm-dpr-channel";
  2177. reg = <0x00000000 0x560f0000 0x00000000 0x00010000>;
  2178. fsl,sc-resource = <0x0000001e>;
  2179. fsl,prgs = <0x0000003e>;
  2180. clocks = <0x00000003 0x0000010c 0x00000003 0x0000010d 0x00000003 0x0000010e>;
  2181. clock-names = "apb", "b", "rtram";
  2182. power-domains = <0x00000028>;
  2183. status = "okay";
  2184. linux,phandle = <0x00000049>;
  2185. phandle = <0x00000049>;
  2186. };
  2187. dpr-channel@56100000 {
  2188. compatible = "fsl,imx8qxp-dpr-channel", "fsl,imx8qm-dpr-channel";
  2189. reg = <0x00000000 0x56100000 0x00000000 0x00010000>;
  2190. fsl,sc-resource = <0x0000001c>;
  2191. fsl,prgs = <0x0000003f 0x00000040>;
  2192. clocks = <0x00000003 0x000001fe 0x00000003 0x000001ff 0x00000003 0x0000010f>;
  2193. clock-names = "apb", "b", "rtram";
  2194. power-domains = <0x00000028>;
  2195. status = "okay";
  2196. linux,phandle = <0x0000004a>;
  2197. phandle = <0x0000004a>;
  2198. };
  2199. dpr-channel@56110000 {
  2200. compatible = "fsl,imx8qxp-dpr-channel", "fsl,imx8qm-dpr-channel";
  2201. reg = <0x00000000 0x56110000 0x00000000 0x00010000>;
  2202. fsl,sc-resource = <0x0000001d>;
  2203. fsl,prgs = <0x00000041 0x00000042>;
  2204. clocks = <0x00000003 0x000001fe 0x00000003 0x000001ff 0x00000003 0x0000010f>;
  2205. clock-names = "apb", "b", "rtram";
  2206. power-domains = <0x00000028>;
  2207. status = "okay";
  2208. linux,phandle = <0x0000004b>;
  2209. phandle = <0x0000004b>;
  2210. };
  2211. dpr-channel@56120000 {
  2212. compatible = "fsl,imx8qxp-dpr-channel", "fsl,imx8qm-dpr-channel";
  2213. reg = <0x00000000 0x56120000 0x00000000 0x00010000>;
  2214. fsl,sc-resource = <0x00000019>;
  2215. fsl,prgs = <0x00000043 0x00000044>;
  2216. clocks = <0x00000003 0x000001fe 0x00000003 0x000001ff 0x00000003 0x0000010f>;
  2217. clock-names = "apb", "b", "rtram";
  2218. power-domains = <0x00000028>;
  2219. status = "okay";
  2220. linux,phandle = <0x0000004c>;
  2221. phandle = <0x0000004c>;
  2222. };
  2223. dpu@56180000 {
  2224. #address-cells = <0x00000001>;
  2225. #size-cells = <0x00000000>;
  2226. compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu";
  2227. reg = <0x00000000 0x56180000 0x00000000 0x00040000>;
  2228. intsteer = <0x00000045>;
  2229. interrupts = * 0x0000000093009430 [0x00000078];
  2230. interrupt-names = "irq_common", "irq_stream0a", "irq_stream0b", "irq_stream1a", "irq_stream1b", "irq_reserved0", "irq_reserved1", "irq_blit", "irq_dpr0", "irq_dpr1";
  2231. clocks = <0x00000003 0x000001bd 0x00000003 0x000001be 0x00000003 0x000000f8 0x00000003 0x000000f9>;
  2232. clock-names = "pll0", "pll1", "disp0", "disp1";
  2233. power-domains = <0x00000046>;
  2234. fsl,dpr-channels = <0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c>;
  2235. fsl,pixel-combiner = <0x0000004d>;
  2236. status = "okay";
  2237. port@0 {
  2238. reg = <0x00000000>;
  2239. linux,phandle = <0x00000115>;
  2240. phandle = <0x00000115>;
  2241. lvds0-endpoint {
  2242. remote-endpoint = <0x0000004e>;
  2243. linux,phandle = <0x00000064>;
  2244. phandle = <0x00000064>;
  2245. };
  2246. lvds1-endpoint {
  2247. remote-endpoint = <0x0000004f>;
  2248. linux,phandle = <0x00000065>;
  2249. phandle = <0x00000065>;
  2250. };
  2251. mipi-dsi-endpoint {
  2252. remote-endpoint = <0x00000050>;
  2253. linux,phandle = <0x0000005d>;
  2254. phandle = <0x0000005d>;
  2255. };
  2256. };
  2257. port@1 {
  2258. reg = <0x00000001>;
  2259. linux,phandle = <0x00000116>;
  2260. phandle = <0x00000116>;
  2261. lvds0-endpoint {
  2262. remote-endpoint = <0x00000051>;
  2263. linux,phandle = <0x00000070>;
  2264. phandle = <0x00000070>;
  2265. };
  2266. lvds1-endpoint {
  2267. remote-endpoint = <0x00000052>;
  2268. linux,phandle = <0x00000071>;
  2269. phandle = <0x00000071>;
  2270. };
  2271. mipi-dsi-endpoint {
  2272. remote-endpoint = <0x00000053>;
  2273. linux,phandle = <0x0000006d>;
  2274. phandle = <0x0000006d>;
  2275. };
  2276. };
  2277. };
  2278. irqsteer@56220000 {
  2279. compatible = "nxp,imx-irqsteer";
  2280. reg = <0x00000000 0x56220000 0x00000000 0x00001000>;
  2281. interrupts = <0x00000000 0x0000003b 0x00000004>;
  2282. interrupt-controller;
  2283. interrupt-parent = <0x00000001>;
  2284. #interrupt-cells = <0x00000002>;
  2285. clocks = <0x00000003 0x000001cb>;
  2286. clock-names = "ipg";
  2287. power-domains = <0x0000002a>;
  2288. linux,phandle = <0x00000059>;
  2289. phandle = <0x00000059>;
  2290. };
  2291. lcdif@5a180000 {
  2292. compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
  2293. reg = <0x00000000 0x5a180000 0x00000000 0x00010000>;
  2294. clocks = <0x00000003 0x000000af 0x00000003 0x00000215 0x00000003 0x000000ad>;
  2295. clock-names = "pix", "disp_axi", "axi";
  2296. assigned-clocks = <0x00000003 0x00000218 0x00000003 0x00000213 0x00000003 0x00000216>;
  2297. assigned-clock-rates = <0x00000000 0x00000000 0x2fec1100>;
  2298. interrupts = <0x00000000 0x0000003e 0x00000004>;
  2299. power-domains = <0x00000054>;
  2300. status = "okay";
  2301. pinctrl-names = "default";
  2302. pinctrl-0 = <0x00000055>;
  2303. bus-width = <0x00000012>;
  2304. port@0 {
  2305. lcdif-endpoint {
  2306. remote-endpoint = <0x00000056>;
  2307. linux,phandle = <0x0000012c>;
  2308. phandle = <0x0000012c>;
  2309. };
  2310. };
  2311. };
  2312. pwm@5a190000 {
  2313. compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
  2314. reg = <0x00000000 0x5a190000 0x00000000 0x00001000>;
  2315. clocks = <0x00000003 0x000000aa 0x00000003 0x000000ac>;
  2316. clock-names = "ipg", "per";
  2317. assigned-clocks = <0x00000003 0x000000ac>;
  2318. assigned-clock-rates = <0x016e3600>;
  2319. #pwm-cells = <0x00000003>;
  2320. power-domains = <0x00000057>;
  2321. status = "okay";
  2322. pinctrl-names = "default";
  2323. pinctrl-0 = <0x00000058>;
  2324. linux,phandle = <0x0000012a>;
  2325. phandle = <0x0000012a>;
  2326. };
  2327. csr@56221000 {
  2328. compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon";
  2329. reg = <0x00000000 0x56221000 0x00000000 0x00001000>;
  2330. linux,phandle = <0x0000005c>;
  2331. phandle = <0x0000005c>;
  2332. };
  2333. dsi_phy@56228300 {
  2334. #address-cells = <0x00000001>;
  2335. #size-cells = <0x00000000>;
  2336. compatible = "mixel,imx8qxp-mipi-dsi-phy";
  2337. reg = <0x00000000 0x56228300 0x00000000 0x00000100>;
  2338. #phy-cells = <0x00000000>;
  2339. status = "disabled";
  2340. linux,phandle = <0x0000005a>;
  2341. phandle = <0x0000005a>;
  2342. };
  2343. mipi_dsi_bridge@56228000 {
  2344. #address-cells = <0x00000001>;
  2345. #size-cells = <0x00000000>;
  2346. compatible = "nwl,mipi-dsi";
  2347. reg = <0x00000000 0x56228000 0x00000000 0x00000300>;
  2348. interrupts = <0x00000010 0x00000004>;
  2349. interrupt-parent = <0x00000059>;
  2350. clocks = <0x00000003 0x000001f4 0x00000003 0x000001c9 0x00000003 0x000001ca>;
  2351. clock-names = "phy_ref", "tx_esc", "rx_esc";
  2352. assigned-clocks = <0x00000003 0x000001f2 0x00000003 0x000001ef 0x00000003 0x000001f0 0x00000003 0x000001c9 0x00000003 0x000001ca>;
  2353. assigned-clock-rates = <0x00000000 0x00000000 0x00000000 0x0112a880 0x044aa200>;
  2354. assigned-clock-parents = <0x00000003 0x000001ec 0x00000003 0x000001ec 0x00000003 0x000001ec>;
  2355. power-domains = <0x0000002a>;
  2356. phys = <0x0000005a>;
  2357. phy-names = "dphy";
  2358. status = "disabled";
  2359. port@0 {
  2360. endpoint {
  2361. remote-endpoint = <0x0000005b>;
  2362. linux,phandle = <0x0000005e>;
  2363. phandle = <0x0000005e>;
  2364. };
  2365. };
  2366. };
  2367. mipi_dsi@56228000 {
  2368. compatible = "fsl,imx8qxp-mipi-dsi";
  2369. clocks = <0x00000003 0x000001c1 0x00000003 0x000001bf 0x00000003 0x000001f4>;
  2370. clock-names = "pixel", "bypass", "phy_ref";
  2371. power-domains = <0x0000002a>;
  2372. csr = <0x0000005c>;
  2373. phys = <0x0000005a>;
  2374. phy-names = "dphy";
  2375. status = "disabled";
  2376. pwr-delay = <0x0000000a>;
  2377. port@0 {
  2378. endpoint {
  2379. remote-endpoint = <0x0000005d>;
  2380. linux,phandle = <0x00000050>;
  2381. phandle = <0x00000050>;
  2382. };
  2383. };
  2384. port@1 {
  2385. endpoint {
  2386. remote-endpoint = <0x0000005e>;
  2387. linux,phandle = <0x0000005b>;
  2388. phandle = <0x0000005b>;
  2389. };
  2390. };
  2391. };
  2392. lvds_region@56220000 {
  2393. compatible = "fsl,imx8qxp-lvds-region", "syscon";
  2394. reg = <0x00000000 0x56220000 0x00000000 0x00010000>;
  2395. linux,phandle = <0x00000060>;
  2396. phandle = <0x00000060>;
  2397. };
  2398. ldb_phy@56221000 {
  2399. compatible = "mixel,lvds-combo-phy";
  2400. reg = <0x00000000 0x56221000 0x00000000 0x00000100 0x00000000 0x56228000 0x00000000 0x00001000>;
  2401. #phy-cells = <0x00000000>;
  2402. clocks = <0x00000003 0x000001c6>;
  2403. clock-names = "phy";
  2404. status = "disabled";
  2405. linux,phandle = <0x00000062>;
  2406. phandle = <0x00000062>;
  2407. };
  2408. ldb@562210e0 {
  2409. #address-cells = <0x00000001>;
  2410. #size-cells = <0x00000000>;
  2411. compatible = "fsl,imx8qxp-ldb";
  2412. clocks = <0x00000003 0x000001c3 0x00000003 0x000001c4 0x00000003 0x000001dc 0x00000003 0x000001dd>;
  2413. clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass";
  2414. power-domains = <0x0000005f>;
  2415. gpr = <0x00000060>;
  2416. aux-gpr = <0x00000061>;
  2417. status = "disabled";
  2418. lvds-channel@0 {
  2419. #address-cells = <0x00000001>;
  2420. #size-cells = <0x00000000>;
  2421. reg = <0x00000000>;
  2422. phys = <0x00000062 0x00000063>;
  2423. phy-names = "ldb_phy", "aux_ldb_phy";
  2424. status = "disabled";
  2425. port@0 {
  2426. reg = <0x00000000>;
  2427. endpoint {
  2428. remote-endpoint = <0x00000064>;
  2429. linux,phandle = <0x0000004e>;
  2430. phandle = <0x0000004e>;
  2431. };
  2432. };
  2433. };
  2434. lvds-channel@1 {
  2435. #address-cells = <0x00000001>;
  2436. #size-cells = <0x00000000>;
  2437. reg = <0x00000001>;
  2438. phys = <0x00000062>;
  2439. phy-names = "ldb_phy";
  2440. status = "disabled";
  2441. port@0 {
  2442. reg = <0x00000000>;
  2443. endpoint {
  2444. remote-endpoint = <0x00000065>;
  2445. linux,phandle = <0x0000004f>;
  2446. phandle = <0x0000004f>;
  2447. };
  2448. };
  2449. };
  2450. };
  2451. pwm@56224000 {
  2452. compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
  2453. reg = <0x00000000 0x56224000 0x00000000 0x00001000>;
  2454. clocks = <0x00000003 0x0000011a 0x00000003 0x0000020e 0x00000003 0x0000011b>;
  2455. clock-names = "ipg", "per", "32k";
  2456. assigned-clocks = <0x00000003 0x0000020e>;
  2457. assigned-clock-rates = <0x016e3600>;
  2458. #pwm-cells = <0x00000002>;
  2459. power-domains = <0x00000066>;
  2460. status = "disabled";
  2461. };
  2462. i2c@56226000 {
  2463. compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
  2464. reg = <0x00000000 0x56226000 0x00000000 0x00001000>;
  2465. interrupts = <0x00000008 0x00000004>;
  2466. interrupt-parent = <0x00000059>;
  2467. clocks = <0x00000003 0x00000113 0x00000003 0x00000116>;
  2468. clock-names = "per", "ipg";
  2469. assigned-clocks = <0x00000003 0x00000111>;
  2470. assigned-clock-rates = <0x016e3600>;
  2471. power-domains = <0x00000067>;
  2472. status = "disabled";
  2473. #address-cells = <0x00000001>;
  2474. #size-cells = <0x00000000>;
  2475. pinctrl-names = "default";
  2476. pinctrl-0 = <0x00000068>;
  2477. clock-frequency = <0x000186a0>;
  2478. };
  2479. irqsteer@56240000 {
  2480. compatible = "nxp,imx-irqsteer";
  2481. reg = <0x00000000 0x56240000 0x00000000 0x00001000>;
  2482. interrupts = <0x00000000 0x0000003c 0x00000004>;
  2483. interrupt-controller;
  2484. interrupt-parent = <0x00000001>;
  2485. #interrupt-cells = <0x00000002>;
  2486. clocks = <0x00000003 0x000001e4>;
  2487. clock-names = "ipg";
  2488. power-domains = <0x0000002c>;
  2489. linux,phandle = <0x00000069>;
  2490. phandle = <0x00000069>;
  2491. };
  2492. csr@56241000 {
  2493. compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon";
  2494. reg = <0x00000000 0x56241000 0x00000000 0x00001000>;
  2495. linux,phandle = <0x0000006c>;
  2496. phandle = <0x0000006c>;
  2497. };
  2498. dsi_phy@56248300 {
  2499. #address-cells = <0x00000001>;
  2500. #size-cells = <0x00000000>;
  2501. compatible = "mixel,imx8qxp-mipi-dsi-phy";
  2502. reg = <0x00000000 0x56248300 0x00000000 0x00000100>;
  2503. #phy-cells = <0x00000000>;
  2504. status = "disabled";
  2505. linux,phandle = <0x0000006a>;
  2506. phandle = <0x0000006a>;
  2507. };
  2508. mipi_dsi_bridge@56248000 {
  2509. #address-cells = <0x00000001>;
  2510. #size-cells = <0x00000000>;
  2511. compatible = "nwl,mipi-dsi";
  2512. reg = <0x00000000 0x56248000 0x00000000 0x00000300>;
  2513. interrupts = <0x00000010 0x00000004>;
  2514. interrupt-parent = <0x00000069>;
  2515. clocks = <0x00000003 0x000001fd 0x00000003 0x000001e2 0x00000003 0x000001e3>;
  2516. clock-names = "phy_ref", "tx_esc", "rx_esc";
  2517. assigned-clocks = <0x00000003 0x000001fb 0x00000003 0x000001f9 0x00000003 0x000001fa 0x00000003 0x000001e2 0x00000003 0x000001e3>;
  2518. assigned-clock-rates = <0x00000000 0x00000000 0x00000000 0x0112a880 0x044aa200>;
  2519. assigned-clock-parents = <0x00000003 0x000001f6 0x00000003 0x000001f6 0x00000003 0x000001f6>;
  2520. power-domains = <0x0000002c>;
  2521. phys = <0x0000006a>;
  2522. phy-names = "dphy";
  2523. status = "disabled";
  2524. port@0 {
  2525. endpoint {
  2526. remote-endpoint = <0x0000006b>;
  2527. linux,phandle = <0x0000006e>;
  2528. phandle = <0x0000006e>;
  2529. };
  2530. };
  2531. };
  2532. mipi_dsi@56248000 {
  2533. compatible = "fsl,imx8qxp-mipi-dsi";
  2534. clocks = <0x00000003 0x000001da 0x00000003 0x000001d8 0x00000003 0x000001fd>;
  2535. clock-names = "pixel", "bypass", "phy_ref";
  2536. power-domains = <0x0000002c>;
  2537. csr = <0x0000006c>;
  2538. phys = <0x0000006a>;
  2539. phy-names = "dphy";
  2540. status = "disabled";
  2541. pwr-delay = <0x0000000a>;
  2542. port@0 {
  2543. endpoint {
  2544. remote-endpoint = <0x0000006d>;
  2545. linux,phandle = <0x00000053>;
  2546. phandle = <0x00000053>;
  2547. };
  2548. };
  2549. port@1 {
  2550. endpoint {
  2551. remote-endpoint = <0x0000006e>;
  2552. linux,phandle = <0x0000006b>;
  2553. phandle = <0x0000006b>;
  2554. };
  2555. };
  2556. };
  2557. lvds_region@56240000 {
  2558. compatible = "fsl,imx8qxp-lvds-region", "syscon";
  2559. reg = <0x00000000 0x56240000 0x00000000 0x00010000>;
  2560. linux,phandle = <0x00000061>;
  2561. phandle = <0x00000061>;
  2562. };
  2563. ldb_phy@56241000 {
  2564. compatible = "mixel,lvds-combo-phy";
  2565. reg = <0x00000000 0x56241000 0x00000000 0x00000100 0x00000000 0x56248000 0x00000000 0x00001000>;
  2566. #phy-cells = <0x00000000>;
  2567. clocks = <0x00000003 0x000001df>;
  2568. clock-names = "phy";
  2569. status = "disabled";
  2570. linux,phandle = <0x00000063>;
  2571. phandle = <0x00000063>;
  2572. };
  2573. ldb@562410e0 {
  2574. #address-cells = <0x00000001>;
  2575. #size-cells = <0x00000000>;
  2576. compatible = "fsl,imx8qxp-ldb";
  2577. clocks = <0x00000003 0x000001dc 0x00000003 0x000001dd 0x00000003 0x000001c3 0x00000003 0x000001c4>;
  2578. clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass";
  2579. power-domains = <0x0000006f>;
  2580. gpr = <0x00000061>;
  2581. aux-gpr = <0x00000060>;
  2582. status = "disabled";
  2583. lvds-channel@0 {
  2584. #address-cells = <0x00000001>;
  2585. #size-cells = <0x00000000>;
  2586. reg = <0x00000000>;
  2587. phys = <0x00000063 0x00000062>;
  2588. phy-names = "ldb_phy", "aux_ldb_phy";
  2589. status = "disabled";
  2590. port@0 {
  2591. reg = <0x00000000>;
  2592. endpoint {
  2593. remote-endpoint = <0x00000070>;
  2594. linux,phandle = <0x00000051>;
  2595. phandle = <0x00000051>;
  2596. };
  2597. };
  2598. };
  2599. lvds-channel@1 {
  2600. #address-cells = <0x00000001>;
  2601. #size-cells = <0x00000000>;
  2602. reg = <0x00000001>;
  2603. phys = <0x00000063>;
  2604. phy-names = "ldb_phy";
  2605. status = "disabled";
  2606. port@0 {
  2607. reg = <0x00000000>;
  2608. endpoint {
  2609. remote-endpoint = <0x00000071>;
  2610. linux,phandle = <0x00000052>;
  2611. phandle = <0x00000052>;
  2612. };
  2613. };
  2614. };
  2615. };
  2616. camera {
  2617. compatible = "fsl,mxc-md", "simple-bus";
  2618. #address-cells = <0x00000002>;
  2619. #size-cells = <0x00000002>;
  2620. ranges;
  2621. isi@58100000 {
  2622. compatible = "fsl,imx8-isi";
  2623. reg = <0x00000000 0x58100000 0x00000000 0x00010000>;
  2624. interrupts = <0x00000000 0x00000129 0x00000000>;
  2625. interface = <0x00000002 0x00000000 0x00000002>;
  2626. clocks = <0x00000003 0x00000126>;
  2627. clock-names = "per";
  2628. assigned-clocks = <0x00000003 0x00000126>;
  2629. assigned-clock-rates = "#�F";
  2630. power-domains = <0x0000002e>;
  2631. status = "okay";
  2632. };
  2633. isi@58110000 {
  2634. compatible = "fsl,imx8-isi";
  2635. reg = <0x00000000 0x58110000 0x00000000 0x00010000>;
  2636. interrupts = <0x00000000 0x0000012a 0x00000000>;
  2637. interface = <0x00000006 0x00000000 0x00000002>;
  2638. clocks = <0x00000003 0x00000127>;
  2639. clock-names = "per";
  2640. assigned-clocks = <0x00000003 0x00000127>;
  2641. assigned-clock-rates = "#�F";
  2642. power-domains = <0x00000072>;
  2643. status = "disabled";
  2644. parallel_csi;
  2645. };
  2646. isi@58120000 {
  2647. compatible = "fsl,imx8-isi";
  2648. reg = <0x00000000 0x58120000 0x00000000 0x00010000>;
  2649. interrupts = <0x00000000 0x0000012b 0x00000000>;
  2650. interface = <0x00000002 0x00000002 0x00000002>;
  2651. clocks = <0x00000003 0x00000128>;
  2652. clock-names = "per";
  2653. assigned-clocks = <0x00000003 0x00000128>;
  2654. assigned-clock-rates = "#�F";
  2655. power-domains = <0x00000073>;
  2656. status = "disabled";
  2657. };
  2658. isi@58130000 {
  2659. compatible = "fsl,imx8-isi";
  2660. reg = <0x00000000 0x58130000 0x00000000 0x00010000>;
  2661. interrupts = <0x00000000 0x0000012c 0x00000000>;
  2662. interface = <0x00000002 0x00000003 0x00000002>;
  2663. clocks = <0x00000003 0x00000129>;
  2664. clock-names = "per";
  2665. assigned-clocks = <0x00000003 0x00000129>;
  2666. assigned-clock-rates = "#�F";
  2667. power-domains = <0x00000074>;
  2668. status = "disabled";
  2669. };
  2670. isi@58140000 {
  2671. compatible = "fsl,imx8-isi";
  2672. reg = <0x00000000 0x58140000 0x00000000 0x00010000>;
  2673. interrupts = <0x00000000 0x0000012d 0x00000000>;
  2674. interface = <0x00000003 0x00000000 0x00000002>;
  2675. clocks = <0x00000003 0x0000012a>;
  2676. clock-names = "per";
  2677. assigned-clocks = <0x00000003 0x0000012a>;
  2678. assigned-clock-rates = "#�F";
  2679. power-domains = <0x00000075>;
  2680. status = "disabled";
  2681. };
  2682. isi@58150000 {
  2683. compatible = "fsl,imx8-isi";
  2684. reg = <0x00000000 0x58150000 0x00000000 0x00010000>;
  2685. interrupts = <0x00000000 0x0000012e 0x00000000>;
  2686. interface = <0x00000003 0x00000001 0x00000002>;
  2687. clocks = <0x00000003 0x0000012b>;
  2688. clock-names = "per";
  2689. assigned-clocks = <0x00000003 0x0000012b>;
  2690. assigned-clock-rates = "#�F";
  2691. power-domains = <0x00000076>;
  2692. status = "disabled";
  2693. };
  2694. isi@58160000 {
  2695. compatible = "fsl,imx8-isi";
  2696. reg = <0x00000000 0x58160000 0x00000000 0x00010000>;
  2697. interrupts = <0x00000000 0x0000012f 0x00000000>;
  2698. interface = <0x00000003 0x00000002 0x00000002>;
  2699. clocks = <0x00000003 0x0000012c>;
  2700. clock-names = "per";
  2701. assigned-clocks = <0x00000003 0x0000012c>;
  2702. assigned-clock-rates = "#�F";
  2703. power-domains = <0x00000077>;
  2704. status = "disabled";
  2705. };
  2706. isi@58170000 {
  2707. compatible = "fsl,imx8-isi";
  2708. reg = <0x00000000 0x58170000 0x00000000 0x00010000>;
  2709. interrupts = <0x00000000 0x00000130 0x00000000>;
  2710. interface = <0x00000003 0x00000003 0x00000002>;
  2711. clocks = <0x00000003 0x0000012d>;
  2712. clock-names = "per";
  2713. assigned-clocks = <0x00000003 0x0000012d>;
  2714. assigned-clock-rates = "#�F";
  2715. power-domains = <0x00000078>;
  2716. status = "disabled";
  2717. };
  2718. csi@58227000 {
  2719. compatible = "fsl,mxc-mipi-csi2";
  2720. reg = <0x00000000 0x58227000 0x00000000 0x00001000 0x00000000 0x58221000 0x00000000 0x00001000>;
  2721. interrupts = <0x0000000a 0x00000004>;
  2722. interrupt-parent = <0x00000037>;
  2723. clocks = <0x00000003 0x00000000 0x00000003 0x0000013c 0x00000003 0x0000013d 0x00000003 0x00000123>;
  2724. clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
  2725. assigned-clocks = <0x00000003 0x0000013c 0x00000003 0x0000013d>;
  2726. assigned-clock-rates = <0x15752a00 0x044aa200>;
  2727. power-domains = <0x0000002f>;
  2728. status = "okay";
  2729. #address-cells = <0x00000001>;
  2730. #size-cells = <0x00000000>;
  2731. port@0 {
  2732. reg = <0x00000000>;
  2733. endpoint {
  2734. remote-endpoint = <0x00000079>;
  2735. data-lanes = <0x00000001 0x00000002>;
  2736. linux,phandle = <0x00000081>;
  2737. phandle = <0x00000081>;
  2738. };
  2739. };
  2740. };
  2741. pcsi@58261000 {
  2742. compatible = "fsl,mxc-parallel-csi";
  2743. reg = <0x00000000 0x58261000 0x00000000 0x00001000>;
  2744. clocks = <0x00000003 0x00000208 0x00000003 0x00000209 0x00000003 0x00000206 0x00000003 0x00000207 0x00000003 0x00000205>;
  2745. clock-names = "pixel", "ipg", "sel", "div", "dpll";
  2746. assigned-clocks = <0x00000003 0x00000206 0x00000003 0x00000207>;
  2747. assigned-clock-parents = <0x00000003 0x00000205>;
  2748. assigned-clock-rates = <0x00000000 0x09896800>;
  2749. power-domains = <0x00000030>;
  2750. status = "disabled";
  2751. };
  2752. jpegdec@58400000 {
  2753. compatible = "fsl,imx8-jpgdec";
  2754. reg = <0x00000000 0x58400000 0x00000000 0x00040020>;
  2755. interrupts = <0x00000000 0x00000135 0x00000004>;
  2756. clocks = <0x00000003 0x0000011f 0x00000003 0x00000120>;
  2757. clock-names = "ipg", "per";
  2758. assigned-clocks = <0x00000003 0x0000011f 0x00000003 0x00000120>;
  2759. assigned-clock-rates = "
  2760. ��";
  2761. power-domains = <0x0000007a>;
  2762. status = "okay";
  2763. };
  2764. jpegenc@58450000 {
  2765. compatible = "fsl,imx8-jpgenc";
  2766. reg = <0x00000000 0x58450000 0x00000000 0x00240020>;
  2767. interrupts = <0x00000000 0x00000131 0x00000004>;
  2768. clocks = <0x00000003 0x0000011d 0x00000003 0x0000011e>;
  2769. clock-names = "ipg", "per";
  2770. assigned-clocks = <0x00000003 0x0000011d 0x00000003 0x0000011e>;
  2771. assigned-clock-rates = "
  2772. ��";
  2773. power-domains = <0x0000007b>;
  2774. status = "okay";
  2775. };
  2776. };
  2777. i2c-rpbus-1 {
  2778. compatible = "fsl,i2c-rpbus";
  2779. status = "disabled";
  2780. };
  2781. i2c-rpbus-5 {
  2782. compatible = "fsl,i2c-rpbus";
  2783. status = "disabled";
  2784. };
  2785. i2c-rpbus-12 {
  2786. compatible = "fsl,i2c-rpbus";
  2787. status = "disabled";
  2788. };
  2789. i2c-rpbus-13 {
  2790. compatible = "fsl,i2c-rpbus";
  2791. status = "disabled";
  2792. };
  2793. i2c-rpbus-14 {
  2794. compatible = "fsl,i2c-rpbus";
  2795. status = "disabled";
  2796. };
  2797. i2c-rpbus-15 {
  2798. compatible = "fsl,i2c-rpbus";
  2799. status = "disabled";
  2800. };
  2801. pwm@56244000 {
  2802. compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
  2803. reg = <0x00000000 0x56244000 0x00000000 0x00001000>;
  2804. clocks = <0x00000003 0x000001d5 0x00000003 0x0000020f 0x00000003 0x000001d6>;
  2805. clock-names = "ipg", "per", "32k";
  2806. assigned-clocks = <0x00000003 0x0000020f>;
  2807. assigned-clock-rates = <0x016e3600>;
  2808. #pwm-cells = <0x00000002>;
  2809. power-domains = <0x0000007c>;
  2810. status = "disabled";
  2811. };
  2812. i2c@56246000 {
  2813. compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
  2814. reg = <0x00000000 0x56246000 0x00000000 0x00001000>;
  2815. interrupts = <0x00000008 0x00000004>;
  2816. interrupt-parent = <0x00000069>;
  2817. clocks = <0x00000003 0x000001ce 0x00000003 0x000001d1>;
  2818. clock-names = "per", "ipg";
  2819. assigned-clocks = <0x00000003 0x000001cc>;
  2820. assigned-clock-rates = <0x016e3600>;
  2821. power-domains = <0x0000007d>;
  2822. status = "okay";
  2823. #address-cells = <0x00000001>;
  2824. #size-cells = <0x00000000>;
  2825. clock-frequency = <0x000186a0>;
  2826. pinctrl-names = "default";
  2827. pinctrl-0 = <0x0000007e>;
  2828. ov5640_mipi@3c {
  2829. compatible = "ovti,ov5640_mipi_v3";
  2830. clocks = <0x00000003 0x00000009>;
  2831. clock-names = "csi_mclk";
  2832. csi_id = <0x00000000>;
  2833. mclk = <0x016e3600>;
  2834. mclk_source = <0x00000000>;
  2835. mipi_csi;
  2836. pinctrl-names = "default";
  2837. pinctrl-0 = <0x0000007f>;
  2838. pwn-gpios = <0x00000080 0x0000000e 0x00000000>;
  2839. reg = <0x0000003c>;
  2840. rst-gpios = <0x00000080 0x0000000f 0x00000001>;
  2841. port {
  2842. endpoint {
  2843. remote-endpoint = <0x00000081>;
  2844. linux,phandle = <0x00000079>;
  2845. phandle = <0x00000079>;
  2846. };
  2847. };
  2848. };
  2849. };
  2850. adc@5a880000 {
  2851. compatible = "fsl,imx8qxp-adc";
  2852. #io-channel-cells = <0x00000001>;
  2853. reg = <0x00000000 0x5a880000 0x00000000 0x00010000>;
  2854. interrupts = <0x00000000 0x000000f0 0x00000004>;
  2855. interrupt-parent = <0x00000001>;
  2856. clocks = <0x00000003 0x000000a9 0x00000003 0x000000a7>;
  2857. clock-names = "per", "ipg";
  2858. assigned-clocks = <0x00000003 0x000000a9>;
  2859. assigned-clock-rates = <0x016e3600>;
  2860. power-domains = <0x00000082>;
  2861. status = "okay";
  2862. pinctrl-names = "default";
  2863. pinctrl-0 = <0x00000083>;
  2864. vref-supply = <0x00000084>;
  2865. };
  2866. i2c@5a800000 {
  2867. compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
  2868. reg = <0x00000000 0x5a800000 0x00000000 0x00004000>;
  2869. interrupts = <0x00000000 0x000000dc 0x00000004>;
  2870. interrupt-parent = <0x00000001>;
  2871. clocks = <0x00000003 0x0000009d 0x00000003 0x00000095>;
  2872. clock-names = "per", "ipg";
  2873. assigned-clocks = <0x00000003 0x00000183 0x00000003 0x000001a4 0x00000003 0x000001a8 0x00000003 0x000001ac>;
  2874. assigned-clock-rates = <0x2ee00000 0x02ee0000 0x00b71b00 0x00b71b00>;
  2875. power-domains = <0x00000085>;
  2876. status = "okay";
  2877. #address-cells = <0x00000001>;
  2878. #size-cells = <0x00000000>;
  2879. clock-frequency = <0x000186a0>;
  2880. pinctrl-names = "default";
  2881. pinctrl-0 = <0x00000086 0x00000087>;
  2882. usb3803@08 {
  2883. compatible = "smsc,usb3803";
  2884. pinctrl-names = "default";
  2885. pinctrl-0 = <0x00000088>;
  2886. reg = <0x00000008>;
  2887. clocks = <0x00000003 0x000001ac>;
  2888. clock-names = "refclk";
  2889. power-domains = <0x00000089>;
  2890. bypass-gpios = <0x0000008a 0x00000005 0x00000001>;
  2891. intn-gpios = <0x00000080 0x00000004 0x00000001>;
  2892. reset-gpios = <0x0000008a 0x00000004 0x00000001>;
  2893. disabled-ports = <0x00000002>;
  2894. initial-mode = <0x00000001>;
  2895. non-removable-devices = <0x00000001>;
  2896. };
  2897. codec@a {
  2898. compatible = "fsl,sgtl5000";
  2899. #sound-dai-cells = <0x00000000>;
  2900. pinctrl-names = "default";
  2901. pinctrl-0 = <0x0000008b>;
  2902. reg = <0x0000000a>;
  2903. clocks = <0x00000003 0x000001ac>;
  2904. power-domains = <0x00000089>;
  2905. VDDA-supply = <0x0000008c>;
  2906. VDDIO-supply = <0x0000008d>;
  2907. VDDD-supply = <0x00000084>;
  2908. linux,phandle = <0x00000130>;
  2909. phandle = <0x00000130>;
  2910. };
  2911. gpio-expander@43 {
  2912. compatible = "fcs,fxl6408";
  2913. gpio-controller;
  2914. #gpio-cells = <0x00000002>;
  2915. reg = <0x00000043>;
  2916. inital_io_dir = <0x000000ff>;
  2917. inital_output = <0x00000005>;
  2918. linux,phandle = <0x0000008a>;
  2919. phandle = <0x0000008a>;
  2920. };
  2921. ad7879@2c {
  2922. compatible = "adi,ad7879-1";
  2923. pinctrl-names = "default";
  2924. pinctrl-0 = <0x0000008e>;
  2925. reg = <0x0000002c>;
  2926. interrupt-parent = <0x00000080>;
  2927. interrupts = <0x00000005 0x00000002>;
  2928. touchscreen-max-pressure = <0x00001000>;
  2929. adi,resistance-plate-x = <0x00000078>;
  2930. adi,first-conversion-delay = [03];
  2931. adi,acquisition-time = [01];
  2932. adi,median-filter-size = [02];
  2933. adi,averaging = [01];
  2934. adi,conversion-interval = [ff];
  2935. };
  2936. };
  2937. i2c@5a810000 {
  2938. compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
  2939. reg = <0x00000000 0x5a810000 0x00000000 0x00004000>;
  2940. interrupts = <0x00000000 0x000000dd 0x00000004>;
  2941. interrupt-parent = <0x00000001>;
  2942. clocks = <0x00000003 0x0000009e 0x00000003 0x00000096>;
  2943. clock-names = "per", "ipg";
  2944. assigned-clocks = <0x00000003 0x0000009e>;
  2945. assigned-clock-rates = <0x016e3600>;
  2946. power-domains = <0x0000008f>;
  2947. status = "okay";
  2948. #address-cells = <0x00000001>;
  2949. #size-cells = <0x00000000>;
  2950. clock-frequency = <0x000186a0>;
  2951. pinctrl-names = "default";
  2952. pinctrl-0 = <0x00000090>;
  2953. atmel_mxt_ts@4a {
  2954. compatible = "atmel,maxtouch";
  2955. pinctrl-names = "default";
  2956. pinctrl-0 = <0x0000000f>;
  2957. reg = <0x0000004a>;
  2958. interrupt-parent = <0x00000080>;
  2959. interrupts = <0x00000014 0x00000002>;
  2960. reset-gpios = <0x00000080 0x00000018 0x00000000>;
  2961. status = "disabled";
  2962. };
  2963. rtc@68 {
  2964. compatible = "st,m41t0";
  2965. reg = <0x00000068>;
  2966. };
  2967. };
  2968. i2c@5a820000 {
  2969. compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
  2970. reg = <0x00000000 0x5a820000 0x00000000 0x00004000>;
  2971. interrupts = <0x00000000 0x000000de 0x00000004>;
  2972. interrupt-parent = <0x00000001>;
  2973. clocks = <0x00000003 0x0000009f 0x00000003 0x00000097>;
  2974. clock-names = "per", "ipg";
  2975. assigned-clocks = <0x00000003 0x0000009f>;
  2976. assigned-clock-rates = <0x016e3600>;
  2977. power-domains = <0x00000091>;
  2978. status = "disabled";
  2979. };
  2980. i2c@5a830000 {
  2981. compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
  2982. reg = <0x00000000 0x5a830000 0x00000000 0x00004000>;
  2983. interrupts = <0x00000000 0x000000df 0x00000004>;
  2984. interrupt-parent = <0x00000001>;
  2985. clocks = <0x00000003 0x000000a0 0x00000003 0x00000098>;
  2986. clock-names = "per", "ipg";
  2987. assigned-clocks = <0x00000003 0x000000a0>;
  2988. assigned-clock-rates = <0x016e3600>;
  2989. power-domains = <0x00000092>;
  2990. status = "disabled";
  2991. };
  2992. usbmisc@5b0d0200 {
  2993. #index-cells = <0x00000001>;
  2994. compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
  2995. reg = <0x00000000 0x5b0d0200 0x00000000 0x00000200>;
  2996. linux,phandle = <0x00000095>;
  2997. phandle = <0x00000095>;
  2998. };
  2999. usbphy@0x5b100000 {
  3000. compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
  3001. reg = <0x00000000 0x5b100000 0x00000000 0x00001000>;
  3002. clocks = <0x00000003 0x000000ef>;
  3003. power-domains = <0x00000093>;
  3004. linux,phandle = <0x00000094>;
  3005. phandle = <0x00000094>;
  3006. };
  3007. usb@5b0d0000 {
  3008. compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
  3009. reg = <0x00000000 0x5b0d0000 0x00000000 0x00000200>;
  3010. interrupt-parent = <0x00000001>;
  3011. interrupts = <0x00000000 0x0000010b 0x00000004>;
  3012. fsl,usbphy = <0x00000094>;
  3013. fsl,usbmisc = <0x00000095 0x00000000>;
  3014. clocks = <0x00000003 0x000000ec>;
  3015. ahb-burst-config = <0x00000000>;
  3016. tx-burst-size-dword = <0x00000010>;
  3017. rx-burst-size-dword = <0x00000010>;
  3018. #stream-id-cells = <0x00000001>;
  3019. power-domains = <0x00000013>;
  3020. status = "okay";
  3021. extcon = <0x00000096 0x00000096>;
  3022. vbus-supply = <0x00000097>;
  3023. srp-disable;
  3024. hnp-disable;
  3025. adp-disable;
  3026. power-polarity-active-high;
  3027. disable-over-current;
  3028. };
  3029. can@5a8d0000 {
  3030. compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
  3031. reg = <0x00000000 0x5a8d0000 0x00000000 0x00010000>;
  3032. interrupts = <0x00000000 0x000000eb 0x00000004>;
  3033. interrupt-parent = <0x00000001>;
  3034. clocks = <0x00000003 0x0000008c 0x00000003 0x00000092>;
  3035. clock-names = "ipg", "per";
  3036. assigned-clocks = <0x00000003 0x00000092>;
  3037. assigned-clock-rates = <0x02625a00>;
  3038. power-domains = <0x0000001f>;
  3039. clk-src = <0x00000000>;
  3040. status = "disabled";
  3041. pinctrl-names = "default";
  3042. pinctrl-0 = <0x00000098>;
  3043. xceiver-supply = <0x0000008d>;
  3044. };
  3045. can@5a8e0000 {
  3046. compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
  3047. reg = <0x00000000 0x5a8e0000 0x00000000 0x00010000>;
  3048. interrupts = <0x00000000 0x000000ec 0x00000004>;
  3049. interrupt-parent = <0x00000001>;
  3050. clocks = <0x00000003 0x0000008c 0x00000003 0x00000092>;
  3051. clock-names = "ipg", "per";
  3052. assigned-clocks = <0x00000003 0x00000092>;
  3053. assigned-clock-rates = <0x02625a00>;
  3054. power-domains = <0x00000099>;
  3055. clk-src = <0x00000000>;
  3056. status = "disabled";
  3057. pinctrl-names = "default";
  3058. pinctrl-0 = <0x0000009a>;
  3059. xceiver-supply = <0x0000008d>;
  3060. };
  3061. can@5a8f0000 {
  3062. compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
  3063. reg = <0x00000000 0x5a8f0000 0x00000000 0x00010000>;
  3064. interrupts = <0x00000000 0x000000ed 0x00000004>;
  3065. interrupt-parent = <0x00000001>;
  3066. clocks = <0x00000003 0x0000008c 0x00000003 0x00000092>;
  3067. clock-names = "ipg", "per";
  3068. assigned-clocks = <0x00000003 0x00000092>;
  3069. assigned-clock-rates = <0x02625a00>;
  3070. power-domains = <0x0000009b>;
  3071. clk-src = <0x00000000>;
  3072. status = "disabled";
  3073. pinctrl-names = "default";
  3074. pinctrl-0 = <0x0000009c>;
  3075. xceiver-supply = <0x0000008d>;
  3076. };
  3077. dma-apbh@5b810000 {
  3078. compatible = "fsl,imx28-dma-apbh";
  3079. reg = <0x00000000 0x5b810000 0x00000000 0x00002000>;
  3080. interrupts = <0x00000000 0x00000112 0x00000004 0x00000000 0x00000112 0x00000004 0x00000000 0x00000112 0x00000004 0x00000000 0x00000112 0x00000004>;
  3081. interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  3082. #dma-cells = <0x00000001>;
  3083. dma-channels = <0x00000004>;
  3084. clocks = <0x00000003 0x000000e2>;
  3085. power-domains = <0x0000009d>;
  3086. linux,phandle = <0x0000009e>;
  3087. phandle = <0x0000009e>;
  3088. };
  3089. gpmi-nand@5b812000 {
  3090. compatible = "fsl,imx8qxp-gpmi-nand";
  3091. #address-cells = <0x00000001>;
  3092. #size-cells = <0x00000001>;
  3093. reg = <0x00000000 0x5b812000 0x00000000 0x00002000 0x00000000 0x5b814000 0x00000000 0x00002000>;
  3094. reg-names = "gpmi-nand", "bch";
  3095. interrupts = <0x00000000 0x00000110 0x00000004>;
  3096. interrupt-names = "bch";
  3097. clocks = <0x00000003 0x000000e0 0x00000003 0x000000de 0x00000003 0x000000e1 0x00000003 0x000000df>;
  3098. clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch";
  3099. dmas = <0x0000009e 0x00000000>;
  3100. dma-names = "rx-tx";
  3101. power-domains = <0x0000009d>;
  3102. assigned-clocks = <0x00000003 0x000000e0>;
  3103. assigned-clock-rates = <0x02faf080>;
  3104. status = "disabled";
  3105. };
  3106. usbphynop1 {
  3107. compatible = "usb-nop-xceiv";
  3108. clocks = <0x00000003 0x000000e8>;
  3109. clock-names = "main_clk";
  3110. power-domains = <0x0000009f>;
  3111. linux,phandle = <0x000000a0>;
  3112. phandle = <0x000000a0>;
  3113. };
  3114. usb3@5b110000 {
  3115. compatible = "Cadence,usb3";
  3116. reg = * 0x000000009300d864 [0x00000050];
  3117. interrupt-parent = <0x00000001>;
  3118. interrupts = <0x00000000 0x0000010f 0x00000004>;
  3119. clocks = <0x00000003 0x000000eb 0x00000003 0x000000ea 0x00000003 0x000000e9 0x00000003 0x000000e6 0x00000003 0x000000e7>;
  3120. clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", "usb3_ipg_clk", "usb3_core_pclk";
  3121. power-domains = <0x00000014>;
  3122. cdns3,usbphy = <0x000000a0>;
  3123. status = "okay";
  3124. dr_mode = "host";
  3125. };
  3126. gpio@5d080000 {
  3127. compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
  3128. reg = <0x00000000 0x5d080000 0x00000000 0x00010000>;
  3129. interrupts = <0x00000000 0x00000088 0x00000004>;
  3130. gpio-controller;
  3131. #gpio-cells = <0x00000002>;
  3132. power-domains = <0x000000a1>;
  3133. interrupt-controller;
  3134. #interrupt-cells = <0x00000002>;
  3135. status = "okay";
  3136. };
  3137. gpio@5d090000 {
  3138. compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
  3139. reg = <0x00000000 0x5d090000 0x00000000 0x00010000>;
  3140. interrupts = <0x00000000 0x00000089 0x00000004>;
  3141. gpio-controller;
  3142. #gpio-cells = <0x00000002>;
  3143. power-domains = <0x000000a2>;
  3144. interrupt-controller;
  3145. #interrupt-cells = <0x00000002>;
  3146. status = "okay";
  3147. linux,phandle = <0x000000ba>;
  3148. phandle = <0x000000ba>;
  3149. };
  3150. gpio@5d0a0000 {
  3151. compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
  3152. reg = <0x00000000 0x5d0a0000 0x00000000 0x00010000>;
  3153. interrupts = <0x00000000 0x0000008a 0x00000004>;
  3154. gpio-controller;
  3155. #gpio-cells = <0x00000002>;
  3156. power-domains = <0x000000a3>;
  3157. interrupt-controller;
  3158. #interrupt-cells = <0x00000002>;
  3159. };
  3160. gpio@5d0b0000 {
  3161. compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
  3162. reg = <0x00000000 0x5d0b0000 0x00000000 0x00010000>;
  3163. interrupts = <0x00000000 0x0000008b 0x00000004>;
  3164. gpio-controller;
  3165. #gpio-cells = <0x00000002>;
  3166. power-domains = <0x000000a4>;
  3167. interrupt-controller;
  3168. #interrupt-cells = <0x00000002>;
  3169. status = "okay";
  3170. pad-wakeup = <0x0000009d 0x00000006 0x0000000a>;
  3171. pad-wakeup-num = <0x00000001>;
  3172. linux,phandle = <0x00000080>;
  3173. phandle = <0x00000080>;
  3174. };
  3175. gpio@5d0c0000 {
  3176. compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
  3177. reg = <0x00000000 0x5d0c0000 0x00000000 0x00010000>;
  3178. interrupts = <0x00000000 0x0000008c 0x00000004>;
  3179. gpio-controller;
  3180. #gpio-cells = <0x00000002>;
  3181. power-domains = <0x000000a5>;
  3182. interrupt-controller;
  3183. #interrupt-cells = <0x00000002>;
  3184. status = "okay";
  3185. linux,phandle = <0x0000011c>;
  3186. phandle = <0x0000011c>;
  3187. };
  3188. gpio@5d0d0000 {
  3189. compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
  3190. reg = <0x00000000 0x5d0d0000 0x00000000 0x00010000>;
  3191. interrupts = <0x00000000 0x0000008d 0x00000004>;
  3192. gpio-controller;
  3193. #gpio-cells = <0x00000002>;
  3194. power-domains = <0x000000a6>;
  3195. interrupt-controller;
  3196. #interrupt-cells = <0x00000002>;
  3197. linux,phandle = <0x00000131>;
  3198. phandle = <0x00000131>;
  3199. };
  3200. gpio@5d0e0000 {
  3201. compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
  3202. reg = <0x00000000 0x5d0e0000 0x00000000 0x00010000>;
  3203. interrupts = <0x00000000 0x0000008e 0x00000004>;
  3204. gpio-controller;
  3205. #gpio-cells = <0x00000002>;
  3206. power-domains = <0x000000a7>;
  3207. interrupt-controller;
  3208. #interrupt-cells = <0x00000002>;
  3209. };
  3210. gpio@5d0f0000 {
  3211. compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
  3212. reg = <0x00000000 0x5d0f0000 0x00000000 0x00010000>;
  3213. interrupts = <0x00000000 0x0000008f 0x00000004>;
  3214. gpio-controller;
  3215. #gpio-cells = <0x00000002>;
  3216. power-domains = <0x000000a8>;
  3217. interrupt-controller;
  3218. #interrupt-cells = <0x00000002>;
  3219. };
  3220. gpio@58222000 {
  3221. compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
  3222. reg = <0x00000000 0x58222000 0x00000000 0x00001000>;
  3223. interrupts = <0x00000000 0x00000004>;
  3224. interrupt-parent = <0x00000037>;
  3225. gpio-controller;
  3226. #gpio-cells = <0x00000002>;
  3227. interrupt-controller;
  3228. #interrupt-cells = <0x00000002>;
  3229. power-domains = <0x0000002f>;
  3230. };
  3231. pwm@5d000000 {
  3232. compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
  3233. reg = <0x00000000 0x5d000000 0x00000000 0x00010000>;
  3234. clocks = <0x00000003 0x00000011 0x00000003 0x00000012>;
  3235. clock-names = "ipg", "per";
  3236. assigned-clocks = <0x00000003 0x00000012 0x00000003 0x00000013>;
  3237. assigned-clock-rates = <0x016e3600 0x016e3600>;
  3238. #pwm-cells = <0x00000003>;
  3239. power-domains = <0x000000a9>;
  3240. status = "okay";
  3241. pinctrl-names = "default";
  3242. pinctrl-0 = <0x000000aa>;
  3243. };
  3244. pwm@5d010000 {
  3245. compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
  3246. reg = <0x00000000 0x5d010000 0x00000000 0x00010000>;
  3247. clocks = <0x00000003 0x00000017 0x00000003 0x00000018>;
  3248. clock-names = "ipg", "per";
  3249. assigned-clocks = <0x00000003 0x00000018 0x00000003 0x00000019>;
  3250. assigned-clock-rates = <0x016e3600 0x016e3600>;
  3251. #pwm-cells = <0x00000003>;
  3252. power-domains = <0x000000ab>;
  3253. status = "okay";
  3254. pinctrl-names = "default";
  3255. pinctrl-0 = <0x000000ac>;
  3256. };
  3257. pwm@5d020000 {
  3258. compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
  3259. reg = <0x00000000 0x5d020000 0x00000000 0x00010000>;
  3260. clocks = <0x00000003 0x0000001d 0x00000003 0x0000001e>;
  3261. clock-names = "ipg", "per";
  3262. assigned-clocks = <0x00000003 0x0000001e 0x00000003 0x0000001f>;
  3263. assigned-clock-rates = <0x016e3600 0x016e3600>;
  3264. #pwm-cells = <0x00000003>;
  3265. power-domains = <0x000000ad>;
  3266. status = "okay";
  3267. pinctrl-names = "default";
  3268. pinctrl-0 = <0x000000ae>;
  3269. };
  3270. pwm@5d030000 {
  3271. compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
  3272. reg = <0x00000000 0x5d030000 0x00000000 0x00010000>;
  3273. clocks = <0x00000003 0x00000023 0x00000003 0x00000024>;
  3274. clock-names = "ipg", "per";
  3275. assigned-clocks = <0x00000003 0x00000024 0x00000003 0x00000025>;
  3276. assigned-clock-rates = <0x016e3600 0x016e3600>;
  3277. #pwm-cells = <0x00000002>;
  3278. power-domains = <0x000000af>;
  3279. status = "disabled";
  3280. };
  3281. pwm@5d040000 {
  3282. compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
  3283. reg = <0x00000000 0x5d040000 0x00000000 0x00010000>;
  3284. clocks = <0x00000003 0x0000002a 0x00000003 0x0000002b>;
  3285. clock-names = "ipg", "per";
  3286. assigned-clocks = <0x00000003 0x0000002b 0x00000003 0x0000002c>;
  3287. assigned-clock-rates = <0x016e3600 0x016e3600>;
  3288. #pwm-cells = <0x00000002>;
  3289. power-domains = <0x000000b0>;
  3290. status = "disabled";
  3291. };
  3292. pwm@5d050000 {
  3293. compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
  3294. reg = <0x00000000 0x5d050000 0x00000000 0x00010000>;
  3295. clocks = <0x00000003 0x00000030 0x00000003 0x00000031>;
  3296. clock-names = "ipg", "per";
  3297. assigned-clocks = <0x00000003 0x00000031 0x00000003 0x00000032>;
  3298. assigned-clock-rates = <0x016e3600 0x016e3600>;
  3299. #pwm-cells = <0x00000002>;
  3300. power-domains = <0x000000b1>;
  3301. status = "disabled";
  3302. };
  3303. pwm@5d060000 {
  3304. compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
  3305. reg = <0x00000000 0x5d060000 0x00000000 0x00010000>;
  3306. clocks = <0x00000003 0x00000036 0x00000003 0x00000037>;
  3307. clock-names = "ipg", "per";
  3308. assigned-clocks = <0x00000003 0x00000037 0x00000003 0x00000038>;
  3309. assigned-clock-rates = <0x016e3600 0x016e3600>;
  3310. #pwm-cells = <0x00000002>;
  3311. power-domains = <0x000000b2>;
  3312. status = "disabled";
  3313. };
  3314. pwm@5d070000 {
  3315. compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
  3316. reg = <0x00000000 0x5d070000 0x00000000 0x00010000>;
  3317. clocks = <0x00000003 0x0000003c 0x00000003 0x0000003d>;
  3318. clock-names = "ipg", "per";
  3319. assigned-clocks = <0x00000003 0x0000003d 0x00000003 0x0000003e>;
  3320. assigned-clock-rates = <0x016e3600 0x016e3600>;
  3321. #pwm-cells = <0x00000002>;
  3322. power-domains = <0x000000b3>;
  3323. status = "disabled";
  3324. };
  3325. gpu@53100000 {
  3326. compatible = "fsl,imx8-gpu";
  3327. reg = <0x00000000 0x53100000 0x00000000 0x00040000>;
  3328. interrupts = <0x00000000 0x00000040 0x00000004>;
  3329. clocks = <0x00000003 0x00000006 0x00000003 0x00000008>;
  3330. clock-names = "core", "shader";
  3331. assigned-clocks = <0x00000003 0x00000006 0x00000003 0x00000008>;
  3332. assigned-clock-rates = <0x29b92700 0x32a9f880>;
  3333. power-domains = <0x000000b4>;
  3334. status = "okay";
  3335. linux,phandle = <0x000000b5>;
  3336. phandle = <0x000000b5>;
  3337. };
  3338. imx8_gpu_ss {
  3339. compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss";
  3340. cores = <0x000000b5>;
  3341. reg = <0x00000000 0x80000000 0x00000000 0x80000000 0x00000000 0x00000000 0x00000000 0x10000000>;
  3342. reg-names = "phys_baseaddr", "contiguous_mem";
  3343. status = "okay";
  3344. };
  3345. ddr_pmu@5c020000 {
  3346. compatible = "fsl,imx8-ddr-pmu";
  3347. reg = <0x00000000 0x5c020000 0x00000000 0x00010000>;
  3348. interrupt-parent = <0x00000001>;
  3349. interrupts = <0x00000000 0x00000083 0x00000004>;
  3350. };
  3351. lpspi@5a000000 {
  3352. compatible = "fsl,imx7ulp-spi";
  3353. reg = <0x00000000 0x5a000000 0x00000000 0x00010000>;
  3354. interrupts = <0x00000000 0x000000d8 0x00000004>;
  3355. interrupt-parent = <0x00000001>;
  3356. clocks = <0x00000003 0x00000085 0x00000003 0x0000007d>;
  3357. clock-names = "per", "ipg";
  3358. assigned-clocks = <0x00000003 0x00000085>;
  3359. assigned-clock-rates = <0x01312d00>;
  3360. power-domains = <0x000000b6>;
  3361. dma-names = "tx", "rx";
  3362. dmas = <0x000000b7 0x00000001 0x00000000 0x00000000 0x000000b7 0x00000000 0x00000000 0x00000001>;
  3363. status = "disabled";
  3364. };
  3365. lpspi@5a020000 {
  3366. compatible = "fsl,imx7ulp-spi";
  3367. reg = <0x00000000 0x5a020000 0x00000000 0x00010000>;
  3368. interrupts = <0x00000000 0x000000da 0x00000004>;
  3369. interrupt-parent = <0x00000001>;
  3370. clocks = <0x00000003 0x00000087 0x00000003 0x0000007f>;
  3371. clock-names = "per", "ipg";
  3372. assigned-clocks = <0x00000003 0x00000087>;
  3373. assigned-clock-rates = <0x01312d00>;
  3374. power-domains = <0x000000b8>;
  3375. dma-names = "tx", "rx";
  3376. dmas = <0x000000b7 0x00000005 0x00000000 0x00000000 0x000000b7 0x00000004 0x00000000 0x00000001>;
  3377. status = "okay";
  3378. #address-cells = <0x00000001>;
  3379. #size-cells = <0x00000000>;
  3380. fsl,spi-num-chipselects = <0x00000001>;
  3381. pinctrl-names = "default";
  3382. pinctrl-0 = <0x000000b9>;
  3383. cs-gpios = <0x000000ba 0x00000000 0x00000001>;
  3384. can@0 {
  3385. compatible = "microchip,mcp2515";
  3386. pinctrl-names = "default";
  3387. pinctrl-0 = <0x000000bb>;
  3388. reg = <0x00000000>;
  3389. clocks = <0x000000bc>;
  3390. interrupt-parent = <0x00000080>;
  3391. interrupts = <0x0000000d 0x00000002>;
  3392. spi-max-frequency = <0x00989680>;
  3393. vdd-supply = <0x000000bd>;
  3394. xceiver-supply = <0x000000be>;
  3395. status = "okay";
  3396. };
  3397. spidev@0 {
  3398. compatible = "toradex,evalspi";
  3399. reg = <0x00000000>;
  3400. spi-max-frequency = <0x00989680>;
  3401. status = "disabled";
  3402. };
  3403. };
  3404. serial@5a060000 {
  3405. compatible = "fsl,imx8qm-lpuart";
  3406. reg = <0x00000000 0x5a060000 0x00000000 0x00001000>;
  3407. interrupts = <0x00000000 0x00000159 0x00000004>;
  3408. interrupt-parent = <0x00000001>;
  3409. clocks = <0x00000003 0x00000003 0x00000003 0x00000001>;
  3410. clock-names = "per", "ipg";
  3411. assigned-clocks = <0x00000003 0x00000003>;
  3412. assigned-clock-rates = <0x04c4b400>;
  3413. power-domains = <0x000000bf>;
  3414. status = "okay";
  3415. pinctrl-names = "default";
  3416. pinctrl-0 = <0x000000c0>;
  3417. };
  3418. serial@5a070000 {
  3419. compatible = "fsl,imx8qm-lpuart";
  3420. reg = <0x00000000 0x5a070000 0x00000000 0x00001000>;
  3421. interrupts = <0x00000000 0x0000015a 0x00000004>;
  3422. interrupt-parent = <0x00000001>;
  3423. clocks = <0x00000003 0x0000007a 0x00000003 0x00000074>;
  3424. clock-names = "per", "ipg";
  3425. assigned-clocks = <0x00000003 0x0000007a>;
  3426. assigned-clock-rates = <0x04c4b400>;
  3427. power-domains = <0x000000c1>;
  3428. dma-names = "tx", "rx";
  3429. dmas = <0x000000b7 0x0000000b 0x00000000 0x00000000 0x000000b7 0x0000000a 0x00000000 0x00000001>;
  3430. status = "disabled";
  3431. };
  3432. serial@5a080000 {
  3433. compatible = "fsl,imx8qm-lpuart";
  3434. reg = <0x00000000 0x5a080000 0x00000000 0x00001000>;
  3435. interrupts = <0x00000000 0x0000015b 0x00000004>;
  3436. interrupt-parent = <0x00000001>;
  3437. clocks = <0x00000003 0x0000007b 0x00000003 0x00000075>;
  3438. clock-names = "per", "ipg";
  3439. assigned-clocks = <0x00000003 0x0000007b>;
  3440. assigned-clock-rates = <0x04c4b400>;
  3441. power-domains = <0x000000c2>;
  3442. dma-names = "tx", "rx";
  3443. dmas = <0x000000b7 0x0000000d 0x00000000 0x00000000 0x000000b7 0x0000000c 0x00000000 0x00000001>;
  3444. status = "okay";
  3445. pinctrl-names = "default";
  3446. pinctrl-0 = <0x000000c3>;
  3447. };
  3448. serial@5a090000 {
  3449. compatible = "fsl,imx8qm-lpuart";
  3450. reg = <0x00000000 0x5a090000 0x00000000 0x00001000>;
  3451. interrupts = <0x00000000 0x0000015c 0x00000004>;
  3452. interrupt-parent = <0x00000001>;
  3453. clocks = <0x00000003 0x0000007c 0x00000003 0x00000076>;
  3454. clock-names = "per", "ipg";
  3455. assigned-clocks = <0x00000003 0x0000007c>;
  3456. assigned-clock-rates = <0x04c4b400>;
  3457. power-domains = <0x000000c4>;
  3458. dma-names = "tx", "rx";
  3459. dmas = <0x000000b7 0x0000000f 0x00000000 0x00000000 0x000000b7 0x0000000e 0x00000000 0x00000001>;
  3460. status = "okay";
  3461. pinctrl-names = "default";
  3462. pinctrl-0 = <0x000000c5 0x000000c6>;
  3463. };
  3464. dma-controller@5a1f0000 {
  3465. compatible = "fsl,imx8qm-edma";
  3466. reg = * 0x000000009300f534 [0x00000100];
  3467. #dma-cells = <0x00000003>;
  3468. dma-channels = <0x00000010>;
  3469. interrupts = * 0x000000009300f660 [0x000000c0];
  3470. interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx", "edma2-chan2-rx", "edma2-chan3-tx", "edma2-chan4-rx", "edma2-chan5-tx", "edma2-chan6-rx", "edma2-chan7-tx", "edma2-chan8-rx", "edma2-chan9-tx", "edma2-chan10-rx", "edma2-chan11-tx", "edma2-chan12-rx", "edma2-chan13-tx", "edma2-chan14-rx", "edma2-chan15-tx";
  3471. pdomains = <0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6>;
  3472. status = "okay";
  3473. linux,phandle = <0x000000b7>;
  3474. phandle = <0x000000b7>;
  3475. };
  3476. dma-controller@591F0000 {
  3477. compatible = "fsl,imx8qm-edma";
  3478. reg = * 0x000000009300f8ec [0x00000100];
  3479. #dma-cells = <0x00000003>;
  3480. shared-interrupt;
  3481. dma-channels = <0x00000010>;
  3482. interrupts = * 0x000000009300fa24 [0x000000c0];
  3483. interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", "edma0-chan2-rx", "edma0-chan3-tx", "edma0-chan4-tx", "edma0-chan5-tx", "edma0-chan6-rx", "edma0-chan7-tx", "edma0-chan8-rx", "edma0-chan9-tx", "edma0-chan12-rx", "edma0-chan13-tx", "edma0-chan14-rx", "edma0-chan15-tx", "edma0-chan16-rx", "edma0-chan17-rx";
  3484. pdomains = <0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6>;
  3485. status = "okay";
  3486. linux,phandle = <0x000000f0>;
  3487. phandle = <0x000000f0>;
  3488. };
  3489. dma-controller@599F0000 {
  3490. compatible = "fsl,imx8qm-edma";
  3491. reg = * 0x000000009300fcb0 [0x00000090];
  3492. #dma-cells = <0x00000003>;
  3493. shared-interrupt;
  3494. dma-channels = <0x00000009>;
  3495. interrupts = * 0x000000009300fd78 [0x0000006c];
  3496. interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", "edma1-chan2-rx", "edma1-chan3-tx", "edma1-chan4-tx", "edma1-chan5-tx", "edma1-chan8-rx", "edma1-chan9-tx", "edma1-chan10-tx";
  3497. pdomains = <0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef>;
  3498. status = "okay";
  3499. linux,phandle = <0x000000f6>;
  3500. phandle = <0x000000f6>;
  3501. };
  3502. acm@59e00000 {
  3503. compatible = "nxp,imx8qm-acm";
  3504. reg = <0x00000000 0x59e00000 0x00000000 0x001d0000>;
  3505. status = "disabled";
  3506. };
  3507. sai@59040000 {
  3508. compatible = "fsl,imx8qm-sai";
  3509. reg = <0x00000000 0x59040000 0x00000000 0x00010000>;
  3510. interrupts = <0x00000000 0x0000013a 0x00000004>;
  3511. clocks = <0x00000003 0x0000018a 0x00000003 0x00000000 0x00000003 0x0000018b 0x00000003 0x00000000 0x00000003 0x00000000>;
  3512. clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  3513. dma-names = "rx", "tx";
  3514. dmas = <0x000000f0 0x0000000c 0x00000000 0x00000001 0x000000f0 0x0000000d 0x00000000 0x00000000>;
  3515. status = "okay";
  3516. power-domains = <0x000000f1>;
  3517. #sound-dai-cells = <0x00000000>;
  3518. pinctrl-names = "default";
  3519. pinctrl-0 = <0x000000f2>;
  3520. linux,phandle = <0x0000012f>;
  3521. phandle = <0x0000012f>;
  3522. };
  3523. sai@59050000 {
  3524. compatible = "fsl,imx8qm-sai";
  3525. reg = <0x00000000 0x59050000 0x00000000 0x00010000>;
  3526. interrupts = <0x00000000 0x0000013c 0x00000004>;
  3527. clocks = <0x00000003 0x0000018c 0x00000003 0x00000000 0x00000003 0x0000018d 0x00000003 0x00000000 0x00000003 0x00000000>;
  3528. clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  3529. dma-names = "rx", "tx";
  3530. dmas = <0x000000f0 0x0000000e 0x00000000 0x00000001 0x000000f0 0x0000000f 0x00000000 0x00000000>;
  3531. status = "disabled";
  3532. power-domains = <0x000000f3>;
  3533. };
  3534. sai@59060000 {
  3535. compatible = "fsl,imx8qm-sai";
  3536. reg = <0x00000000 0x59060000 0x00000000 0x00010000>;
  3537. interrupts = <0x00000000 0x0000013e 0x00000004>;
  3538. clocks = <0x00000003 0x0000018e 0x00000003 0x00000000 0x00000003 0x0000018f 0x00000003 0x00000000 0x00000003 0x00000000>;
  3539. clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  3540. dma-names = "rx";
  3541. dmas = <0x000000f0 0x00000010 0x00000000 0x00000001>;
  3542. status = "disabled";
  3543. power-domains = <0x000000f4>;
  3544. };
  3545. sai@59070000 {
  3546. compatible = "fsl,imx8qm-sai";
  3547. reg = <0x00000000 0x59070000 0x00000000 0x00010000>;
  3548. interrupts = <0x00000000 0x00000143 0x00000004>;
  3549. clocks = <0x00000003 0x00000190 0x00000003 0x00000000 0x00000003 0x00000191 0x00000003 0x00000000 0x00000003 0x00000000>;
  3550. clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  3551. dma-names = "rx";
  3552. dmas = <0x000000f0 0x00000011 0x00000000 0x00000001>;
  3553. status = "disabled";
  3554. power-domains = <0x000000f5>;
  3555. };
  3556. sai@59820000 {
  3557. compatible = "fsl,imx8qm-sai";
  3558. reg = <0x00000000 0x59820000 0x00000000 0x00010000>;
  3559. interrupts = <0x00000000 0x00000149 0x00000004>;
  3560. clocks = <0x00000003 0x00000192 0x00000003 0x00000000 0x00000003 0x00000193 0x00000003 0x00000000 0x00000003 0x00000000>;
  3561. dmas = <0x000000f6 0x00000008 0x00000000 0x00000001 0x000000f6 0x00000009 0x00000000 0x00000000>;
  3562. clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  3563. dma-names = "rx", "tx";
  3564. status = "disabled";
  3565. power-domains = <0x000000f7>;
  3566. };
  3567. sai@59830000 {
  3568. compatible = "fsl,imx8qm-sai";
  3569. reg = <0x00000000 0x59830000 0x00000000 0x00010000>;
  3570. interrupts = <0x00000000 0x0000014b 0x00000004>;
  3571. clocks = <0x00000003 0x00000194 0x00000003 0x00000000 0x00000003 0x00000195 0x00000003 0x00000000 0x00000003 0x00000000>;
  3572. clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  3573. dma-names = "tx";
  3574. dmas = <0x000000f6 0x0000000a 0x00000000 0x00000000>;
  3575. status = "disabled";
  3576. power-domains = <0x000000f8>;
  3577. };
  3578. amix@59840000 {
  3579. compatible = "fsl,imx8qm-amix";
  3580. reg = <0x00000000 0x59840000 0x00000000 0x00010000>;
  3581. clocks = <0x00000003 0x00000187>;
  3582. clock-names = "ipg";
  3583. power-domains = <0x000000f9>;
  3584. status = "disabled";
  3585. };
  3586. asrc@59000000 {
  3587. compatible = "fsl,imx8qm-asrc0";
  3588. reg = <0x00000000 0x59000000 0x00000000 0x00010000>;
  3589. interrupts = <0x00000000 0x00000174 0x00000004 0x00000000 0x00000175 0x00000004>;
  3590. clocks = * 0x0000000093010780 [0x00000098];
  3591. clock-names = "ipg", "mem", "asrck_0", "asrck_1", "asrck_2", "asrck_3", "asrck_4", "asrck_5", "asrck_6", "asrck_7", "asrck_8", "asrck_9", "asrck_a", "asrck_b", "asrck_c", "asrck_d", "asrck_e", "asrck_f", "spba";
  3592. dmas = * 0x00000000930108c0 [0x00000060];
  3593. dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
  3594. fsl,asrc-rate = <0x00001f40>;
  3595. fsl,asrc-width = <0x00000010>;
  3596. power-domains = <0x000000fa>;
  3597. status = "disabled";
  3598. };
  3599. asrc@59800000 {
  3600. compatible = "fsl,imx8qm-asrc1";
  3601. reg = <0x00000000 0x59800000 0x00000000 0x00010000>;
  3602. interrupts = <0x00000000 0x0000017c 0x00000004 0x00000000 0x0000017d 0x00000004>;
  3603. clocks = * 0x0000000093010a10 [0x00000098];
  3604. clock-names = "ipg", "mem", "asrck_0", "asrck_1", "asrck_2", "asrck_3", "asrck_4", "asrck_5", "asrck_6", "asrck_7", "asrck_8", "asrck_9", "asrck_a", "asrck_b", "asrck_c", "asrck_d", "asrck_e", "asrck_f", "spba";
  3605. dmas = * 0x0000000093010b50 [0x00000060];
  3606. dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
  3607. fsl,asrc-rate = <0x00001f40>;
  3608. fsl,asrc-width = <0x00000010>;
  3609. power-domains = <0x000000fb>;
  3610. status = "disabled";
  3611. };
  3612. mqs@59850000 {
  3613. compatible = "fsl,imx8qm-mqs";
  3614. reg = <0x00000000 0x59850000 0x00000000 0x00010000>;
  3615. clocks = <0x00000003 0x00000196 0x00000003 0x00000197>;
  3616. clock-names = "core", "mclk";
  3617. power-domains = <0x000000fc>;
  3618. status = "disabled";
  3619. };
  3620. usdhc@5b010000 {
  3621. compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
  3622. interrupt-parent = <0x00000001>;
  3623. interrupts = <0x00000000 0x000000e8 0x00000004>;
  3624. reg = <0x00000000 0x5b010000 0x00000000 0x00010000>;
  3625. clocks = <0x00000003 0x000000b3 0x00000003 0x000000b9 0x00000003 0x00000000>;
  3626. clock-names = "ipg", "per", "ahb";
  3627. assigned-clocks = <0x00000003 0x00000202 0x00000003 0x000000b6>;
  3628. assigned-clock-parents = <0x00000003 0x00000201>;
  3629. assigned-clock-rates = <0x00000000 0x17d78400>;
  3630. power-domains = <0x000000fd>;
  3631. fsl,tuning-start-tap = <0x00000014>;
  3632. fsl,tuning-step = <0x00000002>;
  3633. status = "okay";
  3634. bus-width = <0x00000008>;
  3635. non-removable;
  3636. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  3637. pinctrl-0 = <0x000000fe>;
  3638. pinctrl-1 = <0x000000ff>;
  3639. pinctrl-2 = <0x00000100>;
  3640. };
  3641. usdhc@5b020000 {
  3642. compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
  3643. interrupt-parent = <0x00000001>;
  3644. interrupts = <0x00000000 0x000000e9 0x00000004>;
  3645. reg = <0x00000000 0x5b020000 0x00000000 0x00010000>;
  3646. clocks = <0x00000003 0x000000b4 0x00000003 0x000000ba 0x00000003 0x00000000>;
  3647. clock-names = "ipg", "per", "ahb";
  3648. assigned-clocks = <0x00000003 0x00000203 0x00000003 0x000000b7>;
  3649. assigned-clock-parents = <0x00000003 0x00000201>;
  3650. assigned-clock-rates = <0x00000000 0x0bebc200>;
  3651. power-domains = <0x00000101>;
  3652. fsl,tuning-start-tap = <0x00000014>;
  3653. fsl,tuning-step = <0x00000002>;
  3654. status = "okay";
  3655. bus-width = <0x00000004>;
  3656. cd-gpios = <0x00000080 0x00000009 0x00000001>;
  3657. pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
  3658. pinctrl-0 = <0x00000102 0x00000103>;
  3659. pinctrl-1 = <0x00000104 0x00000103>;
  3660. pinctrl-2 = <0x00000105 0x00000103>;
  3661. pinctrl-3 = <0x00000106 0x00000107>;
  3662. disable-wp;
  3663. no-1-8-v;
  3664. vmmc-supply = <0x0000008d>;
  3665. };
  3666. usdhc@5b030000 {
  3667. compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
  3668. interrupt-parent = <0x00000001>;
  3669. interrupts = <0x00000000 0x000000ea 0x00000004>;
  3670. reg = <0x00000000 0x5b030000 0x00000000 0x00010000>;
  3671. clocks = <0x00000003 0x000000b5 0x00000003 0x000000bb 0x00000003 0x00000000>;
  3672. clock-names = "ipg", "per", "ahb";
  3673. assigned-clocks = <0x00000003 0x00000204 0x00000003 0x000000b8>;
  3674. assigned-clock-parents = <0x00000003 0x00000201>;
  3675. assigned-clock-rates = <0x00000000 0x0bebc200>;
  3676. power-domains = <0x00000108>;
  3677. status = "disabled";
  3678. };
  3679. ethernet@5b040000 {
  3680. compatible = "fsl,imx8qm-fec";
  3681. reg = <0x00000000 0x5b040000 0x00000000 0x00010000>;
  3682. interrupt-parent = <0x00000001>;
  3683. interrupts = <0x00000000 0x00000102 0x00000004 0x00000000 0x00000100 0x00000004 0x00000000 0x00000101 0x00000004 0x00000000 0x00000103 0x00000004>;
  3684. clocks = <0x00000003 0x000000c6 0x00000003 0x000000c4 0x00000003 0x000000da 0x00000003 0x000000ce 0x00000003 0x000000cc>;
  3685. clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
  3686. assigned-clocks = <0x00000003 0x000000bc 0x00000003 0x000000bd>;
  3687. assigned-clock-rates = <0x0ee6b280 0x07735940>;
  3688. fsl,num-tx-queues = <0x00000003>;
  3689. fsl,num-rx-queues = <0x00000003>;
  3690. fsl,wakeup_irq = <0x00000000>;
  3691. power-domains = <0x00000109>;
  3692. status = "okay";
  3693. pinctrl-names = "default", "sleep";
  3694. pinctrl-0 = <0x0000010a>;
  3695. pinctrl-1 = <0x0000010b>;
  3696. phy-mode = "rmii";
  3697. phy-handle = <0x0000010c>;
  3698. fsl,magic-packet;
  3699. mdio {
  3700. #address-cells = <0x00000001>;
  3701. #size-cells = <0x00000000>;
  3702. ethernet-phy@2 {
  3703. compatible = "ethernet-phy-ieee802.3-c22";
  3704. max-speed = <0x00000064>;
  3705. reg = <0x00000002>;
  3706. linux,phandle = <0x0000010c>;
  3707. phandle = <0x0000010c>;
  3708. };
  3709. };
  3710. };
  3711. ethernet@5b050000 {
  3712. compatible = "fsl,imx8qm-fec";
  3713. reg = <0x00000000 0x5b050000 0x00000000 0x00010000>;
  3714. interrupt-parent = <0x00000001>;
  3715. interrupts = <0x00000000 0x00000106 0x00000004 0x00000000 0x00000104 0x00000004 0x00000000 0x00000105 0x00000004 0x00000000 0x00000107 0x00000004>;
  3716. clocks = <0x00000003 0x000000c9 0x00000003 0x000000c7 0x00000003 0x000000d5 0x00000003 0x000000cf 0x00000003 0x000000cd>;
  3717. clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
  3718. assigned-clocks = <0x00000003 0x000000c1 0x00000003 0x000000be>;
  3719. assigned-clock-rates = <0x0ee6b280 0x07735940>;
  3720. fsl,num-tx-queues = <0x00000003>;
  3721. fsl,num-rx-queues = <0x00000003>;
  3722. fsl,wakeup_irq = <0x00000000>;
  3723. power-domains = <0x0000010d>;
  3724. status = "disabled";
  3725. };
  3726. mlb@5B060000 {
  3727. compatible = "fsl,imx6q-mlb150";
  3728. reg = <0x00000000 0x5b060000 0x00000000 0x00010000>;
  3729. interrupt-parent = <0x00000001>;
  3730. interrupts = <0x00000000 0x00000109 0x00000004 0x00000000 0x0000010a 0x00000004>;
  3731. clocks = <0x00000003 0x000000f3 0x00000003 0x000000f2 0x00000003 0x000000f4>;
  3732. clock-names = "mlb", "hclk", "ipg";
  3733. assigned-clocks = <0x00000003 0x000000f3 0x00000003 0x000000f2 0x00000003 0x000000f4>;
  3734. assigned-clock-rates = <0x13de4355 0x13de4355 0x04f790d5>;
  3735. power-domains = <0x0000010e>;
  3736. status = "disabled";
  3737. };
  3738. gpt0@5d140000 {
  3739. compatible = "fsl,imx8qxp-gpt";
  3740. reg = <0x00000000 0x5d140000 0x00000000 0x00004000>;
  3741. interrupts = <0x00000000 0x00000050 0x00000004>;
  3742. clocks = <0x00000003 0x00000000 0x00000003 0x0000000a>;
  3743. clock-names = "ipg", "per";
  3744. power-domains = <0x0000010f>;
  3745. };
  3746. dsp@596e8000 {
  3747. compatible = "fsl,imx8qxp-dsp";
  3748. reserved-region = <0x00000110>;
  3749. reg = <0x00000000 0x596e8000 0x00000000 0x00088000>;
  3750. clocks = <0x00000003 0x000001b4 0x00000003 0x000001b6 0x00000003 0x000001b5>;
  3751. clock-names = "ipg", "ocram", "core";
  3752. fsl,dsp-firmware = "imx/dsp/hifi4.bin";
  3753. power-domains = <0x00000111>;
  3754. };
  3755. esai@59010000 {
  3756. compatible = "fsl,imx8qm-esai";
  3757. reg = <0x00000000 0x59010000 0x00000000 0x00010000>;
  3758. interrupts = <0x00000000 0x00000199 0x00000004>;
  3759. clocks = <0x00000003 0x00000188 0x00000003 0x00000189 0x00000003 0x00000188 0x00000003 0x00000000>;
  3760. clock-names = "core", "extal", "fsys", "spba";
  3761. dmas = <0x000000f0 0x00000006 0x00000000 0x00000001 0x000000f0 0x00000007 0x00000000 0x00000000>;
  3762. dma-names = "rx", "tx";
  3763. power-domains = <0x00000112>;
  3764. status = "disabled";
  3765. };
  3766. spdif@59020000 {
  3767. compatible = "fsl,imx8qm-spdif";
  3768. reg = <0x00000000 0x59020000 0x00000000 0x00010000>;
  3769. interrupts = <0x00000000 0x000001c8 0x00000004 0x00000000 0x000001ca 0x00000004>;
  3770. clocks = * 0x0000000093011a6c [0x00000050];
  3771. clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba";
  3772. dmas = <0x000000f0 0x00000008 0x00000000 0x00000005 0x000000f0 0x00000009 0x00000000 0x00000004>;
  3773. dma-names = "rx", "tx";
  3774. power-domains = <0x00000113>;
  3775. status = "disabled";
  3776. };
  3777. flexspi@05d120000 {
  3778. #address-cells = <0x00000001>;
  3779. #size-cells = <0x00000000>;
  3780. compatible = "fsl,imx8qxp-flexspi";
  3781. reg = <0x00000000 0x5d120000 0x00000000 0x00010000 0x00000000 0x08000000 0x00000000 0x10000000>;
  3782. reg-names = "FlexSPI", "FlexSPI-memory";
  3783. interrupts = <0x00000000 0x0000005c 0x00000004>;
  3784. clocks = <0x00000003 0x00000061>;
  3785. assigned-clock-rates = <0x01ba8140>;
  3786. clock-names = "fspi";
  3787. power-domains = <0x00000114>;
  3788. status = "disabled";
  3789. };
  3790. hyperbus@05d120000 {
  3791. #address-cells = <0x00000001>;
  3792. #size-cells = <0x00000001>;
  3793. compatible = "fsl,imx8qxp-hyperbus";
  3794. reg = <0x00000000 0x5d120000 0x00000000 0x00010000 0x00000000 0x08000000 0x00000000 0x04000000>;
  3795. ranges = <0x00000000 0x00000000 0x08000000 0x04000000>;
  3796. reg-names = "HyperBus", "HyperBus-memory";
  3797. interrupts = <0x00000000 0x0000005c 0x00000004>;
  3798. clocks = <0x00000003 0x00000061>;
  3799. assigned-clock-rates = <0x01ba8140>;
  3800. clock-names = "hyperbus";
  3801. power-domains = <0x00000114>;
  3802. status = "disabled";
  3803. };
  3804. display-subsystem {
  3805. compatible = "fsl,imx-display-subsystem";
  3806. ports = <0x00000115 0x00000116>;
  3807. status = "okay";
  3808. };
  3809. dma_cap {
  3810. compatible = "dma-capability";
  3811. only-dma-mask32 = <0x00000001>;
  3812. };
  3813. hsio@5f080000 {
  3814. compatible = "fsl,imx8qm-hsio", "syscon";
  3815. reg = <0x00000000 0x5f080000 0x00000000 0x000f0000>;
  3816. linux,phandle = <0x00000119>;
  3817. phandle = <0x00000119>;
  3818. };
  3819. ocotp {
  3820. #address-cells = <0x00000001>;
  3821. #size-cells = <0x00000001>;
  3822. compatible = "fsl,imx8qxp-ocotp", "syscon";
  3823. };
  3824. pcie@0x5f010000 {
  3825. compatible = "fsl,imx8qxp-pcie", "snps,dw-pcie";
  3826. reg = <0x00000000 0x5f010000 0x00000000 0x00010000 0x00000000 0x7ff00000 0x00000000 0x00080000>;
  3827. reg-names = "dbi", "config";
  3828. reserved-region = <0x00000117>;
  3829. #address-cells = <0x00000003>;
  3830. #size-cells = <0x00000002>;
  3831. device_type = "pci";
  3832. ranges = <0x81000000 0x00000000 0x00000000 0x00000000 0x7ff80000 0x00000000 0x00010000 0x82000000 0x00000000 0x70000000 0x00000000 0x70000000 0x00000000 0x0ff00000>;
  3833. num-lanes = <0x00000001>;
  3834. #interrupt-cells = <0x00000001>;
  3835. interrupts = <0x00000000 0x00000066 0x00000004 0x00000000 0x00000068 0x00000004>;
  3836. interrupt-names = "msi";
  3837. clocks = <0x00000003 0x00000140 0x00000003 0x00000141 0x00000003 0x00000148 0x00000003 0x00000143 0x00000003 0x00000142>;
  3838. clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi";
  3839. interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
  3840. interrupt-map = * 0x0000000093012150 [0x00000080];
  3841. power-domains = <0x00000118>;
  3842. fsl,max-link-speed = <0x00000001>;
  3843. hsio-cfg = <0x00000003>;
  3844. hsio = <0x00000119>;
  3845. ctrl-id = <0x00000001>;
  3846. cpu-base-addr = <0x80000000>;
  3847. status = "okay";
  3848. pinctrl-names = "default";
  3849. pinctrl-0 = <0x0000011a 0x0000011b>;
  3850. ext_osc = <0x00000001>;
  3851. clkreq-gpio = <0x0000008a 0x00000003 0x00000000>;
  3852. disable-gpio = <0x0000008a 0x00000006 0x00000001>;
  3853. power-on-gpio = <0x0000008a 0x00000002 0x00000001>;
  3854. reset-gpio = <0x0000011c 0x00000000 0x00000001>;
  3855. };
  3856. imx_ion {
  3857. compatible = "fsl,mxc-ion";
  3858. fsl,heap-id = <0x00000000>;
  3859. };
  3860. vpu@2c000000 {
  3861. compatible = "nxp,imx8qm-vpu", "nxp,imx8qxp-vpu";
  3862. reg = <0x00000000 0x2c000000 0x00000000 0x01000000>;
  3863. reg-names = "vpu_regs";
  3864. interrupts = <0x00000000 0x000001d0 0x00000004 0x00000000 0x000001d1 0x00000004 0x00000000 0x000001d2 0x00000004 0x00000000 0x000001d3 0x00000004 0x00000000 0x000001d4 0x00000004>;
  3865. interrupt-names = "enc_irq", "enc_fiq", "dec_irq", "dec_fiq", "dec_sif";
  3866. clocks = <0x00000003 0x000001ea>;
  3867. clock-names = "vpu_clk";
  3868. assigned-clocks = <0x00000003 0x000001ea>;
  3869. power-domains = <0x0000011d>;
  3870. status = "okay";
  3871. };
  3872. vpu_decoder@2c000000 {
  3873. compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
  3874. boot-region = <0x0000011e>;
  3875. rpc-region = <0x0000011f>;
  3876. reg = <0x00000000 0x2c000000 0x00000000 0x01000000>;
  3877. reg-names = "vpu_regs";
  3878. power-domains = <0x0000011d>;
  3879. reg-csr = <0x2d040000>;
  3880. status = "okay";
  3881. clocks = <0x00000003 0x000001ea>;
  3882. clock-names = "vpu_clk";
  3883. assigned-clocks = <0x00000003 0x000001ea>;
  3884. core_type = <0x00000001>;
  3885. };
  3886. vpu_encoder@2d000000 {
  3887. compatible = "nxp,imx8qxp-b0-vpuenc";
  3888. #address-cells = <0x00000001>;
  3889. #size-cells = <0x00000001>;
  3890. boot-region = <0x00000120>;
  3891. rpc-region = <0x00000121>;
  3892. reserved-region = <0x00000122>;
  3893. reg = <0x00000000 0x2d000000 0x00000000 0x01000000 0x00000000 0x2c000000 0x00000000 0x02000000>;
  3894. reg-names = "vpu_regs";
  3895. power-domains = <0x00000123>;
  3896. reg-rpc-system = <0x40000000>;
  3897. resolution-max = <0x00000780 0x00000780>;
  3898. fps-max = <0x00000078>;
  3899. status = "okay";
  3900. core_type = <0x00000001>;
  3901. core0@1020000 {
  3902. compatible = "fsl,imx8-mu1-vpu-m0";
  3903. reg = <0x01020000 0x00020000>;
  3904. reg-csr = <0x01050000 0x00010000>;
  3905. interrupts = <0x00000000 0x000001d6 0x00000004>;
  3906. fsl,vpu_ap_mu_id = <0x00000011>;
  3907. fw-buf-size = <0x00200000>;
  3908. rpc-buf-size = <0x00080000>;
  3909. print-buf-size = <0x00080000>;
  3910. };
  3911. };
  3912. imx_rpmsg {
  3913. compatible = "fsl,rpmsg-bus", "simple-bus";
  3914. #address-cells = <0x00000002>;
  3915. #size-cells = <0x00000002>;
  3916. ranges;
  3917. mu_rpmsg@5d200000 {
  3918. compatible = "fsl,imx6sx-mu";
  3919. reg = <0x00000000 0x5d200000 0x00000000 0x00010000>;
  3920. interrupts = <0x00000000 0x000000b8 0x00000004>;
  3921. clocks = <0x00000003 0x00000211>;
  3922. clock-names = "ipg";
  3923. power-domains = <0x00000124>;
  3924. };
  3925. rpmsg {
  3926. compatible = "fsl,imx8qxp-rpmsg";
  3927. status = "okay";
  3928. mub-partition = <0x00000003>;
  3929. power-domains = <0x00000124>;
  3930. memory-region = <0x00000125>;
  3931. vdev-nums = <0x00000002>;
  3932. reg = <0x00000000 0x90000000 0x00000000 0x00020000>;
  3933. };
  3934. };
  3935. caam@0x31400000 {
  3936. compatible = "fsl,sec-v4.0";
  3937. reg = <0x00000000 0x31400000 0x00000000 0x00400000>;
  3938. interrupts = <0x00000000 0x00000094 0x00000004>;
  3939. #address-cells = <0x00000001>;
  3940. #size-cells = <0x00000001>;
  3941. ranges = <0x00000000 0x00000000 0x31400000 0x00400000>;
  3942. fsl,sec-era = <0x00000009>;
  3943. jr1@0x20000 {
  3944. compatible = "fsl,sec-v4.0-job-ring";
  3945. reg = <0x00020000 0x00001000>;
  3946. interrupts = <0x00000000 0x000001c4 0x00000004>;
  3947. power-domains = <0x00000126>;
  3948. status = "disabled";
  3949. };
  3950. jr2@30000 {
  3951. compatible = "fsl,sec-v4.0-job-ring";
  3952. reg = <0x00030000 0x00001000>;
  3953. interrupts = <0x00000000 0x000001c5 0x00000004>;
  3954. power-domains = <0x00000127>;
  3955. status = "okay";
  3956. };
  3957. jr3@40000 {
  3958. compatible = "fsl,sec-v4.0-job-ring";
  3959. reg = <0x00040000 0x00001000>;
  3960. interrupts = <0x00000000 0x000001c6 0x00000004>;
  3961. power-domains = <0x00000128>;
  3962. status = "okay";
  3963. };
  3964. };
  3965. caam-sm@31800000 {
  3966. compatible = "fsl,imx6q-caam-sm";
  3967. reg = <0x00000000 0x31800000 0x00000000 0x00010000>;
  3968. };
  3969. sc-powerkey {
  3970. compatible = "fsl,imx8-pwrkey";
  3971. linux,keycode = <0x00000074>;
  3972. wakeup-source;
  3973. };
  3974. wdog {
  3975. compatible = "fsl,imx8-wdt";
  3976. };
  3977. chosen {
  3978. bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
  3979. stdout-path = "/serial@5a090000";
  3980. #address-cells = <0x00000002>;
  3981. #size-cells = <0x00000002>;
  3982. module@0 {
  3983. bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk0p2 rootwait rw";
  3984. xen,dom0-bootargs = "console=dtuart dtuart=ttyLP3 earlycon=lpuart3,0x5a090000,115200";
  3985. compatible = "xen,linux-zimage", "xen,multiboot-module";
  3986. reg = <0x00000000 0x82100000 0x00000000 0x01490a00>;
  3987. };
  3988. };
  3989. backlight {
  3990. compatible = "pwm-backlight";
  3991. pinctrl-names = "default";
  3992. pinctrl-0 = <0x00000129>;
  3993. enable-gpios = <0x00000080 0x0000000c 0x00000000>;
  3994. status = "okay";
  3995. brightness-levels = <0x00000000 0x0000002d 0x0000003f 0x00000058 0x00000077 0x0000009e 0x000000cb 0x000000ff>;
  3996. default-brightness-level = <0x00000004>;
  3997. pwms = <0x0000012a 0x00000000 0x0065b9ab 0x00000001>;
  3998. linux,phandle = <0x0000012b>;
  3999. phandle = <0x0000012b>;
  4000. };
  4001. panel {
  4002. compatible = "panel-dpi";
  4003. backlight = <0x0000012b>;
  4004. enable-gpios = <0x0000011c 0x00000013 0x00000000>;
  4005. power-supply = <0x000000bd>;
  4006. width-mm = <0x000000d9>;
  4007. height-mm = <0x00000088>;
  4008. data-mapping = "bgr666";
  4009. panel-timing {
  4010. clock-frequency = <0x018023d8>;
  4011. hactive = <0x00000280>;
  4012. hback-porch = <0x00000030>;
  4013. hfront-porch = <0x00000010>;
  4014. hsync-len = <0x00000060>;
  4015. vactive = <0x000001e0>;
  4016. vback-porch = <0x0000001f>;
  4017. vfront-porch = <0x0000000b>;
  4018. vsync-len = <0x00000002>;
  4019. pixelclk-active = <0x00000000>;
  4020. };
  4021. port {
  4022. endpoint {
  4023. remote-endpoint = <0x0000012c>;
  4024. linux,phandle = <0x00000056>;
  4025. phandle = <0x00000056>;
  4026. };
  4027. };
  4028. };
  4029. regulators {
  4030. compatible = "simple-bus";
  4031. #address-cells = <0x00000001>;
  4032. #size-cells = <0x00000000>;
  4033. regulator-module-3v3 {
  4034. compatible = "regulator-fixed";
  4035. regulator-name = "+V3.3";
  4036. regulator-min-microvolt = <0x00325aa0>;
  4037. regulator-max-microvolt = <0x00325aa0>;
  4038. linux,phandle = <0x0000008d>;
  4039. phandle = <0x0000008d>;
  4040. };
  4041. regulator-module-3v3-avdd {
  4042. compatible = "regulator-fixed";
  4043. regulator-name = "+V3.3_AVDD_AUDIO";
  4044. regulator-min-microvolt = <0x00325aa0>;
  4045. regulator-max-microvolt = <0x00325aa0>;
  4046. linux,phandle = <0x0000008c>;
  4047. phandle = <0x0000008c>;
  4048. };
  4049. regulator-vref-1v8 {
  4050. compatible = "regulator-fixed";
  4051. regulator-name = "vref-1v8";
  4052. regulator-min-microvolt = <0x001b7740>;
  4053. regulator-max-microvolt = <0x001b7740>;
  4054. linux,phandle = <0x00000084>;
  4055. phandle = <0x00000084>;
  4056. };
  4057. regulator-vga-avcc {
  4058. compatible = "regulator-fixed";
  4059. regulator-name = "+3.3V_AVCC_VGA";
  4060. regulator-min-microvolt = <0x00325aa0>;
  4061. regulator-max-microvolt = <0x00325aa0>;
  4062. regulator-always-on;
  4063. };
  4064. regulator-3v3 {
  4065. compatible = "regulator-fixed";
  4066. regulator-name = "3.3V";
  4067. regulator-min-microvolt = <0x00325aa0>;
  4068. regulator-max-microvolt = <0x00325aa0>;
  4069. linux,phandle = <0x000000bd>;
  4070. phandle = <0x000000bd>;
  4071. };
  4072. regulator-5v0 {
  4073. compatible = "regulator-fixed";
  4074. regulator-name = "5V";
  4075. regulator-min-microvolt = <0x004c4b40>;
  4076. regulator-max-microvolt = <0x004c4b40>;
  4077. linux,phandle = <0x000000be>;
  4078. phandle = <0x000000be>;
  4079. };
  4080. regulator-usbh-vbus {
  4081. compatible = "regulator-fixed";
  4082. pinctrl-names = "default";
  4083. pinctrl-0 = <0x0000012d>;
  4084. regulator-name = "usbh_vbus";
  4085. regulator-min-microvolt = <0x004c4b40>;
  4086. regulator-max-microvolt = <0x004c4b40>;
  4087. gpio = <0x0000011c 0x00000003 0x00000001>;
  4088. regulator-always-on;
  4089. linux,phandle = <0x00000097>;
  4090. phandle = <0x00000097>;
  4091. };
  4092. };
  4093. sound {
  4094. compatible = "simple-audio-card";
  4095. simple-audio-card,name = "imx8qxp-sgtl5000";
  4096. simple-audio-card,format = "i2s";
  4097. simple-audio-card,bitclock-master = <0x0000012e>;
  4098. simple-audio-card,frame-master = <0x0000012e>;
  4099. simple-audio-card,cpu {
  4100. sound-dai = <0x0000012f>;
  4101. };
  4102. simple-audio-card,codec {
  4103. sound-dai = <0x00000130>;
  4104. clocks = <0x00000003 0x000001ac>;
  4105. linux,phandle = <0x0000012e>;
  4106. phandle = <0x0000012e>;
  4107. };
  4108. };
  4109. clk16m {
  4110. compatible = "fixed-clock";
  4111. #clock-cells = <0x00000000>;
  4112. clock-frequency = "", "�$";
  4113. linux,phandle = <0x000000bc>;
  4114. phandle = <0x000000bc>;
  4115. };
  4116. usbc_det {
  4117. compatible = "linux,extcon-usb-gpio";
  4118. debounce = <0x00000019>;
  4119. id-gpio = <0x00000131 0x00000009 0x00000000>;
  4120. pinctrl-names = "default";
  4121. pinctrl-0 = <0x00000132>;
  4122. linux,phandle = <0x00000096>;
  4123. phandle = <0x00000096>;
  4124. };
  4125. gpio-keys {
  4126. compatible = "gpio-keys";
  4127. pinctrl-names = "default";
  4128. pinctrl-0 = <0x00000133>;
  4129. wakeup {
  4130. label = "Wake-Up";
  4131. gpios = <0x00000080 0x0000000a 0x00000000>;
  4132. linux,code = <0x0000008f>;
  4133. debounce-interval = <0x0000000a>;
  4134. wakeup-source;
  4135. };
  4136. };
  4137. };
  4138.  
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!