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sunxi-h3-h5.dtsi

hanni76
Dec 13th, 2017
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  1. /*
  2. * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42.  
  43. #include <dt-bindings/clock/sun8i-de2.h>
  44. #include <dt-bindings/clock/sun8i-h3-ccu.h>
  45. #include <dt-bindings/clock/sun8i-r-ccu.h>
  46. #include <dt-bindings/interrupt-controller/arm-gic.h>
  47. #include <dt-bindings/reset/sun8i-de2.h>
  48. #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49. #include <dt-bindings/reset/sun8i-r-ccu.h>
  50.  
  51. / {
  52. interrupt-parent = <&gic>;
  53. #address-cells = <1>;
  54. #size-cells = <1>;
  55.  
  56. sound_hdmi: sound {
  57. compatible = "simple-audio-card";
  58. simple-audio-card,format = "i2s";
  59. simple-audio-card,name = "allwinner,hdmi";
  60. simple-audio-card,mclk-fs = <256>;
  61. status = "disabled";
  62.  
  63. simple-audio-card,codec {
  64. sound-dai = <&hdmi>;
  65. };
  66.  
  67. simple-audio-card,cpu {
  68. sound-dai = <&i2s2>;
  69. };
  70. };
  71.  
  72. clocks {
  73. #address-cells = <1>;
  74. #size-cells = <1>;
  75. ranges;
  76.  
  77. osc24M: osc24M_clk {
  78. #clock-cells = <0>;
  79. compatible = "fixed-clock";
  80. clock-frequency = <24000000>;
  81. clock-output-names = "osc24M";
  82. };
  83.  
  84. osc32k: osc32k_clk {
  85. #clock-cells = <0>;
  86. compatible = "fixed-clock";
  87. clock-frequency = <32768>;
  88. clock-output-names = "osc32k";
  89. };
  90.  
  91. iosc: internal-osc-clk {
  92. #clock-cells = <0>;
  93. compatible = "fixed-clock";
  94. clock-frequency = <16000000>;
  95. clock-accuracy = <300000000>;
  96. clock-output-names = "iosc";
  97. };
  98. };
  99.  
  100. de: display-engine {
  101. compatible = "allwinner,sun8i-h3-display-engine";
  102. allwinner,pipelines = <&mixer0>,
  103. <&mixer1>;
  104. status = "disabled";
  105. };
  106.  
  107. soc {
  108. compatible = "simple-bus";
  109. #address-cells = <1>;
  110. #size-cells = <1>;
  111. ranges;
  112.  
  113. display_clocks: clock@1000000 {
  114. /* compatible is in per SoC .dtsi file */
  115. reg = <0x01000000 0x100000>;
  116. clocks = <&ccu CLK_BUS_DE>,
  117. <&ccu CLK_DE>;
  118. clock-names = "bus",
  119. "mod";
  120. resets = <&ccu RST_BUS_DE>;
  121. #clock-cells = <1>;
  122. #reset-cells = <1>;
  123. assigned-clocks = <&ccu CLK_DE>;
  124. assigned-clock-parents = <&ccu CLK_PLL_DE>;
  125. assigned-clock-rates = <432000000>;
  126. };
  127.  
  128. hdmi: hdmi@1ee0000 {
  129. #sound-dai-cells = <0>;
  130. compatible = "allwinner,sun8i-h3-dw-hdmi";
  131. reg = <0x01ee0000 0x10000>,
  132. <0x01ef0000 0x10000>;
  133. reg-io-width = <1>;
  134. interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  135. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI>,
  136. <&ccu CLK_HDMI_DDC>;
  137. clock-names = "iahb", "isfr", "ddc";
  138. resets = <&ccu RST_BUS_HDMI0>, <&ccu RST_BUS_HDMI1>;
  139. reset-names = "hdmi", "ddc";
  140. status = "disabled";
  141.  
  142. ports {
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145.  
  146. hdmi_in: port@0 {
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. reg = <0>;
  150.  
  151. hdmi_in_tcon0: endpoint@0 {
  152. reg = <0>;
  153. remote-endpoint = <&tcon0_out_hdmi>;
  154. };
  155. };
  156.  
  157. hdmi_out: port@1 {
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. reg = <1>;
  161. };
  162. };
  163. };
  164.  
  165. mixer0: mixer@1100000 {
  166. compatible = "allwinner,sun8i-h3-de2-mixer0";
  167. reg = <0x01100000 0x100000>;
  168. clocks = <&display_clocks CLK_BUS_MIXER0>,
  169. <&display_clocks CLK_MIXER0>;
  170. clock-names = "bus",
  171. "mod";
  172. resets = <&display_clocks RST_MIXER0>;
  173. status = "disabled";
  174.  
  175. ports {
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178.  
  179. mixer0_out: port@1 {
  180. #address-cells = <1>;
  181. #size-cells = <0>;
  182. reg = <1>;
  183.  
  184. mixer0_out_tcon0: endpoint@0 {
  185. reg = <0>;
  186. remote-endpoint = <&tcon0_in_mixer0>;
  187. };
  188.  
  189. mixer0_out_tcon1: endpoint@1 {
  190. reg = <1>;
  191. remote-endpoint = <&tcon1_in_mixer0>;
  192. };
  193. };
  194. };
  195. };
  196.  
  197. mixer1: mixer@1200000 {
  198. compatible = "allwinner,sun8i-h3-de2-mixer1";
  199. reg = <0x01200000 0x100000>;
  200. clocks = <&display_clocks CLK_BUS_MIXER1>,
  201. <&display_clocks CLK_MIXER1>;
  202. clock-names = "bus",
  203. "mod";
  204. /* resets is in per SoC .dtsi file */
  205. status = "disabled";
  206.  
  207. ports {
  208. #address-cells = <1>;
  209. #size-cells = <0>;
  210.  
  211. mixer1_out: port@1 {
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. reg = <1>;
  215.  
  216. mixer1_out_tcon0: endpoint@0 {
  217. reg = <0>;
  218. remote-endpoint = <&tcon0_in_mixer1>;
  219. };
  220.  
  221. mixer1_out_tcon1: endpoint@1 {
  222. reg = <1>;
  223. remote-endpoint = <&tcon1_in_mixer1>;
  224. };
  225. };
  226. };
  227. };
  228.  
  229. syscon: syscon@1c00000 {
  230. compatible = "allwinner,sun8i-h3-system-controller",
  231. "syscon";
  232. reg = <0x01c00000 0x1000>;
  233. };
  234.  
  235. dma: dma-controller@01c02000 {
  236. compatible = "allwinner,sun8i-h3-dma";
  237. reg = <0x01c02000 0x1000>;
  238. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  239. clocks = <&ccu CLK_BUS_DMA>;
  240. resets = <&ccu RST_BUS_DMA>;
  241. #dma-cells = <1>;
  242. };
  243.  
  244. tcon0: lcd-controller@1c0c000 {
  245. compatible = "allwinner,sun8i-h3-tcon";
  246. reg = <0x01c0c000 0x1000>;
  247. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  248. clocks = <&ccu CLK_BUS_TCON0>,
  249. <&ccu CLK_TCON0>;
  250. clock-names = "ahb",
  251. "tcon-ch1";
  252. resets = <&ccu RST_BUS_TCON0>;
  253. reset-names = "lcd";
  254. status = "disabled";
  255.  
  256. ports {
  257. #address-cells = <1>;
  258. #size-cells = <0>;
  259.  
  260. tcon0_in: port@0 {
  261. #address-cells = <1>;
  262. #size-cells = <0>;
  263. reg = <0>;
  264.  
  265. tcon0_in_mixer0: endpoint@0 {
  266. reg = <0>;
  267. remote-endpoint = <&mixer0_out_tcon0>;
  268. };
  269.  
  270. tcon0_in_mixer1: endpoint@1 {
  271. reg = <1>;
  272. remote-endpoint = <&mixer1_out_tcon0>;
  273. };
  274. };
  275.  
  276. tcon0_out: port@1 {
  277. #address-cells = <1>;
  278. #size-cells = <0>;
  279. reg = <1>;
  280.  
  281. tcon0_out_hdmi: endpoint@1 {
  282. reg = <1>;
  283. remote-endpoint = <&hdmi_in_tcon0>;
  284. };
  285. };
  286. };
  287. };
  288.  
  289. tcon1: lcd-controller@1c0d000 {
  290. compatible = "allwinner,sun8i-h3-tcon";
  291. reg = <0x01c0d000 0x1000>;
  292. interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  293. clocks = <&ccu CLK_BUS_TCON1>,
  294. <&ccu CLK_TVE>;
  295. clock-names = "ahb",
  296. "tcon-ch1";
  297. resets = <&ccu RST_BUS_TCON1>;
  298. reset-names = "lcd";
  299. status = "disabled";
  300.  
  301. ports {
  302. #address-cells = <1>;
  303. #size-cells = <0>;
  304.  
  305. tcon1_in: port@0 {
  306. #address-cells = <1>;
  307. #size-cells = <0>;
  308. reg = <0>;
  309.  
  310. tcon1_in_mixer0: endpoint@0 {
  311. reg = <0>;
  312. remote-endpoint = <&mixer0_out_tcon1>;
  313. };
  314.  
  315. tcon1_in_mixer1: endpoint@1 {
  316. reg = <1>;
  317. remote-endpoint = <&mixer1_out_tcon1>;
  318. };
  319. };
  320.  
  321. tcon1_out: port@1 {
  322. #address-cells = <1>;
  323. #size-cells = <0>;
  324. reg = <1>;
  325. };
  326. };
  327. };
  328.  
  329. mmc0: mmc@01c0f000 {
  330. /* compatible and clocks are in per SoC .dtsi file */
  331. reg = <0x01c0f000 0x1000>;
  332. resets = <&ccu RST_BUS_MMC0>;
  333. reset-names = "ahb";
  334. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  335. status = "disabled";
  336. #address-cells = <1>;
  337. #size-cells = <0>;
  338. };
  339.  
  340. mmc1: mmc@01c10000 {
  341. /* compatible and clocks are in per SoC .dtsi file */
  342. reg = <0x01c10000 0x1000>;
  343. resets = <&ccu RST_BUS_MMC1>;
  344. reset-names = "ahb";
  345. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  346. status = "disabled";
  347. #address-cells = <1>;
  348. #size-cells = <0>;
  349. };
  350.  
  351. mmc2: mmc@01c11000 {
  352. /* compatible and clocks are in per SoC .dtsi file */
  353. reg = <0x01c11000 0x1000>;
  354. resets = <&ccu RST_BUS_MMC2>;
  355. reset-names = "ahb";
  356. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  357. status = "disabled";
  358. #address-cells = <1>;
  359. #size-cells = <0>;
  360. };
  361.  
  362. usb_otg: usb@01c19000 {
  363. compatible = "allwinner,sun8i-h3-musb";
  364. reg = <0x01c19000 0x400>;
  365. clocks = <&ccu CLK_BUS_OTG>;
  366. resets = <&ccu RST_BUS_OTG>;
  367. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  368. interrupt-names = "mc";
  369. phys = <&usbphy 0>;
  370. phy-names = "usb";
  371. extcon = <&usbphy 0>;
  372. status = "disabled";
  373. };
  374.  
  375. usbphy: phy@01c19400 {
  376. compatible = "allwinner,sun8i-h3-usb-phy";
  377. reg = <0x01c19400 0x2c>,
  378. <0x01c1a800 0x4>,
  379. <0x01c1b800 0x4>,
  380. <0x01c1c800 0x4>,
  381. <0x01c1d800 0x4>;
  382. reg-names = "phy_ctrl",
  383. "pmu0",
  384. "pmu1",
  385. "pmu2",
  386. "pmu3";
  387. clocks = <&ccu CLK_USB_PHY0>,
  388. <&ccu CLK_USB_PHY1>,
  389. <&ccu CLK_USB_PHY2>,
  390. <&ccu CLK_USB_PHY3>;
  391. clock-names = "usb0_phy",
  392. "usb1_phy",
  393. "usb2_phy",
  394. "usb3_phy";
  395. resets = <&ccu RST_USB_PHY0>,
  396. <&ccu RST_USB_PHY1>,
  397. <&ccu RST_USB_PHY2>,
  398. <&ccu RST_USB_PHY3>;
  399. reset-names = "usb0_reset",
  400. "usb1_reset",
  401. "usb2_reset",
  402. "usb3_reset";
  403. status = "disabled";
  404. #phy-cells = <1>;
  405. };
  406.  
  407. ehci0: usb@01c1a000 {
  408. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  409. reg = <0x01c1a000 0x100>;
  410. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  411. clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
  412. resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
  413. status = "disabled";
  414. };
  415.  
  416. ohci0: usb@01c1a400 {
  417. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  418. reg = <0x01c1a400 0x100>;
  419. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  420. clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
  421. <&ccu CLK_USB_OHCI0>;
  422. resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
  423. status = "disabled";
  424. };
  425.  
  426. ehci1: usb@01c1b000 {
  427. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  428. reg = <0x01c1b000 0x100>;
  429. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  430. clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
  431. resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
  432. phys = <&usbphy 1>;
  433. phy-names = "usb";
  434. status = "disabled";
  435. };
  436.  
  437. ohci1: usb@01c1b400 {
  438. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  439. reg = <0x01c1b400 0x100>;
  440. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  441. clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
  442. <&ccu CLK_USB_OHCI1>;
  443. resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
  444. phys = <&usbphy 1>;
  445. phy-names = "usb";
  446. status = "disabled";
  447. };
  448.  
  449. ehci2: usb@01c1c000 {
  450. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  451. reg = <0x01c1c000 0x100>;
  452. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  453. clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
  454. resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
  455. phys = <&usbphy 2>;
  456. phy-names = "usb";
  457. status = "disabled";
  458. };
  459.  
  460. ohci2: usb@01c1c400 {
  461. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  462. reg = <0x01c1c400 0x100>;
  463. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  464. clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
  465. <&ccu CLK_USB_OHCI2>;
  466. resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
  467. phys = <&usbphy 2>;
  468. phy-names = "usb";
  469. status = "disabled";
  470. };
  471.  
  472. ehci3: usb@01c1d000 {
  473. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  474. reg = <0x01c1d000 0x100>;
  475. interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
  476. clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
  477. resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
  478. phys = <&usbphy 3>;
  479. phy-names = "usb";
  480. status = "disabled";
  481. };
  482.  
  483. ohci3: usb@01c1d400 {
  484. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  485. reg = <0x01c1d400 0x100>;
  486. interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  487. clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
  488. <&ccu CLK_USB_OHCI3>;
  489. resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
  490. phys = <&usbphy 3>;
  491. phy-names = "usb";
  492. status = "disabled";
  493. };
  494.  
  495. ccu: clock@01c20000 {
  496. /* compatible is in per SoC .dtsi file */
  497. reg = <0x01c20000 0x400>;
  498. clocks = <&osc24M>, <&osc32k>;
  499. clock-names = "hosc", "losc";
  500. #clock-cells = <1>;
  501. #reset-cells = <1>;
  502. };
  503.  
  504. pio: pinctrl@01c20800 {
  505. /* compatible is in per SoC .dtsi file */
  506. reg = <0x01c20800 0x400>;
  507. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  508. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  509. clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
  510. clock-names = "apb", "hosc", "losc";
  511. gpio-controller;
  512. #gpio-cells = <3>;
  513. interrupt-controller;
  514. #interrupt-cells = <3>;
  515.  
  516. emac_rgmii_pins: emac0 {
  517. pins = "PD0", "PD1", "PD2", "PD3", "PD4",
  518. "PD5", "PD7", "PD8", "PD9", "PD10",
  519. "PD12", "PD13", "PD15", "PD16", "PD17";
  520. function = "emac";
  521. drive-strength = <40>;
  522. };
  523.  
  524. i2c0_pins: i2c0 {
  525. pins = "PA11", "PA12";
  526. function = "i2c0";
  527. };
  528.  
  529. i2c1_pins: i2c1 {
  530. pins = "PA18", "PA19";
  531. function = "i2c1";
  532. };
  533.  
  534. i2c2_pins: i2c2 {
  535. pins = "PE12", "PE13";
  536. function = "i2c2";
  537. };
  538.  
  539. i2s0_pins: i2s0 {
  540. pins = "PA18", "PA19", "PA20", "PA21";
  541. function = "i2s0";
  542. };
  543.  
  544. i2s1_pins: i2s1 {
  545. pins = "PG10", "PG11", "PG12", "PG13";
  546. function = "i2s1";
  547. };
  548.  
  549. mmc0_pins_a: mmc0@0 {
  550. pins = "PF0", "PF1", "PF2", "PF3",
  551. "PF4", "PF5";
  552. function = "mmc0";
  553. drive-strength = <30>;
  554. bias-pull-up;
  555. };
  556.  
  557. mmc0_cd_pin: mmc0_cd_pin@0 {
  558. pins = "PF6";
  559. function = "gpio_in";
  560. bias-pull-up;
  561. };
  562.  
  563. mmc1_pins_a: mmc1@0 {
  564. pins = "PG0", "PG1", "PG2", "PG3",
  565. "PG4", "PG5";
  566. function = "mmc1";
  567. drive-strength = <30>;
  568. bias-pull-up;
  569. };
  570.  
  571. mmc2_8bit_pins: mmc2_8bit {
  572. pins = "PC5", "PC6", "PC8",
  573. "PC9", "PC10", "PC11",
  574. "PC12", "PC13", "PC14",
  575. "PC15", "PC16";
  576. function = "mmc2";
  577. drive-strength = <30>;
  578. bias-pull-up;
  579. };
  580.  
  581. spdif_tx_pins_a: spdif@0 {
  582. pins = "PA17";
  583. function = "spdif";
  584. };
  585.  
  586. spi0_pins: spi0 {
  587. pins = "PC0", "PC1", "PC2", "PC3";
  588. function = "spi0";
  589. };
  590.  
  591. spi1_pins: spi1 {
  592. pins = "PA15", "PA16", "PA14", "PA13";
  593. function = "spi1";
  594. };
  595.  
  596. uart0_pins_a: uart0@0 {
  597. pins = "PA4", "PA5";
  598. function = "uart0";
  599. };
  600.  
  601. uart1_pins: uart1 {
  602. pins = "PG6", "PG7";
  603. function = "uart1";
  604. };
  605.  
  606. uart1_rts_cts_pins: uart1_rts_cts {
  607. pins = "PG8", "PG9";
  608. function = "uart1";
  609. };
  610.  
  611. uart2_pins: uart2 {
  612. pins = "PA0", "PA1";
  613. function = "uart2";
  614. };
  615.  
  616. uart3_pins: uart3 {
  617. pins = "PA13", "PA14";
  618. function = "uart3";
  619. };
  620.  
  621. uart3_rts_cts_pins: uart3_rts_cts {
  622. pins = "PA15", "PA16";
  623. function = "uart3";
  624. };
  625.  
  626. };
  627.  
  628. timer@01c20c00 {
  629. compatible = "allwinner,sun4i-a10-timer";
  630. reg = <0x01c20c00 0xa0>;
  631. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  632. <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  633. clocks = <&osc24M>;
  634. };
  635.  
  636. emac: ethernet@1c30000 {
  637. compatible = "allwinner,sun8i-h3-emac";
  638. syscon = <&syscon>;
  639. reg = <0x01c30000 0x10000>;
  640. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  641. interrupt-names = "macirq";
  642. resets = <&ccu RST_BUS_EMAC>;
  643. reset-names = "stmmaceth";
  644. clocks = <&ccu CLK_BUS_EMAC>;
  645. clock-names = "stmmaceth";
  646. #address-cells = <1>;
  647. #size-cells = <0>;
  648. status = "disabled";
  649.  
  650. mdio: mdio {
  651. #address-cells = <1>;
  652. #size-cells = <0>;
  653. int_mii_phy: ethernet-phy@1 {
  654. compatible = "ethernet-phy-ieee802.3-c22";
  655. reg = <1>;
  656. clocks = <&ccu CLK_BUS_EPHY>;
  657. resets = <&ccu RST_BUS_EPHY>;
  658. };
  659. };
  660. };
  661.  
  662. spi0: spi@01c68000 {
  663. compatible = "allwinner,sun8i-h3-spi";
  664. reg = <0x01c68000 0x1000>;
  665. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  666. clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
  667. clock-names = "ahb", "mod";
  668. dmas = <&dma 23>, <&dma 23>;
  669. dma-names = "rx", "tx";
  670. pinctrl-names = "default";
  671. pinctrl-0 = <&spi0_pins>;
  672. resets = <&ccu RST_BUS_SPI0>;
  673. status = "disabled";
  674. #address-cells = <1>;
  675. #size-cells = <0>;
  676. };
  677.  
  678. spi1: spi@01c69000 {
  679. compatible = "allwinner,sun8i-h3-spi";
  680. reg = <0x01c69000 0x1000>;
  681. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  682. clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
  683. clock-names = "ahb", "mod";
  684. dmas = <&dma 24>, <&dma 24>;
  685. dma-names = "rx", "tx";
  686. pinctrl-names = "default";
  687. pinctrl-0 = <&spi1_pins>;
  688. resets = <&ccu RST_BUS_SPI1>;
  689. status = "disabled";
  690. #address-cells = <1>;
  691. #size-cells = <0>;
  692. };
  693.  
  694. wdt0: watchdog@01c20ca0 {
  695. compatible = "allwinner,sun6i-a31-wdt";
  696. reg = <0x01c20ca0 0x20>;
  697. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  698. };
  699.  
  700. spdif: spdif@01c21000 {
  701. #sound-dai-cells = <0>;
  702. compatible = "allwinner,sun8i-h3-spdif";
  703. reg = <0x01c21000 0x400>;
  704. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  705. clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
  706. resets = <&ccu RST_BUS_SPDIF>;
  707. clock-names = "apb", "spdif";
  708. dmas = <&dma 2>;
  709. dma-names = "tx";
  710. status = "disabled";
  711. };
  712.  
  713. pwm: pwm@01c21400 {
  714. compatible = "allwinner,sun8i-h3-pwm";
  715. reg = <0x01c21400 0x8>;
  716. clocks = <&osc24M>;
  717. #pwm-cells = <3>;
  718. status = "disabled";
  719. };
  720.  
  721. i2s0: i2s@01c22000 {
  722. #sound-dai-cells = <0>;
  723. compatible = "allwinner,sun8i-h3-i2s";
  724. reg = <0x01c22000 0x400>;
  725. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  726. clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
  727. clock-names = "apb", "mod";
  728. dmas = <&dma 3>, <&dma 3>;
  729. resets = <&ccu RST_BUS_I2S0>;
  730. dma-names = "rx", "tx";
  731. status = "disabled";
  732. };
  733.  
  734. i2s1: i2s@01c22400 {
  735. #sound-dai-cells = <0>;
  736. compatible = "allwinner,sun8i-h3-i2s";
  737. reg = <0x01c22400 0x400>;
  738. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  739. clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
  740. clock-names = "apb", "mod";
  741. dmas = <&dma 4>, <&dma 4>;
  742. resets = <&ccu RST_BUS_I2S1>;
  743. dma-names = "rx", "tx";
  744. status = "disabled";
  745. };
  746.  
  747. i2s2: i2s@1c22800 {
  748. #sound-dai-cells = <0>;
  749. compatible = "allwinner,sun8i-h3-i2s";
  750. reg = <0x01c22800 0x400>;
  751. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  752. clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
  753. clock-names = "apb", "mod";
  754. dmas = <&dma 27>;
  755. resets = <&ccu RST_BUS_I2S2>;
  756. dma-names = "tx";
  757. status = "disabled";
  758. };
  759.  
  760. codec: codec@01c22c00 {
  761. #sound-dai-cells = <0>;
  762. compatible = "allwinner,sun8i-h3-codec";
  763. reg = <0x01c22c00 0x400>;
  764. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  765. clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
  766. clock-names = "apb", "codec";
  767. resets = <&ccu RST_BUS_CODEC>;
  768. dmas = <&dma 15>, <&dma 15>;
  769. dma-names = "rx", "tx";
  770. allwinner,codec-analog-controls = <&codec_analog>;
  771. status = "disabled";
  772. };
  773.  
  774. uart0: serial@01c28000 {
  775. compatible = "snps,dw-apb-uart";
  776. reg = <0x01c28000 0x400>;
  777. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  778. reg-shift = <2>;
  779. reg-io-width = <4>;
  780. clocks = <&ccu CLK_BUS_UART0>;
  781. resets = <&ccu RST_BUS_UART0>;
  782. dmas = <&dma 6>, <&dma 6>;
  783. dma-names = "rx", "tx";
  784. status = "disabled";
  785. };
  786.  
  787. uart1: serial@01c28400 {
  788. compatible = "snps,dw-apb-uart";
  789. reg = <0x01c28400 0x400>;
  790. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  791. reg-shift = <2>;
  792. reg-io-width = <4>;
  793. clocks = <&ccu CLK_BUS_UART1>;
  794. resets = <&ccu RST_BUS_UART1>;
  795. dmas = <&dma 7>, <&dma 7>;
  796. dma-names = "rx", "tx";
  797. status = "disabled";
  798. };
  799.  
  800. uart2: serial@01c28800 {
  801. compatible = "snps,dw-apb-uart";
  802. reg = <0x01c28800 0x400>;
  803. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  804. reg-shift = <2>;
  805. reg-io-width = <4>;
  806. clocks = <&ccu CLK_BUS_UART2>;
  807. resets = <&ccu RST_BUS_UART2>;
  808. dmas = <&dma 8>, <&dma 8>;
  809. dma-names = "rx", "tx";
  810. status = "disabled";
  811. };
  812.  
  813. uart3: serial@01c28c00 {
  814. compatible = "snps,dw-apb-uart";
  815. reg = <0x01c28c00 0x400>;
  816. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  817. reg-shift = <2>;
  818. reg-io-width = <4>;
  819. clocks = <&ccu CLK_BUS_UART3>;
  820. resets = <&ccu RST_BUS_UART3>;
  821. dmas = <&dma 9>, <&dma 9>;
  822. dma-names = "rx", "tx";
  823. status = "disabled";
  824. };
  825.  
  826. i2c0: i2c@01c2ac00 {
  827. compatible = "allwinner,sun6i-a31-i2c";
  828. reg = <0x01c2ac00 0x400>;
  829. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  830. clocks = <&ccu CLK_BUS_I2C0>;
  831. resets = <&ccu RST_BUS_I2C0>;
  832. pinctrl-names = "default";
  833. pinctrl-0 = <&i2c0_pins>;
  834. status = "disabled";
  835. #address-cells = <1>;
  836. #size-cells = <0>;
  837. };
  838.  
  839. i2c1: i2c@01c2b000 {
  840. compatible = "allwinner,sun6i-a31-i2c";
  841. reg = <0x01c2b000 0x400>;
  842. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  843. clocks = <&ccu CLK_BUS_I2C1>;
  844. resets = <&ccu RST_BUS_I2C1>;
  845. pinctrl-names = "default";
  846. pinctrl-0 = <&i2c1_pins>;
  847. status = "disabled";
  848. #address-cells = <1>;
  849. #size-cells = <0>;
  850. };
  851.  
  852. i2c2: i2c@01c2b400 {
  853. compatible = "allwinner,sun6i-a31-i2c";
  854. reg = <0x01c2b400 0x400>;
  855. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  856. clocks = <&ccu CLK_BUS_I2C2>;
  857. resets = <&ccu RST_BUS_I2C2>;
  858. pinctrl-names = "default";
  859. pinctrl-0 = <&i2c2_pins>;
  860. status = "disabled";
  861. #address-cells = <1>;
  862. #size-cells = <0>;
  863. };
  864.  
  865. gic: interrupt-controller@01c81000 {
  866. compatible = "arm,gic-400";
  867. reg = <0x01c81000 0x1000>,
  868. <0x01c82000 0x2000>,
  869. <0x01c84000 0x2000>,
  870. <0x01c86000 0x2000>;
  871. interrupt-controller;
  872. #interrupt-cells = <3>;
  873. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  874. };
  875.  
  876. rtc: rtc@01f00000 {
  877. compatible = "allwinner,sun6i-a31-rtc";
  878. reg = <0x01f00000 0x54>;
  879. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  880. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  881. };
  882.  
  883. r_ccu: clock@1f01400 {
  884. compatible = "allwinner,sun8i-h3-r-ccu";
  885. reg = <0x01f01400 0x100>;
  886. clocks = <&osc24M>, <&osc32k>, <&iosc>,
  887. <&ccu 9>;
  888. clock-names = "hosc", "losc", "iosc", "pll-periph";
  889. #clock-cells = <1>;
  890. #reset-cells = <1>;
  891. };
  892.  
  893. codec_analog: codec-analog@01f015c0 {
  894. compatible = "allwinner,sun8i-h3-codec-analog";
  895. reg = <0x01f015c0 0x4>;
  896. };
  897.  
  898. ir: ir@01f02000 {
  899. compatible = "allwinner,sun5i-a13-ir";
  900. clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
  901. clock-names = "apb", "ir";
  902. resets = <&r_ccu RST_APB0_IR>;
  903. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  904. reg = <0x01f02000 0x40>;
  905. status = "disabled";
  906. };
  907.  
  908. r_i2c: i2c@01f02400 {
  909. compatible = "allwinner,sun6i-a31-i2c";
  910. reg = <0x01f02400 0x400>;
  911. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  912. pinctrl-names = "default";
  913. pinctrl-0 = <&r_i2c_pins>;
  914. clocks = <&r_ccu CLK_APB0_I2C>;
  915. clock-frequency = <100000>;
  916. resets = <&r_ccu RST_APB0_I2C>;
  917. status = "disabled";
  918. #address-cells = <1>;
  919. #size-cells = <0>;
  920. };
  921.  
  922. r_pio: pinctrl@01f02c00 {
  923. compatible = "allwinner,sun8i-h3-r-pinctrl";
  924. reg = <0x01f02c00 0x400>;
  925. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  926. clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
  927. clock-names = "apb", "hosc", "losc";
  928. gpio-controller;
  929. #gpio-cells = <3>;
  930. interrupt-controller;
  931. #interrupt-cells = <3>;
  932.  
  933. ir_pins_a: ir@0 {
  934. pins = "PL11";
  935. function = "s_cir_rx";
  936. };
  937.  
  938. r_i2c_pins: r-i2c {
  939. pins = "PL0", "PL1";
  940. function = "s_i2c";
  941. };
  942. };
  943. };
  944. };
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