diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c
index 09701c17f3f6..e1654c827819 100644
--- a/drivers/net/dsa/lantiq_gswip.c
+++ b/drivers/net/dsa/lantiq_gswip.c
@@ -92,9 +92,7 @@
                     GSWIP_MDIO_PHY_FDUP_MASK)

 /* GSWIP MII Registers */
-#define GSWIP_MII_CFG0         0x00
-#define GSWIP_MII_CFG1         0x02
-#define GSWIP_MII_CFG5         0x04
+#define GSWIP_MII_CFGp(p)      (0x2 * (p))
 #define  GSWIP_MII_CFG_EN      BIT(14)
 #define  GSWIP_MII_CFG_LDCLKDIS        BIT(12)
 #define  GSWIP_MII_CFG_MODE_MIIP   0x0
@@ -392,17 +390,9 @@ static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
                   int port)
 {
-   switch (port) {
-   case 0:
-       gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG0);
-       break;
-   case 1:
-       gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG1);
-       break;
-   case 5:
-       gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG5);
-       break;
-   }
+   /* There's no MII_CFG register for the CPU port */
+   if (!dsa_is_cpu_port(priv->ds, port))
+       gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
 }

 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
@@ -822,9 +812,8 @@ static int gswip_setup(struct dsa_switch *ds)
    gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);

    /* Disable the xMII link */
-   gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 0);
-   gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 1);
-   gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 5);
+   for (i = 0; i < priv->hw_info->max_ports; i++)
+       gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i);

    /* enable special tag insertion on cpu port */
    gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,