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XikeStor SKS8300-8T OpenWrt bootlader

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Jun 23rd, 2025
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  1. [ 0.907107] Using MAC 00008243ee800000
  2. [ 0.911354] set sds port 0 to 2
  3. [ 0.914847] set sds port 8 to 3
  4. [ 0.918401] set sds port 16 to 4
  5. [ 0.921999] set sds port 20 to 5
  6. [ 0.925580] set sds port 24 to 6
  7. [ 0.929195] set sds port 25 to 7
  8. [ 0.932786] set sds port 26 to 8
  9. [ 0.936367] set sds port 27 to 9
  10. [ 0.940795] c45_mask: 00000000
  11. [ 0.966393] REALTEK RTL9300 SERDES mdio-bus:00: Detected internal RTL9300 Serdes
  12. [ 1.002239] REALTEK RTL9300 SERDES mdio-bus:08: Detected internal RTL9300 Serdes
  13. [ 1.038054] REALTEK RTL9300 SERDES mdio-bus:10: Detected internal RTL9300 Serdes
  14. [ 1.073809] REALTEK RTL9300 SERDES mdio-bus:14: Detected internal RTL9300 Serdes
  15. [ 1.109573] REALTEK RTL9300 SERDES mdio-bus:18: Detected internal RTL9300 Serdes
  16. [ 1.145226] REALTEK RTL9300 SERDES mdio-bus:19: Detected internal RTL9300 Serdes
  17. [ 1.181145] REALTEK RTL9300 SERDES mdio-bus:1a: Detected internal RTL9300 Serdes
  18. [ 1.216805] REALTEK RTL9300 SERDES mdio-bus:1b: Detected internal RTL9300 Serdes
  19. [ 1.234600] i2c_dev: i2c /dev entries driver
  20. [ 1.239673] rtl9300_i2c_probe probing I2C adapter
  21. [ 1.245024] i2c-rtl9300 1b00036c.i2c: SCL speed 100000, mode is 0
  22. [ 1.251888] rtl9300_i2c_probe scl_num 0
  23. [ 1.256159] rtl9300_i2c_probe sda_num 0
  24. [ 1.265402] NET: Registered PF_INET6 protocol family
  25. [ 1.290272] Segment Routing with IPv6
  26. [ 1.294492] In-situ OAM (IOAM) with IPv6
  27. [ 1.299176] NET: Registered PF_PACKET protocol family
  28. [ 1.305289] 8021q: 802.1Q VLAN Support v1.8
  29. [ 1.380472] REALTEK RTL9300 SERDES rtldsa_mdio-0:00: Detected internal RTL9300 Serdes
  30. [ 1.416343] REALTEK RTL9300 SERDES rtldsa_mdio-0:08: Detected internal RTL9300 Serdes
  31. [ 1.452564] REALTEK RTL9300 SERDES rtldsa_mdio-0:10: Detected internal RTL9300 Serdes
  32. [ 1.488744] REALTEK RTL9300 SERDES rtldsa_mdio-0:14: Detected internal RTL9300 Serdes
  33. [ 1.524665] REALTEK RTL9300 SERDES rtldsa_mdio-0:18: Detected internal RTL9300 Serdes
  34. [ 1.560920] REALTEK RTL9300 SERDES rtldsa_mdio-0:19: Detected internal RTL9300 Serdes
  35. [ 1.597031] REALTEK RTL9300 SERDES rtldsa_mdio-0:1a: Detected internal RTL9300 Serdes
  36. [ 1.632955] REALTEK RTL9300 SERDES rtldsa_mdio-0:1b: Detected internal RTL9300 Serdes
  37. [ 1.667222] rtl93xx_setup called
  38. [ 1.670883] In rtl83xx_vlan_setup
  39. [ 1.674560] UNKNOWN_MC_PMASK: 000000001fffffff
  40. [ 2.736876] rtl83xx_enable_phy_polling: f110101
  41. [ 2.743134] rtl930x_led_init led_set configuration invalid skipping over this set
  42. [ 2.751509] rtl930x_led_init led_set configuration invalid skipping over this set
  43. [ 2.759868] rtl930x_led_init led_set configuration invalid skipping over this set
  44. [ 2.768433] rtl83xx-switch switch@1b000000: configuring for fixed/internal link mode
  45. [ 2.777132] rtl93xx_phylink_mac_config port 28, mode 1, phy-mode internal, speed -1, link 0
  46. [ 2.787914] rtl83xx-switch switch@1b000000 lan1 (uninitialized): PHY [mdio-bus:00] driver [REALTEK RTL9300 SERDES] (irq=POLL)
  47. [ 2.803447] rtl83xx-switch switch@1b000000 lan2 (uninitialized): PHY [mdio-bus:08] driver [REALTEK RTL9300 SERDES] (irq=POLL)
  48. [ 2.819141] rtl83xx-switch switch@1b000000 lan3 (uninitialized): PHY [mdio-bus:10] driver [REALTEK RTL9300 SERDES] (irq=POLL)
  49. [ 2.834734] rtl83xx-switch switch@1b000000 lan4 (uninitialized): PHY [mdio-bus:14] driver [REALTEK RTL9300 SERDES] (irq=POLL)
  50. [ 2.850279] rtl83xx-switch switch@1b000000 lan5 (uninitialized): PHY [mdio-bus:18] driver [REALTEK RTL9300 SERDES] (irq=POLL)
  51. [ 2.865836] rtl83xx-switch switch@1b000000 lan6 (uninitialized): PHY [mdio-bus:19] driver [REALTEK RTL9300 SERDES] (irq=POLL)
  52. [ 2.881348] rtl83xx-switch switch@1b000000 lan7 (uninitialized): PHY [mdio-bus:1a] driver [REALTEK RTL9300 SERDES] (irq=POLL)
  53. [ 2.897020] rtl83xx-switch switch@1b000000 lan8 (uninitialized): PHY [mdio-bus:1b] driver [REALTEK RTL9300 SERDES] (irq=POLL)
  54. [ 2.911455] rtl838x-eth 1b00a300.ethernet eth0: entered promiscuous mode
  55. [ 2.919139] DSA: tree 0 setup
  56. [ 2.922540] LINK state irq: 23
  57. [ 2.925970] In rtl83xx_setup_qos
  58. [ 2.929813] rtl930x_dbgfs_init called
  59. [ 2.934032] rtl83xx-switch switch@1b000000: Link is Up - 10Gbps/Full - flow control off
  60. [ 2.947157] rtl83xx_fib_event_work_do: FIB4 default rule failed
  61. [ 2.953779] rtl83xx_fib_event_work_do: FIB4 default rule failed
  62. [ 2.971847] clk: Disabling unused clocks
  63. [ 3.023954] Freeing unused kernel image (initmem) memory: 9708K
  64. [ 3.030629] This architecture does not have kernel memory protection.
  65. [ 3.037831] Run /init as init process
  66. [ 3.041904] with arguments:
  67. [ 3.045194] /init
  68. [ 3.047749] with environment:
  69. [ 3.051242] HOME=/
  70. [ 3.053857] TERM=linux
  71. [ 3.552793] init: Console is alive
  72. [ 3.557191] init: - watchdog -
  73. [ 3.577549] kmodloader: loading kernel modules from /etc/modules-boot.d/*
  74. [ 3.589006] gpio_button_hotplug: loading out-of-tree module taints kernel.
  75. [ 3.602388] kmodloader: done loading kernel modules from /etc/modules-boot.d/*
  76. [ 3.621357] init: - preinit -
  77. [ 6.556931] random: crng init done
  78. Cannot parse config file '/etc/fw_env.config': No such file or directory
  79. Failed to find NVMEM device
  80. [ 7.572604] RESETTING 9300, CPU_PORT 28
  81. [ 7.777461] rtl838x-eth 1b00a300.ethernet eth0: configuring for fixed/internal link mode
  82. [ 7.786466] In rtl838x_mac_config, mode 1
  83. [ 7.791804] Setting up RTL9300 port isolation for independent operation
  84. [ 7.799267] Port 0: traffic matrix set to 0x1fffffef
  85. [ 7.804795] Port 1: traffic matrix set to 0x1fffffdf
  86. [ 7.810339] Port 2: traffic matrix set to 0x1fffffbf
  87. [ 7.815864] Port 3: traffic matrix set to 0x1fffff7f
  88. [ 7.821408] Port 4: traffic matrix set to 0x1ffffffe
  89. [ 7.826963] Port 5: traffic matrix set to 0x1ffffffd
  90. [ 7.832487] Port 6: traffic matrix set to 0x1ffffffb
  91. [ 7.838031] Port 7: traffic matrix set to 0x1ffffff7
  92. [ 7.843554] Port 8: traffic matrix set to 0x1fffffff
  93. [ 7.849099] Port 9: traffic matrix set to 0x1fffffff
  94. [ 7.854623] Port 10: traffic matrix set to 0x1fffffff
  95. [ 7.860264] Port 11: traffic matrix set to 0x1fffffff
  96. [ 7.865885] Port 12: traffic matrix set to 0x1fffffff
  97. [ 7.871525] Port 13: traffic matrix set to 0x1fffffff
  98. [ 7.877177] Port 14: traffic matrix set to 0x1fffffff
  99. [ 7.882797] Port 15: traffic matrix set to 0x1fffffff
  100. [ 7.888438] Port 16: traffic matrix set to 0x1fffffff
  101. [ 7.894059] Port 17: traffic matrix set to 0x1fffffff
  102. [ 7.899712] Port 18: traffic matrix set to 0x1fffffff
  103. [ 7.905337] Port 19: traffic matrix set to 0x1fffffff
  104. [ 7.910982] Port 20: traffic matrix set to 0x1fffffff
  105. [ 7.916598] Port 21: traffic matrix set to 0x1fffffff
  106. [ 7.922238] Port 22: traffic matrix set to 0x1fffffff
  107. [ 7.927891] Port 23: traffic matrix set to 0x1fffffff
  108. [ 7.933512] Port 24: traffic matrix set to 0x1fffffff
  109. [ 7.939152] Port 25: traffic matrix set to 0x1fffffff
  110. [ 7.944773] Port 26: traffic matrix set to 0x1fffffff
  111. [ 7.950413] Port 27: traffic matrix set to 0x1fffffff
  112. [ 7.956033] CPU port 28: traffic matrix set to 0xfffffff
  113. [ 7.961960] === Port Pairing Debug ===
  114. [ 7.966129] Port 0 traffic matrix: 0x1fffffef
  115. [ 7.970995] Port 1 traffic matrix: 0x1fffffdf
  116. [ 7.975843] Port 2 traffic matrix: 0x1fffffbf
  117. [ 7.980711] Port 3 traffic matrix: 0x1fffff7f
  118. [ 7.985560] Port 4 traffic matrix: 0x1ffffffe
  119. [ 7.990427] Port 5 traffic matrix: 0x1ffffffd
  120. [ 7.995276] Port 6 traffic matrix: 0x1ffffffb
  121. [ 8.000143] Port 7 traffic matrix: 0x1ffffff7
  122. [ 8.004992] Port 8 traffic matrix: 0x1fffffff
  123. [ 8.009873] === MAC Configuration Debug ===
  124. [ 8.014525] Port 0: MAC_CTRL=0x00000033, FORCE_MODE=0x00000194
  125. [ 8.021048] Port 1: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  126. [ 8.027591] Port 2: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  127. [ 8.034088] Port 3: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  128. [ 8.040602] Port 4: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  129. [ 8.047116] Port 5: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  130. [ 8.053608] Port 6: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  131. [ 8.060115] Port 7: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  132. [ 8.066607] Port isolation control registers:
  133. [ 8.071472] Port 0 VLAN_PB: 0x00000000
  134. [ 8.075638] Port 1 VLAN_PB: 0x00000000
  135. [ 8.079827] Port 2 VLAN_PB: 0x00000000
  136. [ 8.083994] Port 3 VLAN_PB: 0x00000000
  137. [ 8.088183] Port 4 VLAN_PB: 0x00000000
  138. [ 8.092350] Port 5 VLAN_PB: 0x00000000
  139. [ 8.096510] Port 6 VLAN_PB: 0x00000000
  140. [ 8.100699] Port 7 VLAN_PB: 0x00000000
  141. [ 8.104866] === Trunk/LAG Configuration Debug ===
  142. [ 8.110120] Trunk mode control: 0x00000000
  143. [ 8.114670] === Special Configuration Debug ===
  144. [ 8.119738] Mirror control: 0x00000000
  145. [ 8.123905] === PHY Polling Debug ===
  146. [ 8.127999] PHY polling control: 0x0f110101
  147. [ 8.132646] Port 0: PHY polling ENABLED
  148. [ 8.136931] Port 8: PHY polling ENABLED
  149. [ 8.141194] Port 16: PHY polling ENABLED
  150. [ 8.145547] Port 20: PHY polling ENABLED
  151. [ 8.149931] Port 24: PHY polling ENABLED
  152. [ 8.154291] Port 25: PHY polling ENABLED
  153. [ 8.158671] Port 26: PHY polling ENABLED
  154. [ 8.163033] Port 27: PHY polling ENABLED
  155. [ 8.167414] Port 0 SMI config: 0x00000000
  156. [ 8.171871] Port 1 SMI config: 0x00000400
  157. [ 8.176321] Port 2 SMI config: 0x00200000
  158. [ 8.180800] Port 3 SMI config: 0x00000c00
  159. [ 8.185256] Port 4 SMI config: 0x00018820
  160. [ 8.189735] Port 5 SMI config: 0x00000000
  161. [ 8.194192] Port 6 SMI config: 0x00f00000
  162. [ 8.198670] Port 7 SMI config: 0x00000000
  163. [ 8.203127] Setting up PHY polling for all ports
  164. [ 8.208280] PHY polling mask set to: 0x0f110101
  165. [ 8.213317] === Direct Link Status Debug ===
  166. [ 8.218085] MAC_LINK_STS register: 0x00000000
  167. [ 8.222928] Port 0 speed status: 0x00000002
  168. [ 8.227608] Port 1 speed status: 0x00000002
  169. [ 8.232258] Port 2 speed status: 0x00000002
  170. [ 8.236933] Port 3 speed status: 0x00000002
  171. [ 8.241579] Port 4 speed status: 0x00000002
  172. [ 8.246222] Port 5 speed status: 0x00000002
  173. [ 8.250893] Port 6 speed status: 0x00000002
  174. [ 8.255544] Port 7 speed status: 0x00000002
  175. [ 8.260234] rtl83xx-switch switch@1b000000 lan1: configuring for phy/usxgmii link mode
  176. [ 8.269092] rtl93xx_phylink_mac_config port 0, mode 0, phy-mode usxgmii, speed -1, link 0
  177. [ 8.278230] rtl93xx_phylink_mac_config SDS is 2
  178. [ 8.283270] rtl93xx_phylink_mac_config: Configuring port 0 SDS 2 for USXGMII
  179. [ 8.291129] rtl9300_serdes_setup: port 0, sds 2, mode usxgmii (30)
  180. [ 8.298037] rtl9300_sds_rst 30
  181. [ 8.321406] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 2
  182. [ 8.387588] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  183. [ 8.394598] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  184. [ 8.402396] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  185. [ 8.409521] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  186. [ 8.417251] rtl9300_phy_enable_10g_1g set medium: 00000002
  187. [ 8.424361] rtl9300_phy_enable_10g_1g set medium after: 00000002
  188. [ 8.433068] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  189. [ 8.445122] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  190. [ 8.453096] rtl9300_force_sds_mode: SDS: 2, mode 30
  191. [ 8.458558] rtl9300_force_sds_mode: serdes 2 forcing to d
  192. [ 8.470578] Configuring USXGMII for independent operation on SDS 2
  193. [ 8.506438] rtl9300_force_sds_mode: serdes 2 forced to d DONE
  194. [ 8.512868] start_1.1.1 initial value for sds 2
  195. [ 8.518926] Before calibration - SDS 2 coupling: 0x051f
  196. [ 8.524739] start_1.1.1 initial value for sds 2
  197. [ 8.586756] end_1.1.1 --
  198. [ 8.589616] start_1.1.2 Load DFE init. value
  199. [ 8.596354] end_1.1.2
  200. [ 8.598900] start_1.1.3 disable LEQ training,enable DFE clock
  201. [ 8.617296] end_1.1.3 --
  202. [ 8.620111] start_1.1.4 offset cali setting
  203. [ 8.626750] end_1.1.4
  204. [ 8.629296] start_1.1.5 LEQ and DFE setting
  205. [ 8.647949] end_1.1.5
  206. [ 8.659476] start_1.2.1 ForegroundOffsetCal_Manual
  207. [ 8.668832] end_1.2.1
  208. [ 8.679838] start_1.2.3 Foreground Calibration
  209. [ 8.698310] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  210. [ 8.706988] rtl9300_do_rx_calibration_2_3: end_1.2.3
  211. [ 8.712509] start_1.4.1
  212. [ 8.936068] end_1.4.1
  213. [ 8.938819] start_1.4.2
  214. [ 8.951350] vth_set_bin = 3
  215. [ 8.954074] vth_set_bin = 3
  216. [ 8.958198] Vth Maunal = 0
  217. [ 9.077103] Tap0 Sign : +
  218. [ 9.080113] tap0_coef_bin = 19
  219. [ 9.084015] tap0 manual = 0
  220. [ 9.093413] end_1.4.2
  221. [ 9.118512] After calibration - SDS 2 coupling: 0x051f
  222. [ 9.126737] Forcing SerDes 2 coupling bits to independent mode
  223. [ 9.138248] Final SDS 2 coupling reg 0x20.18: 0x053f (should be 0x053f)
  224. [ 9.149629] USXGMII final coupling check for SDS 2:
  225. [ 9.156050] Reg 0x20.18: 0x053f
  226. [ 9.160758] Reg 0x21.11: 0x000f
  227. [ 9.165440] SDS 2 force mode register: 0xd
  228. [ 9.170019] SDS 2 mode select register: 0x1e
  229. [ 9.175762] SDS 2 lane coupling reg 0x20.18: 0x053f
  230. [ 9.182208] SDS 2 analog coupling reg 0x21.11: 0x000f
  231. [ 9.189043] 8021q: adding VLAN 0 to HW filter on device lan1
  232. [ 9.195627] rtl838x-eth 1b00a300.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
  233. [ 9.225023] rtl83xx-switch switch@1b000000 lan1: Link is Up - 1Gbps/Full - flow control off
  234. [ 9.234553] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  235. [ 9.242006] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  236. [ 9.257945] rtl83xx_fib_event_work_do: FIB4 failed
  237. [ 9.263312] rtl83xx_fib_event_work_do: FIB4 failed
  238. [ 9.268766] rtl83xx_fib_event_work_do: FIB4 failed
  239.  
  240. Press the [f] key and hit [enter] to enter failsafe mode
  241. Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level
  242. [ 10.416934] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  243. [ 13.487030] rtl83xx_fib4_del: no such gateway: 0.0.0.0
  244. [ 13.492800] rtl83xx_fib4_del: no such gateway: 0.0.0.0
  245. [ 13.503219] rtl83xx-switch switch@1b000000 lan1: Link is Down
  246. [ 13.524208] procd: - early -
  247. [ 13.527590] rtl83xx_fib4_del: no such gateway: 0.0.0.0
  248. [ 13.533818] procd: - watchdog -
  249. [ 14.187956] procd: - watchdog -
  250. [ 14.192030] procd: - ubus -
  251. [ 14.252099] procd: - init -
  252. Please press Enter to activate this console.
  253. [ 15.123980] kmodloader: loading kernel modules from /etc/modules.d/*
  254. [ 15.307949] kmodloader: done loading kernel modules from /etc/modules.d/*
  255. [ 16.760635] urngd: v1.0.2 started.
  256. [ 20.376384] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  257. [ 30.830432] in rtl838x_eth_stop
  258. [ 30.834102] rtl838x-eth 1b00a300.ethernet eth0: Link is Down
  259. [ 31.366284] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  260. [ 31.373697] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  261. [ 31.381095] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  262. [ 31.388472] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  263. [ 31.607885] RESETTING 9300, CPU_PORT 28
  264. [ 31.812735] rtl838x-eth 1b00a300.ethernet eth0: configuring for fixed/internal link mode
  265. [ 31.821739] In rtl838x_mac_config, mode 1
  266. [ 31.835958] rtl838x-eth 1b00a300.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
  267. [ 31.851998] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  268. [ 31.859468] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  269. [ 32.033925] Setting up RTL9300 port isolation for independent operation
  270. [ 32.041404] Port 0: traffic matrix set to 0x1fffffef
  271. [ 32.047004] Port 1: traffic matrix set to 0x1fffffdf
  272. [ 32.052530] Port 2: traffic matrix set to 0x1fffffbf
  273. [ 32.058084] Port 3: traffic matrix set to 0x1fffff7f
  274. [ 32.063607] Port 4: traffic matrix set to 0x1ffffffe
  275. [ 32.069156] Port 5: traffic matrix set to 0x1ffffffd
  276. [ 32.074684] Port 6: traffic matrix set to 0x1ffffffb
  277. [ 32.080233] Port 7: traffic matrix set to 0x1ffffff7
  278. [ 32.085760] Port 8: traffic matrix set to 0x1fffffff
  279. [ 32.091309] Port 9: traffic matrix set to 0x1fffffff
  280. [ 32.096837] Port 10: traffic matrix set to 0x1fffffff
  281. [ 32.102511] Port 11: traffic matrix set to 0x1fffffff
  282. [ 32.108179] Port 12: traffic matrix set to 0x1fffffff
  283. [ 32.113804] Port 13: traffic matrix set to 0x1fffffff
  284. [ 32.119450] Port 14: traffic matrix set to 0x1fffffff
  285. [ 32.125074] Port 15: traffic matrix set to 0x1fffffff
  286. [ 32.130719] Port 16: traffic matrix set to 0x1fffffff
  287. [ 32.136343] Port 17: traffic matrix set to 0x1fffffff
  288. [ 32.141990] Port 18: traffic matrix set to 0x1fffffff
  289. [ 32.147660] Port 19: traffic matrix set to 0x1fffffff
  290. [ 32.153284] Port 20: traffic matrix set to 0x1fffffff
  291. [ 32.158934] Port 21: traffic matrix set to 0x1fffffff
  292. [ 32.164554] Port 22: traffic matrix set to 0x1fffffff
  293. [ 32.170199] Port 23: traffic matrix set to 0x1fffffff
  294. [ 32.175824] Port 24: traffic matrix set to 0x1fffffff
  295. [ 32.181468] Port 25: traffic matrix set to 0x1fffffff
  296. [ 32.187130] Port 26: traffic matrix set to 0x1fffffff
  297. [ 32.192754] Port 27: traffic matrix set to 0x1fffffff
  298. [ 32.198398] CPU port 28: traffic matrix set to 0xfffffff
  299. [ 32.204311] === Port Pairing Debug ===
  300. [ 32.208510] Port 0 traffic matrix: 0x1fffffef
  301. [ 32.213362] Port 1 traffic matrix: 0x1fffffdf
  302. [ 32.218235] Port 2 traffic matrix: 0x1fffffbf
  303. [ 32.223086] Port 3 traffic matrix: 0x1fffff7f
  304. [ 32.227984] Port 4 traffic matrix: 0x1ffffffe
  305. [ 32.232838] Port 5 traffic matrix: 0x1ffffffd
  306. [ 32.237734] Port 6 traffic matrix: 0x1ffffffb
  307. [ 32.242590] Port 7 traffic matrix: 0x1ffffff7
  308. [ 32.247469] Port 8 traffic matrix: 0x1fffffff
  309. [ 32.252318] === MAC Configuration Debug ===
  310. [ 32.257003] Port 0: MAC_CTRL=0x00000030, FORCE_MODE=0x00000014
  311. [ 32.263496] Port 1: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  312. [ 32.270013] Port 2: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  313. [ 32.276504] Port 3: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  314. [ 32.283015] Port 4: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  315. [ 32.289536] Port 5: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  316. [ 32.296024] Port 6: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  317. [ 32.302536] Port 7: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  318. [ 32.309056] Port isolation control registers:
  319. [ 32.313903] Port 0 VLAN_PB: 0x00000000
  320. [ 32.318096] Port 1 VLAN_PB: 0x00000000
  321. [ 32.322268] Port 2 VLAN_PB: 0x00000000
  322. [ 32.326427] Port 3 VLAN_PB: 0x00000000
  323. [ 32.330622] Port 4 VLAN_PB: 0x00000000
  324. [ 32.334792] Port 5 VLAN_PB: 0x00000000
  325. [ 32.338986] Port 6 VLAN_PB: 0x00000000
  326. [ 32.343157] Port 7 VLAN_PB: 0x00000000
  327. [ 32.347351] === Trunk/LAG Configuration Debug ===
  328. [ 32.352587] Trunk mode control: 0x00000000
  329. [ 32.357164] === Special Configuration Debug ===
  330. [ 32.362203] Mirror control: 0x00000000
  331. [ 32.366365] === PHY Polling Debug ===
  332. [ 32.370470] PHY polling control: 0x0f110101
  333. [ 32.375123] Port 0: PHY polling ENABLED
  334. [ 32.379420] Port 8: PHY polling ENABLED
  335. [ 32.383690] Port 16: PHY polling ENABLED
  336. [ 32.388078] Port 20: PHY polling ENABLED
  337. [ 32.392440] Port 24: PHY polling ENABLED
  338. [ 32.396793] Port 25: PHY polling ENABLED
  339. [ 32.401182] Port 26: PHY polling ENABLED
  340. [ 32.405545] Port 27: PHY polling ENABLED
  341. [ 32.409932] Port 0 SMI config: 0x00000000
  342. [ 32.414393] Port 1 SMI config: 0x00000400
  343. [ 32.418900] Port 2 SMI config: 0x00200000
  344. [ 32.423363] Port 3 SMI config: 0x00000c00
  345. [ 32.427855] Port 4 SMI config: 0x00018820
  346. [ 32.432315] Port 5 SMI config: 0x00000000
  347. [ 32.436765] Port 6 SMI config: 0x00f00000
  348. [ 32.441249] Port 7 SMI config: 0x00000000
  349. [ 32.445709] Setting up PHY polling for all ports
  350. [ 32.450881] PHY polling mask set to: 0x0f110101
  351. [ 32.455926] === Direct Link Status Debug ===
  352. [ 32.460706] MAC_LINK_STS register: 0x01000001
  353. [ 32.465554] Port 0: Link UP (bit 0 set)
  354. [ 32.469846] Port 24: Link UP (bit 24 set) - PHANTOM!
  355. [ 32.475368] Port 0 speed status: 0x00000002
  356. [ 32.480054] Port 1 speed status: 0x00000002
  357. [ 32.484706] Port 2 speed status: 0x00000002
  358. [ 32.489388] Port 3 speed status: 0x00000002
  359. [ 32.494045] Port 4 speed status: 0x00000002
  360. [ 32.498721] Port 5 speed status: 0x00000002
  361. [ 32.503375] Port 6 speed status: 0x00000002
  362. [ 32.508051] Port 7 speed status: 0x00000002
  363. [ 32.512725] rtl83xx-switch switch@1b000000 lan1: configuring for phy/usxgmii link mode
  364. [ 32.521574] rtl93xx_phylink_mac_config port 0, mode 0, phy-mode usxgmii, speed -1, link 0
  365. [ 32.530719] rtl93xx_phylink_mac_config SDS is 2
  366. [ 32.535755] rtl93xx_phylink_mac_config: Configuring port 0 SDS 2 for USXGMII
  367. [ 32.543619] rtl9300_serdes_setup: port 0, sds 2, mode usxgmii (30)
  368. [ 32.550534] rtl9300_sds_rst 30
  369. [ 32.573912] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 2
  370. [ 32.640121] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  371. [ 32.647169] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  372. [ 32.654946] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  373. [ 32.662086] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  374. [ 32.669810] rtl9300_phy_enable_10g_1g set medium: 00000002
  375. [ 32.676946] rtl9300_phy_enable_10g_1g set medium after: 00000002
  376. [ 32.685629] rtl9300_serdes_mac_link_config: registers before 00000000 00001a03
  377. [ 32.697704] rtl9300_serdes_mac_link_config: registers after 00000000 00001803
  378. [ 32.705656] rtl9300_force_sds_mode: SDS: 2, mode 30
  379. [ 32.711109] rtl9300_force_sds_mode: serdes 2 forcing to d
  380. [ 32.723136] Configuring USXGMII for independent operation on SDS 2
  381. [ 32.759009] rtl9300_force_sds_mode: serdes 2 forced to d DONE
  382. [ 32.765410] start_1.1.1 initial value for sds 2
  383. [ 32.771471] Before calibration - SDS 2 coupling: 0x051f
  384. [ 32.777319] start_1.1.1 initial value for sds 2
  385. [ 32.839320] end_1.1.1 --
  386. [ 32.842140] start_1.1.2 Load DFE init. value
  387. [ 32.848919] end_1.1.2
  388. [ 32.851450] start_1.1.3 disable LEQ training,enable DFE clock
  389. [ 32.869871] end_1.1.3 --
  390. [ 32.872693] start_1.1.4 offset cali setting
  391. [ 32.879370] end_1.1.4
  392. [ 32.881898] start_1.1.5 LEQ and DFE setting
  393. [ 32.900561] end_1.1.5
  394. [ 32.912107] start_1.2.1 ForegroundOffsetCal_Manual
  395. [ 32.921469] end_1.2.1
  396. [ 32.932477] start_1.2.3 Foreground Calibration
  397. [ 32.950957] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  398. [ 32.959642] rtl9300_do_rx_calibration_2_3: end_1.2.3
  399. [ 32.965167] start_1.4.1
  400. [ 33.188761] end_1.4.1
  401. [ 33.191488] start_1.4.2
  402. [ 33.204013] vth_set_bin = 3
  403. [ 33.206733] vth_set_bin = 3
  404. [ 33.210863] Vth Maunal = 0
  405. [ 33.329783] Tap0 Sign : +
  406. [ 33.332800] tap0_coef_bin = 20
  407. [ 33.336700] tap0 manual = 0
  408. [ 33.346104] end_1.4.2
  409. [ 33.371217] After calibration - SDS 2 coupling: 0x051f
  410. [ 33.379479] Forcing SerDes 2 coupling bits to independent mode
  411. [ 33.390989] Final SDS 2 coupling reg 0x20.18: 0x053f (should be 0x053f)
  412. [ 33.402379] USXGMII final coupling check for SDS 2:
  413. [ 33.408840] Reg 0x20.18: 0x053f
  414. [ 33.413526] Reg 0x21.11: 0x000f
  415. [ 33.418230] SDS 2 force mode register: 0xd
  416. [ 33.422790] SDS 2 mode select register: 0x1e
  417. [ 33.428563] SDS 2 lane coupling reg 0x20.18: 0x053f
  418. [ 33.434987] SDS 2 analog coupling reg 0x21.11: 0x000f
  419. [ 33.442829] 8021q: adding VLAN 0 to HW filter on device lan1
  420. [ 33.488723] rtl83xx-switch switch@1b000000 lan1: Link is Up - 1Gbps/Full - flow control off
  421. [ 33.533480] switch: port 1(lan1) entered blocking state
  422. [ 33.539406] switch: port 1(lan1) entered disabled state
  423. [ 33.545281] rtl83xx-switch switch@1b000000 lan1: entered allmulticast mode
  424. [ 33.553017] rtl838x-eth 1b00a300.ethernet eth0: entered allmulticast mode
  425. [ 33.561548] rtl83xx-switch switch@1b000000 lan1: entered promiscuous mode
  426. [ 33.596182] switch: port 1(lan1) entered blocking state
  427. [ 33.602110] switch: port 1(lan1) entered forwarding state
  428. [ 33.817032] Setting up RTL9300 port isolation for independent operation
  429. [ 33.824422] Port 0: traffic matrix set to 0x1fffffef
  430. [ 33.830018] Port 1: traffic matrix set to 0x1fffffdf
  431. [ 33.835546] Port 2: traffic matrix set to 0x1fffffbf
  432. [ 33.841099] Port 3: traffic matrix set to 0x1fffff7f
  433. [ 33.846622] Port 4: traffic matrix set to 0x1ffffffe
  434. [ 33.852172] Port 5: traffic matrix set to 0x1ffffffd
  435. [ 33.857740] Port 6: traffic matrix set to 0x1ffffffb
  436. [ 33.863264] Port 7: traffic matrix set to 0x1ffffff7
  437. [ 33.868825] Port 8: traffic matrix set to 0x1fffffff
  438. [ 33.874349] Port 9: traffic matrix set to 0x1fffffff
  439. [ 33.879904] Port 10: traffic matrix set to 0x1fffffff
  440. [ 33.885523] Port 11: traffic matrix set to 0x1fffffff
  441. [ 33.891168] Port 12: traffic matrix set to 0x1fffffff
  442. [ 33.896793] Port 13: traffic matrix set to 0x1fffffff
  443. [ 33.902437] Port 14: traffic matrix set to 0x1fffffff
  444. [ 33.908110] Port 15: traffic matrix set to 0x1fffffff
  445. [ 33.913733] Port 16: traffic matrix set to 0x1fffffff
  446. [ 33.919397] Port 17: traffic matrix set to 0x1fffffff
  447. [ 33.925020] Port 18: traffic matrix set to 0x1fffffff
  448. [ 33.930672] Port 19: traffic matrix set to 0x1fffffff
  449. [ 33.936299] Port 20: traffic matrix set to 0x1fffffff
  450. [ 33.941944] Port 21: traffic matrix set to 0x1fffffff
  451. [ 33.947606] Port 22: traffic matrix set to 0x1fffffff
  452. [ 33.953230] Port 23: traffic matrix set to 0x1fffffff
  453. [ 33.958875] Port 24: traffic matrix set to 0x1fffffff
  454. [ 33.964500] Port 25: traffic matrix set to 0x1fffffff
  455. [ 33.970144] Port 26: traffic matrix set to 0x1fffffff
  456. [ 33.975770] Port 27: traffic matrix set to 0x1fffffff
  457. [ 33.981413] CPU port 28: traffic matrix set to 0xfffffff
  458. [ 33.987361] === Port Pairing Debug ===
  459. [ 33.991534] Port 0 traffic matrix: 0x1fffffef
  460. [ 33.996367] Port 1 traffic matrix: 0x1fffffdf
  461. [ 34.001241] Port 2 traffic matrix: 0x1fffffbf
  462. [ 34.006093] Port 3 traffic matrix: 0x1fffff7f
  463. [ 34.010985] Port 4 traffic matrix: 0x1ffffffe
  464. [ 34.015836] Port 5 traffic matrix: 0x1ffffffd
  465. [ 34.020730] Port 6 traffic matrix: 0x1ffffffb
  466. [ 34.025579] Port 7 traffic matrix: 0x1ffffff7
  467. [ 34.030457] Port 8 traffic matrix: 0x1fffffff
  468. [ 34.035308] === MAC Configuration Debug ===
  469. [ 34.039983] Port 0: MAC_CTRL=0x00000033, FORCE_MODE=0x00000016
  470. [ 34.046475] Port 1: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  471. [ 34.052989] Port 2: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  472. [ 34.059509] Port 3: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  473. [ 34.065996] Port 4: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  474. [ 34.072509] Port 5: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  475. [ 34.079030] Port 6: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  476. [ 34.085516] Port 7: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  477. [ 34.092029] Port isolation control registers:
  478. [ 34.096908] Port 0 VLAN_PB: 0x00010004
  479. [ 34.101079] Port 1 VLAN_PB: 0x00000000
  480. [ 34.105238] Port 2 VLAN_PB: 0x00000000
  481. [ 34.109433] Port 3 VLAN_PB: 0x00000000
  482. [ 34.113603] Port 4 VLAN_PB: 0x00000000
  483. [ 34.117798] Port 5 VLAN_PB: 0x00000000
  484. [ 34.121968] Port 6 VLAN_PB: 0x00000000
  485. [ 34.126128] Port 7 VLAN_PB: 0x00000000
  486. [ 34.130336] === Trunk/LAG Configuration Debug ===
  487. [ 34.135576] Trunk mode control: 0x00000000
  488. [ 34.140158] === Special Configuration Debug ===
  489. [ 34.145192] Mirror control: 0x00000000
  490. [ 34.149386] === PHY Polling Debug ===
  491. [ 34.153460] PHY polling control: 0x0f110101
  492. [ 34.158137] Port 0: PHY polling ENABLED
  493. [ 34.162404] Port 8: PHY polling ENABLED
  494. [ 34.166661] Port 16: PHY polling ENABLED
  495. [ 34.171049] Port 20: PHY polling ENABLED
  496. [ 34.175411] Port 24: PHY polling ENABLED
  497. [ 34.179799] Port 25: PHY polling ENABLED
  498. [ 34.184162] Port 26: PHY polling ENABLED
  499. [ 34.188549] Port 27: PHY polling ENABLED
  500. [ 34.192914] Port 0 SMI config: 0x00000000
  501. [ 34.197398] Port 1 SMI config: 0x00000400
  502. [ 34.201858] Port 2 SMI config: 0x00200000
  503. [ 34.206307] Port 3 SMI config: 0x00000c00
  504. [ 34.210808] Port 4 SMI config: 0x00018820
  505. [ 34.215269] Port 5 SMI config: 0x00000000
  506. [ 34.219759] Port 6 SMI config: 0x00f00000
  507. [ 34.224222] Port 7 SMI config: 0x00000000
  508. [ 34.228705] Setting up PHY polling for all ports
  509. [ 34.233841] PHY polling mask set to: 0x0f110101
  510. [ 34.238912] === Direct Link Status Debug ===
  511. [ 34.243663] MAC_LINK_STS register: 0x11000001
  512. [ 34.248538] Port 0: Link UP (bit 0 set)
  513. [ 34.252800] Port 24: Link UP (bit 24 set) - PHANTOM!
  514. [ 34.258346] Port 28: Link UP (bit 28 set) - PHANTOM!
  515. [ 34.263868] Port 0 speed status: 0x00000002
  516. [ 34.268546] Port 1 speed status: 0x00000002
  517. [ 34.273198] Port 2 speed status: 0x00000002
  518. [ 34.277875] Port 3 speed status: 0x00000002
  519. [ 34.282528] Port 4 speed status: 0x00000002
  520. [ 34.287206] Port 5 speed status: 0x00000002
  521. [ 34.291858] Port 6 speed status: 0x00000002
  522. [ 34.296501] Port 7 speed status: 0x00000002
  523. [ 34.301199] rtl83xx-switch switch@1b000000 lan2: configuring for phy/usxgmii link mode
  524. [ 34.310065] rtl93xx_phylink_mac_config port 8, mode 0, phy-mode usxgmii, speed -1, link 0
  525. [ 34.319202] rtl93xx_phylink_mac_config SDS is 3
  526. [ 34.324237] rtl93xx_phylink_mac_config: Configuring port 8 SDS 3 for USXGMII
  527. [ 34.332101] rtl9300_serdes_setup: port 8, sds 3, mode usxgmii (30)
  528. [ 34.339030] rtl9300_sds_rst 30
  529. [ 34.362433] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 3
  530. [ 34.428616] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  531. [ 34.435626] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  532. [ 34.443430] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  533. [ 34.450564] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  534. [ 34.458289] rtl9300_phy_enable_10g_1g set medium: 00000002
  535. [ 34.465388] rtl9300_phy_enable_10g_1g set medium after: 00000002
  536. [ 34.474100] rtl9300_serdes_mac_link_config: registers before 00000000 00001203
  537. [ 34.486164] rtl9300_serdes_mac_link_config: registers after 00000000 00001003
  538. [ 34.494137] rtl9300_force_sds_mode: SDS: 3, mode 30
  539. [ 34.499624] rtl9300_force_sds_mode: serdes 3 forcing to d
  540. [ 34.511663] Configuring USXGMII for independent operation on SDS 3
  541. [ 34.547546] rtl9300_force_sds_mode: serdes 3 forced to d DONE
  542. [ 34.553946] start_1.1.1 initial value for sds 3
  543. [ 34.560012] Before calibration - SDS 3 coupling: 0x051f
  544. [ 34.565828] start_1.1.1 initial value for sds 3
  545. [ 34.627868] end_1.1.1 --
  546. [ 34.630693] start_1.1.2 Load DFE init. value
  547. [ 34.637459] end_1.1.2
  548. [ 34.639988] start_1.1.3 disable LEQ training,enable DFE clock
  549. [ 34.658391] end_1.1.3 --
  550. [ 34.661211] start_1.1.4 offset cali setting
  551. [ 34.667883] end_1.1.4
  552. [ 34.670409] start_1.1.5 LEQ and DFE setting
  553. [ 34.689076] end_1.1.5
  554. [ 34.700613] start_1.2.1 ForegroundOffsetCal_Manual
  555. [ 34.709971] end_1.2.1
  556. [ 34.720973] start_1.2.3 Foreground Calibration
  557. [ 34.739458] rtl9300_do_rx_calibration_2_3: fgcal_gray: 18, fgcal_binary 27
  558. [ 34.748145] rtl9300_do_rx_calibration_2_3: end_1.2.3
  559. [ 34.753668] start_1.4.1
  560. [ 34.977287] end_1.4.1
  561. [ 34.980015] start_1.4.2
  562. [ 34.992541] vth_set_bin = 3
  563. [ 34.995260] vth_set_bin = 3
  564. [ 34.999390] Vth Maunal = 0
  565. [ 35.118302] Tap0 Sign : +
  566. [ 35.121317] tap0_coef_bin = 16
  567. [ 35.125219] tap0 manual = 0
  568. [ 35.134625] end_1.4.2
  569. [ 35.159721] After calibration - SDS 3 coupling: 0x051f
  570. [ 35.167980] Forcing SerDes 3 coupling bits to independent mode
  571. [ 35.179504] Final SDS 3 coupling reg 0x20.18: 0x053f (should be 0x053f)
  572. [ 35.190902] USXGMII final coupling check for SDS 3:
  573. [ 35.197355] Reg 0x20.18: 0x053f
  574. [ 35.202038] Reg 0x21.11: 0x000f
  575. [ 35.206714] SDS 3 force mode register: 0xd
  576. [ 35.211299] SDS 3 mode select register: 0x1e
  577. [ 35.217078] SDS 3 lane coupling reg 0x20.18: 0x053f
  578. [ 35.223507] SDS 3 analog coupling reg 0x21.11: 0x000f
  579. [ 35.230349] 8021q: adding VLAN 0 to HW filter on device lan2
  580. [ 35.265928] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  581. [ 35.273388] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  582. [ 35.300129] rtl83xx-switch switch@1b000000 lan2: Link is Up - 1Gbps/Full - flow control off
  583. [ 35.612097] switch: port 2(lan2) entered blocking state
  584. [ 35.618026] switch: port 2(lan2) entered disabled state
  585. [ 35.623897] rtl83xx-switch switch@1b000000 lan2: entered allmulticast mode
  586. [ 35.697741] rtl83xx-switch switch@1b000000 lan2: entered promiscuous mode
  587. [ 35.705662] switch: port 2(lan2) entered blocking state
  588. [ 35.711598] switch: port 2(lan2) entered forwarding state
  589. [ 35.938871] Setting up RTL9300 port isolation for independent operation
  590. [ 35.946261] Port 0: traffic matrix set to 0x1fffffef
  591. [ 35.951874] Port 1: traffic matrix set to 0x1fffffdf
  592. [ 35.957445] Port 2: traffic matrix set to 0x1fffffbf
  593. [ 35.962976] Port 3: traffic matrix set to 0x1fffff7f
  594. [ 35.968525] Port 4: traffic matrix set to 0x1ffffffe
  595. [ 35.974052] Port 5: traffic matrix set to 0x1ffffffd
  596. [ 35.979601] Port 6: traffic matrix set to 0x1ffffffb
  597. [ 35.985130] Port 7: traffic matrix set to 0x1ffffff7
  598. [ 35.990678] Port 8: traffic matrix set to 0x1fffffff
  599. [ 35.996206] Port 9: traffic matrix set to 0x1fffffff
  600. [ 36.001767] Port 10: traffic matrix set to 0x1fffffff
  601. [ 36.007430] Port 11: traffic matrix set to 0x1fffffff
  602. [ 36.013049] Port 12: traffic matrix set to 0x1fffffff
  603. [ 36.018699] Port 13: traffic matrix set to 0x1fffffff
  604. [ 36.024320] Port 14: traffic matrix set to 0x1fffffff
  605. [ 36.029965] Port 15: traffic matrix set to 0x1fffffff
  606. [ 36.035589] Port 16: traffic matrix set to 0x1fffffff
  607. [ 36.041234] Port 17: traffic matrix set to 0x1fffffff
  608. [ 36.046896] Port 18: traffic matrix set to 0x1fffffff
  609. [ 36.052520] Port 19: traffic matrix set to 0x1fffffff
  610. [ 36.058165] Port 20: traffic matrix set to 0x1fffffff
  611. [ 36.063790] Port 21: traffic matrix set to 0x1fffffff
  612. [ 36.069435] Port 22: traffic matrix set to 0x1fffffff
  613. [ 36.075060] Port 23: traffic matrix set to 0x1fffffff
  614. [ 36.080706] Port 24: traffic matrix set to 0x1fffffff
  615. [ 36.086330] Port 25: traffic matrix set to 0x1fffffff
  616. [ 36.091975] Port 26: traffic matrix set to 0x1fffffff
  617. [ 36.097636] Port 27: traffic matrix set to 0x1fffffff
  618. [ 36.103260] CPU port 28: traffic matrix set to 0xfffffff
  619. [ 36.109202] === Port Pairing Debug ===
  620. [ 36.113373] Port 0 traffic matrix: 0x1fffffef
  621. [ 36.118258] Port 1 traffic matrix: 0x1fffffdf
  622. [ 36.123104] Port 2 traffic matrix: 0x1fffffbf
  623. [ 36.127977] Port 3 traffic matrix: 0x1fffff7f
  624. [ 36.132830] Port 4 traffic matrix: 0x1ffffffe
  625. [ 36.137703] Port 5 traffic matrix: 0x1ffffffd
  626. [ 36.142555] Port 6 traffic matrix: 0x1ffffffb
  627. [ 36.147428] Port 7 traffic matrix: 0x1ffffff7
  628. [ 36.152280] Port 8 traffic matrix: 0x1fffffff
  629. [ 36.157156] === MAC Configuration Debug ===
  630. [ 36.161813] Port 0: MAC_CTRL=0x00000033, FORCE_MODE=0x00000016
  631. [ 36.168325] Port 1: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  632. [ 36.174810] Port 2: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  633. [ 36.181322] Port 3: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  634. [ 36.187843] Port 4: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  635. [ 36.194330] Port 5: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  636. [ 36.200843] Port 6: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  637. [ 36.207365] Port 7: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  638. [ 36.213850] Port isolation control registers:
  639. [ 36.218730] Port 0 VLAN_PB: 0x00010004
  640. [ 36.222900] Port 1 VLAN_PB: 0x00000000
  641. [ 36.227099] Port 2 VLAN_PB: 0x00000000
  642. [ 36.231265] Port 3 VLAN_PB: 0x00000000
  643. [ 36.235424] Port 4 VLAN_PB: 0x00000000
  644. [ 36.239619] Port 5 VLAN_PB: 0x00000000
  645. [ 36.243789] Port 6 VLAN_PB: 0x00000000
  646. [ 36.247984] Port 7 VLAN_PB: 0x00000000
  647. [ 36.252154] === Trunk/LAG Configuration Debug ===
  648. [ 36.257438] Trunk mode control: 0x00000000
  649. [ 36.262030] === Special Configuration Debug ===
  650. [ 36.267104] Mirror control: 0x00000000
  651. [ 36.271272] === PHY Polling Debug ===
  652. [ 36.275335] PHY polling control: 0x0f110101
  653. [ 36.280030] Port 0: PHY polling ENABLED
  654. [ 36.284296] Port 8: PHY polling ENABLED
  655. [ 36.288595] Port 16: PHY polling ENABLED
  656. [ 36.292959] Port 20: PHY polling ENABLED
  657. [ 36.297346] Port 24: PHY polling ENABLED
  658. [ 36.301710] Port 25: PHY polling ENABLED
  659. [ 36.306063] Port 26: PHY polling ENABLED
  660. [ 36.310450] Port 27: PHY polling ENABLED
  661. [ 36.314815] Port 0 SMI config: 0x00000000
  662. [ 36.319297] Port 1 SMI config: 0x00000400
  663. [ 36.323759] Port 2 SMI config: 0x00200000
  664. [ 36.328252] Port 3 SMI config: 0x00000c00
  665. [ 36.332711] Port 4 SMI config: 0x00018820
  666. [ 36.337213] Port 5 SMI config: 0x00000000
  667. [ 36.341673] Port 6 SMI config: 0x00f00000
  668. [ 36.346122] Port 7 SMI config: 0x00000000
  669. [ 36.350610] Setting up PHY polling for all ports
  670. [ 36.355742] PHY polling mask set to: 0x0f110101
  671. [ 36.360806] === Direct Link Status Debug ===
  672. [ 36.365554] MAC_LINK_STS register: 0x11000001
  673. [ 36.370425] Port 0: Link UP (bit 0 set)
  674. [ 36.374691] Port 24: Link UP (bit 24 set) - PHANTOM!
  675. [ 36.380238] Port 28: Link UP (bit 28 set) - PHANTOM!
  676. [ 36.385761] Port 0 speed status: 0x00000002
  677. [ 36.390437] Port 1 speed status: 0x00000002
  678. [ 36.395090] Port 2 speed status: 0x00000002
  679. [ 36.399767] Port 3 speed status: 0x00000002
  680. [ 36.404420] Port 4 speed status: 0x00000002
  681. [ 36.409096] Port 5 speed status: 0x00000002
  682. [ 36.413750] Port 6 speed status: 0x00000002
  683. [ 36.418426] Port 7 speed status: 0x00000002
  684. [ 36.423100] rtl83xx-switch switch@1b000000 lan3: configuring for phy/usxgmii link mode
  685. [ 36.431950] rtl93xx_phylink_mac_config port 16, mode 0, phy-mode usxgmii, speed -1, link 0
  686. [ 36.441199] rtl93xx_phylink_mac_config SDS is 4
  687. [ 36.446244] rtl93xx_phylink_mac_config: Configuring port 16 SDS 4 for USXGMII
  688. [ 36.454209] rtl9300_serdes_setup: port 16, sds 4, mode usxgmii (30)
  689. [ 36.461216] rtl9300_sds_rst 30
  690. [ 36.484595] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 4
  691. [ 36.550794] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  692. [ 36.557846] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  693. [ 36.565629] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  694. [ 36.572755] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  695. [ 36.580480] rtl9300_phy_enable_10g_1g set medium: 00000002
  696. [ 36.587614] rtl9300_phy_enable_10g_1g set medium after: 00000002
  697. [ 36.596293] rtl9300_serdes_mac_link_config: registers before 00000000 00001203
  698. [ 36.608361] rtl9300_serdes_mac_link_config: registers after 00000000 00001003
  699. [ 36.616302] rtl9300_force_sds_mode: SDS: 4, mode 30
  700. [ 36.621753] rtl9300_force_sds_mode: serdes 4 forcing to d
  701. [ 36.633784] Configuring USXGMII for independent operation on SDS 4
  702. [ 36.669671] rtl9300_force_sds_mode: serdes 4 forced to d DONE
  703. [ 36.676075] start_1.1.1 initial value for sds 4
  704. [ 36.682136] Before calibration - SDS 4 coupling: 0x051f
  705. [ 36.687983] start_1.1.1 initial value for sds 4
  706. [ 36.749967] end_1.1.1 --
  707. [ 36.752786] start_1.1.2 Load DFE init. value
  708. [ 36.759556] end_1.1.2
  709. [ 36.762080] start_1.1.3 disable LEQ training,enable DFE clock
  710. [ 36.780499] end_1.1.3 --
  711. [ 36.783322] start_1.1.4 offset cali setting
  712. [ 36.789995] end_1.1.4
  713. [ 36.792519] start_1.1.5 LEQ and DFE setting
  714. [ 36.811180] end_1.1.5
  715. [ 36.822716] start_1.2.1 ForegroundOffsetCal_Manual
  716. [ 36.832072] end_1.2.1
  717. [ 36.843071] start_1.2.3 Foreground Calibration
  718. [ 36.861552] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 28
  719. [ 36.870236] rtl9300_do_rx_calibration_2_3: end_1.2.3
  720. [ 36.875761] start_1.4.1
  721. [ 37.099375] end_1.4.1
  722. [ 37.102100] start_1.4.2
  723. [ 37.114629] vth_set_bin = 7
  724. [ 37.117383] vth_set_bin = 7
  725. [ 37.121484] Vth Maunal = 0
  726. [ 37.240377] Tap0 Sign : +
  727. [ 37.243393] tap0_coef_bin = 16
  728. [ 37.247327] tap0 manual = 0
  729. [ 37.256708] end_1.4.2
  730. [ 37.281797] After calibration - SDS 4 coupling: 0x051f
  731. [ 37.290056] Forcing SerDes 4 coupling bits to independent mode
  732. [ 37.301567] Final SDS 4 coupling reg 0x20.18: 0x053f (should be 0x053f)
  733. [ 37.312955] USXGMII final coupling check for SDS 4:
  734. [ 37.319417] Reg 0x20.18: 0x053f
  735. [ 37.324104] Reg 0x21.11: 0x000f
  736. [ 37.328812] SDS 4 force mode register: 0xd
  737. [ 37.333367] SDS 4 mode select register: 0x1e
  738. [ 37.339139] SDS 4 lane coupling reg 0x20.18: 0x053f
  739. [ 37.345563] SDS 4 analog coupling reg 0x21.11: 0x000f
  740. [ 37.352399] 8021q: adding VLAN 0 to HW filter on device lan3
  741. [ 37.507021] rtl83xx-switch switch@1b000000 lan3: Link is Up - 1Gbps/Full - flow control off
  742. [ 37.793572] switch: port 3(lan3) entered blocking state
  743. [ 37.799497] switch: port 3(lan3) entered disabled state
  744. [ 37.805368] rtl83xx-switch switch@1b000000 lan3: entered allmulticast mode
  745. [ 37.849241] rtl83xx-switch switch@1b000000 lan3: entered promiscuous mode
  746. [ 37.857242] switch: port 3(lan3) entered blocking state
  747. [ 37.863085] switch: port 3(lan3) entered forwarding state
  748. [ 38.041902] Setting up RTL9300 port isolation for independent operation
  749. [ 38.049363] Port 0: traffic matrix set to 0x1fffffef
  750. [ 38.054894] Port 1: traffic matrix set to 0x1fffffdf
  751. [ 38.060465] Port 2: traffic matrix set to 0x1fffffbf
  752. [ 38.065996] Port 3: traffic matrix set to 0x1fffff7f
  753. [ 38.071551] Port 4: traffic matrix set to 0x1ffffffe
  754. [ 38.077111] Port 5: traffic matrix set to 0x1ffffffd
  755. [ 38.082639] Port 6: traffic matrix set to 0x1ffffffb
  756. [ 38.088199] Port 7: traffic matrix set to 0x1ffffff7
  757. [ 38.093724] Port 8: traffic matrix set to 0x1fffffff
  758. [ 38.099279] Port 9: traffic matrix set to 0x1fffffff
  759. [ 38.104809] Port 10: traffic matrix set to 0x1fffffff
  760. [ 38.110455] Port 11: traffic matrix set to 0x1fffffff
  761. [ 38.116079] Port 12: traffic matrix set to 0x1fffffff
  762. [ 38.121725] Port 13: traffic matrix set to 0x1fffffff
  763. [ 38.127386] Port 14: traffic matrix set to 0x1fffffff
  764. [ 38.133010] Port 15: traffic matrix set to 0x1fffffff
  765. [ 38.138656] Port 16: traffic matrix set to 0x1fffffff
  766. [ 38.144280] Port 17: traffic matrix set to 0x1fffffff
  767. [ 38.149926] Port 18: traffic matrix set to 0x1fffffff
  768. [ 38.155550] Port 19: traffic matrix set to 0x1fffffff
  769. [ 38.161195] Port 20: traffic matrix set to 0x1fffffff
  770. [ 38.166820] Port 21: traffic matrix set to 0x1fffffff
  771. [ 38.172466] Port 22: traffic matrix set to 0x1fffffff
  772. [ 38.178127] Port 23: traffic matrix set to 0x1fffffff
  773. [ 38.183751] Port 24: traffic matrix set to 0x1fffffff
  774. [ 38.189396] Port 25: traffic matrix set to 0x1fffffff
  775. [ 38.195020] Port 26: traffic matrix set to 0x1fffffff
  776. [ 38.200675] Port 27: traffic matrix set to 0x1fffffff
  777. [ 38.206299] CPU port 28: traffic matrix set to 0xfffffff
  778. [ 38.212237] === Port Pairing Debug ===
  779. [ 38.216403] Port 0 traffic matrix: 0x1fffffef
  780. [ 38.221274] Port 1 traffic matrix: 0x1fffffdf
  781. [ 38.226125] Port 2 traffic matrix: 0x1fffffbf
  782. [ 38.230998] Port 3 traffic matrix: 0x1fffff7f
  783. [ 38.235851] Port 4 traffic matrix: 0x1ffffffe
  784. [ 38.240724] Port 5 traffic matrix: 0x1ffffffd
  785. [ 38.245576] Port 6 traffic matrix: 0x1ffffffb
  786. [ 38.250449] Port 7 traffic matrix: 0x1ffffff7
  787. [ 38.255301] Port 8 traffic matrix: 0x1fffffff
  788. [ 38.260202] === MAC Configuration Debug ===
  789. [ 38.264859] Port 0: MAC_CTRL=0x00000033, FORCE_MODE=0x00000016
  790. [ 38.271381] Port 1: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  791. [ 38.277909] Port 2: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  792. [ 38.284396] Port 3: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  793. [ 38.290909] Port 4: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  794. [ 38.297430] Port 5: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  795. [ 38.303917] Port 6: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  796. [ 38.310439] Port 7: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  797. [ 38.316972] Port isolation control registers:
  798. [ 38.321814] Port 0 VLAN_PB: 0x00010004
  799. [ 38.325973] Port 1 VLAN_PB: 0x00000000
  800. [ 38.330167] Port 2 VLAN_PB: 0x00000000
  801. [ 38.334338] Port 3 VLAN_PB: 0x00000000
  802. [ 38.338532] Port 4 VLAN_PB: 0x00000000
  803. [ 38.342703] Port 5 VLAN_PB: 0x00000000
  804. [ 38.346896] Port 6 VLAN_PB: 0x00000000
  805. [ 38.351068] Port 7 VLAN_PB: 0x00000000
  806. [ 38.355227] === Trunk/LAG Configuration Debug ===
  807. [ 38.360487] Trunk mode control: 0x00000000
  808. [ 38.365041] === Special Configuration Debug ===
  809. [ 38.370103] Mirror control: 0x00000000
  810. [ 38.374275] === PHY Polling Debug ===
  811. [ 38.378374] PHY polling control: 0x0f110101
  812. [ 38.383025] Port 0: PHY polling ENABLED
  813. [ 38.387317] Port 8: PHY polling ENABLED
  814. [ 38.391582] Port 16: PHY polling ENABLED
  815. [ 38.395936] Port 20: PHY polling ENABLED
  816. [ 38.400323] Port 24: PHY polling ENABLED
  817. [ 38.404687] Port 25: PHY polling ENABLED
  818. [ 38.409074] Port 26: PHY polling ENABLED
  819. [ 38.413437] Port 27: PHY polling ENABLED
  820. [ 38.417833] Port 0 SMI config: 0x00000000
  821. [ 38.422293] Port 1 SMI config: 0x00000400
  822. [ 38.426744] Port 2 SMI config: 0x00200000
  823. [ 38.431234] Port 3 SMI config: 0x00000c00
  824. [ 38.435697] Port 4 SMI config: 0x00018820
  825. [ 38.440181] Port 5 SMI config: 0x00000000
  826. [ 38.444640] Port 6 SMI config: 0x00f00000
  827. [ 38.449143] Port 7 SMI config: 0x00000000
  828. [ 38.453610] Setting up PHY polling for all ports
  829. [ 38.458775] PHY polling mask set to: 0x0f110101
  830. [ 38.463810] === Direct Link Status Debug ===
  831. [ 38.468583] MAC_LINK_STS register: 0x11000001
  832. [ 38.473430] Port 0: Link UP (bit 0 set)
  833. [ 38.477740] Port 24: Link UP (bit 24 set) - PHANTOM!
  834. [ 38.483269] Port 28: Link UP (bit 28 set) - PHANTOM!
  835. [ 38.488824] Port 0 speed status: 0x00000002
  836. [ 38.493477] Port 1 speed status: 0x00000002
  837. [ 38.498169] Port 2 speed status: 0x00000002
  838. [ 38.502824] Port 3 speed status: 0x00000002
  839. [ 38.507505] Port 4 speed status: 0x00000002
  840. [ 38.512154] Port 5 speed status: 0x00000002
  841. [ 38.516797] Port 6 speed status: 0x00000002
  842. [ 38.521475] Port 7 speed status: 0x00000002
  843. [ 38.526146] rtl83xx-switch switch@1b000000 lan4: configuring for phy/usxgmii link mode
  844. [ 38.535009] rtl93xx_phylink_mac_config port 20, mode 0, phy-mode usxgmii, speed -1, link 0
  845. [ 38.544251] rtl93xx_phylink_mac_config SDS is 5
  846. [ 38.549324] rtl93xx_phylink_mac_config: Configuring port 20 SDS 5 for USXGMII
  847. [ 38.557295] rtl9300_serdes_setup: port 20, sds 5, mode usxgmii (30)
  848. [ 38.564272] rtl9300_sds_rst 30
  849. [ 38.587658] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 5
  850. [ 38.653839] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  851. [ 38.660876] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  852. [ 38.668684] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  853. [ 38.675784] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  854. [ 38.683491] rtl9300_phy_enable_10g_1g set medium: 00000002
  855. [ 38.690625] rtl9300_phy_enable_10g_1g set medium after: 00000002
  856. [ 38.699339] rtl9300_serdes_mac_link_config: registers before 00000000 00001203
  857. [ 38.711401] rtl9300_serdes_mac_link_config: registers after 00000000 00001003
  858. [ 38.719375] rtl9300_force_sds_mode: SDS: 5, mode 30
  859. [ 38.724799] rtl9300_force_sds_mode: serdes 5 forcing to d
  860. [ 38.736815] Configuring USXGMII for independent operation on SDS 5
  861. [ 38.772702] rtl9300_force_sds_mode: serdes 5 forced to d DONE
  862. [ 38.779135] start_1.1.1 initial value for sds 5
  863. [ 38.785174] Before calibration - SDS 5 coupling: 0x051f
  864. [ 38.791013] start_1.1.1 initial value for sds 5
  865. [ 38.852997] end_1.1.1 --
  866. [ 38.855816] start_1.1.2 Load DFE init. value
  867. [ 38.862595] end_1.1.2
  868. [ 38.865127] start_1.1.3 disable LEQ training,enable DFE clock
  869. [ 38.883535] end_1.1.3 --
  870. [ 38.886352] start_1.1.4 offset cali setting
  871. [ 38.893025] end_1.1.4
  872. [ 38.895549] start_1.1.5 LEQ and DFE setting
  873. [ 38.914210] end_1.1.5
  874. [ 38.925747] start_1.2.1 ForegroundOffsetCal_Manual
  875. [ 38.935102] end_1.2.1
  876. [ 38.946102] start_1.2.3 Foreground Calibration
  877. [ 38.964599] rtl9300_do_rx_calibration_2_3: fgcal_gray: 20, fgcal_binary 30
  878. [ 38.973296] rtl9300_do_rx_calibration_2_3: end_1.2.3
  879. [ 38.978857] start_1.4.1
  880. [ 39.202418] end_1.4.1
  881. [ 39.205147] start_1.4.2
  882. [ 39.217689] vth_set_bin = 2
  883. [ 39.220410] vth_set_bin = 2
  884. [ 39.224504] Vth Maunal = 0
  885. [ 39.343407] Tap0 Sign : +
  886. [ 39.346423] tap0_coef_bin = 17
  887. [ 39.350360] tap0 manual = 0
  888. [ 39.359768] end_1.4.2
  889. [ 39.384856] After calibration - SDS 5 coupling: 0x051f
  890. [ 39.393119] Forcing SerDes 5 coupling bits to independent mode
  891. [ 39.404624] Final SDS 5 coupling reg 0x20.18: 0x053f (should be 0x053f)
  892. [ 39.416024] USXGMII final coupling check for SDS 5:
  893. [ 39.422487] Reg 0x20.18: 0x053f
  894. [ 39.427200] Reg 0x21.11: 0x000f
  895. [ 39.431884] SDS 5 force mode register: 0xd
  896. [ 39.436432] SDS 5 mode select register: 0x1e
  897. [ 39.442205] SDS 5 lane coupling reg 0x20.18: 0x053f
  898. [ 39.448663] SDS 5 analog coupling reg 0x21.11: 0x000f
  899. [ 39.455468] 8021q: adding VLAN 0 to HW filter on device lan4
  900. [ 39.587278] rtl83xx-switch switch@1b000000 lan4: Link is Up - 1Gbps/Full - flow control off
  901. [ 39.668630] switch: port 4(lan4) entered blocking state
  902. [ 39.674485] switch: port 4(lan4) entered disabled state
  903. [ 39.680438] rtl83xx-switch switch@1b000000 lan4: entered allmulticast mode
  904. [ 39.689712] rtl83xx-switch switch@1b000000 lan4: entered promiscuous mode
  905. [ 39.697730] switch: port 4(lan4) entered blocking state
  906. [ 39.703574] switch: port 4(lan4) entered forwarding state
  907. [ 39.751946] Setting up RTL9300 port isolation for independent operation
  908. [ 39.759389] Port 0: traffic matrix set to 0x1fffffef
  909. [ 39.764918] Port 1: traffic matrix set to 0x1fffffdf
  910. [ 39.770491] Port 2: traffic matrix set to 0x1fffffbf
  911. [ 39.776021] Port 3: traffic matrix set to 0x1fffff7f
  912. [ 39.781576] Port 4: traffic matrix set to 0x1ffffffe
  913. [ 39.787136] Port 5: traffic matrix set to 0x1ffffffd
  914. [ 39.792663] Port 6: traffic matrix set to 0x1ffffffb
  915. [ 39.798212] Port 7: traffic matrix set to 0x1ffffff7
  916. [ 39.803739] Port 8: traffic matrix set to 0x1fffffff
  917. [ 39.809288] Port 9: traffic matrix set to 0x1fffffff
  918. [ 39.814816] Port 10: traffic matrix set to 0x1fffffff
  919. [ 39.820463] Port 11: traffic matrix set to 0x1fffffff
  920. [ 39.826085] Port 12: traffic matrix set to 0x1fffffff
  921. [ 39.831731] Port 13: traffic matrix set to 0x1fffffff
  922. [ 39.837393] Port 14: traffic matrix set to 0x1fffffff
  923. [ 39.843017] Port 15: traffic matrix set to 0x1fffffff
  924. [ 39.848673] Port 16: traffic matrix set to 0x1fffffff
  925. [ 39.854296] Port 17: traffic matrix set to 0x1fffffff
  926. [ 39.859947] Port 18: traffic matrix set to 0x1fffffff
  927. [ 39.865566] Port 19: traffic matrix set to 0x1fffffff
  928. [ 39.871211] Port 20: traffic matrix set to 0x1fffffff
  929. [ 39.876836] Port 21: traffic matrix set to 0x1fffffff
  930. [ 39.882480] Port 22: traffic matrix set to 0x1fffffff
  931. [ 39.888142] Port 23: traffic matrix set to 0x1fffffff
  932. [ 39.893767] Port 24: traffic matrix set to 0x1fffffff
  933. [ 39.899412] Port 25: traffic matrix set to 0x1fffffff
  934. [ 39.905037] Port 26: traffic matrix set to 0x1fffffff
  935. [ 39.910682] Port 27: traffic matrix set to 0x1fffffff
  936. [ 39.916305] CPU port 28: traffic matrix set to 0xfffffff
  937. [ 39.922238] === Port Pairing Debug ===
  938. [ 39.926409] Port 0 traffic matrix: 0x1fffffef
  939. [ 39.931280] Port 1 traffic matrix: 0x1fffffdf
  940. [ 39.936133] Port 2 traffic matrix: 0x1fffffbf
  941. [ 39.941006] Port 3 traffic matrix: 0x1fffff7f
  942. [ 39.945857] Port 4 traffic matrix: 0x1ffffffe
  943. [ 39.950730] Port 5 traffic matrix: 0x1ffffffd
  944. [ 39.955582] Port 6 traffic matrix: 0x1ffffffb
  945. [ 39.960464] Port 7 traffic matrix: 0x1ffffff7
  946. [ 39.965317] Port 8 traffic matrix: 0x1fffffff
  947. [ 39.970198] === MAC Configuration Debug ===
  948. [ 39.974850] Port 0: MAC_CTRL=0x00000033, FORCE_MODE=0x00000016
  949. [ 39.981372] Port 1: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  950. [ 39.987910] Port 2: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  951. [ 39.994403] Port 3: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  952. [ 40.000920] Port 4: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  953. [ 40.007445] Port 5: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  954. [ 40.013932] Port 6: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  955. [ 40.020449] Port 7: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  956. [ 40.026974] Port isolation control registers:
  957. [ 40.031820] Port 0 VLAN_PB: 0x00010004
  958. [ 40.035980] Port 1 VLAN_PB: 0x00000000
  959. [ 40.040176] Port 2 VLAN_PB: 0x00000000
  960. [ 40.044345] Port 3 VLAN_PB: 0x00000000
  961. [ 40.048540] Port 4 VLAN_PB: 0x00000000
  962. [ 40.052710] Port 5 VLAN_PB: 0x00000000
  963. [ 40.056903] Port 6 VLAN_PB: 0x00000000
  964. [ 40.061074] Port 7 VLAN_PB: 0x00000000
  965. [ 40.065234] === Trunk/LAG Configuration Debug ===
  966. [ 40.070504] Trunk mode control: 0x00000000
  967. [ 40.075057] === Special Configuration Debug ===
  968. [ 40.080123] Mirror control: 0x00000000
  969. [ 40.084291] === PHY Polling Debug ===
  970. [ 40.088388] PHY polling control: 0x0f110101
  971. [ 40.093040] Port 0: PHY polling ENABLED
  972. [ 40.097331] Port 8: PHY polling ENABLED
  973. [ 40.101598] Port 16: PHY polling ENABLED
  974. [ 40.105951] Port 20: PHY polling ENABLED
  975. [ 40.110339] Port 24: PHY polling ENABLED
  976. [ 40.114702] Port 25: PHY polling ENABLED
  977. [ 40.119110] Port 26: PHY polling ENABLED
  978. [ 40.123480] Port 27: PHY polling ENABLED
  979. [ 40.127874] Port 0 SMI config: 0x00000000
  980. [ 40.132336] Port 1 SMI config: 0x00000400
  981. [ 40.136785] Port 2 SMI config: 0x00200000
  982. [ 40.141271] Port 3 SMI config: 0x00000c00
  983. [ 40.145730] Port 4 SMI config: 0x00018820
  984. [ 40.150214] Port 5 SMI config: 0x00000000
  985. [ 40.154674] Port 6 SMI config: 0x00f00000
  986. [ 40.159157] Port 7 SMI config: 0x00000000
  987. [ 40.163618] Setting up PHY polling for all ports
  988. [ 40.168777] PHY polling mask set to: 0x0f110101
  989. [ 40.173816] === Direct Link Status Debug ===
  990. [ 40.178600] MAC_LINK_STS register: 0x11000001
  991. [ 40.183445] Port 0: Link UP (bit 0 set)
  992. [ 40.187741] Port 24: Link UP (bit 24 set) - PHANTOM!
  993. [ 40.193258] Port 28: Link UP (bit 28 set) - PHANTOM!
  994. [ 40.198806] Port 0 speed status: 0x00000002
  995. [ 40.203457] Port 1 speed status: 0x00000002
  996. [ 40.208134] Port 2 speed status: 0x00000002
  997. [ 40.212787] Port 3 speed status: 0x00000002
  998. [ 40.217464] Port 4 speed status: 0x00000002
  999. [ 40.222118] Port 5 speed status: 0x00000002
  1000. [ 40.226760] Port 6 speed status: 0x00000002
  1001. [ 40.231438] Port 7 speed status: 0x00000002
  1002. [ 40.236110] rtl83xx-switch switch@1b000000 lan5: configuring for phy/usxgmii link mode
  1003. [ 40.244961] rtl93xx_phylink_mac_config port 24, mode 0, phy-mode usxgmii, speed -1, link 0
  1004. [ 40.254200] rtl93xx_phylink_mac_config SDS is 6
  1005. [ 40.259272] rtl93xx_phylink_mac_config: Configuring port 24 SDS 6 for USXGMII
  1006. [ 40.267268] rtl9300_serdes_setup: port 24, sds 6, mode usxgmii (30)
  1007. [ 40.274245] rtl9300_sds_rst 30
  1008. [ 40.297647] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 6
  1009. [ 40.363815] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  1010. [ 40.370857] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  1011. [ 40.378672] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  1012. [ 40.385773] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  1013. [ 40.393480] rtl9300_phy_enable_10g_1g set medium: 00000002
  1014. [ 40.400624] rtl9300_phy_enable_10g_1g set medium after: 00000002
  1015. [ 40.409342] rtl9300_serdes_mac_link_config: registers before 00000000 00001203
  1016. [ 40.421408] rtl9300_serdes_mac_link_config: registers after 00000000 00001003
  1017. [ 40.429382] rtl9300_force_sds_mode: SDS: 6, mode 30
  1018. [ 40.434806] rtl9300_force_sds_mode: serdes 6 forcing to d
  1019. [ 40.446822] Configuring USXGMII for independent operation on SDS 6
  1020. [ 40.482693] rtl9300_force_sds_mode: serdes 6 forced to d DONE
  1021. [ 40.489125] start_1.1.1 initial value for sds 6
  1022. [ 40.495163] Before calibration - SDS 6 coupling: 0x051f
  1023. [ 40.501003] start_1.1.1 initial value for sds 6
  1024. [ 40.563002] end_1.1.1 --
  1025. [ 40.565824] start_1.1.2 Load DFE init. value
  1026. [ 40.572592] end_1.1.2
  1027. [ 40.575117] start_1.1.3 disable LEQ training,enable DFE clock
  1028. [ 40.593558] end_1.1.3 --
  1029. [ 40.596385] start_1.1.4 offset cali setting
  1030. [ 40.603058] end_1.1.4
  1031. [ 40.605582] start_1.1.5 LEQ and DFE setting
  1032. [ 40.624251] end_1.1.5
  1033. [ 40.635793] start_1.2.1 ForegroundOffsetCal_Manual
  1034. [ 40.645144] end_1.2.1
  1035. [ 40.656143] start_1.2.3 Foreground Calibration
  1036. [ 40.674629] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  1037. [ 40.683317] rtl9300_do_rx_calibration_2_3: end_1.2.3
  1038. [ 40.688876] start_1.4.1
  1039. [ 40.912434] end_1.4.1
  1040. [ 40.915154] start_1.4.2
  1041. [ 40.927696] vth_set_bin = 2
  1042. [ 40.930417] vth_set_bin = 2
  1043. [ 40.934511] Vth Maunal = 0
  1044. [ 41.053432] Tap0 Sign : +
  1045. [ 41.056449] tap0_coef_bin = 16
  1046. [ 41.060394] tap0 manual = 0
  1047. [ 41.069816] end_1.4.2
  1048. [ 41.094898] After calibration - SDS 6 coupling: 0x051f
  1049. [ 41.103161] Forcing SerDes 6 coupling bits to independent mode
  1050. [ 41.114666] Final SDS 6 coupling reg 0x20.18: 0x053f (should be 0x053f)
  1051. [ 41.126057] USXGMII final coupling check for SDS 6:
  1052. [ 41.132515] Reg 0x20.18: 0x053f
  1053. [ 41.137233] Reg 0x21.11: 0x000f
  1054. [ 41.141916] SDS 6 force mode register: 0xd
  1055. [ 41.146464] SDS 6 mode select register: 0x1e
  1056. [ 41.152238] SDS 6 lane coupling reg 0x20.18: 0x053f
  1057. [ 41.158696] SDS 6 analog coupling reg 0x21.11: 0x000f
  1058. [ 41.165508] 8021q: adding VLAN 0 to HW filter on device lan5
  1059. [ 41.225991] rtl83xx-switch switch@1b000000 lan5: Link is Up - 1Gbps/Full - flow control off
  1060. [ 41.236554] switch: port 5(lan5) entered blocking state
  1061. [ 41.242499] switch: port 5(lan5) entered disabled state
  1062. [ 41.248424] rtl83xx-switch switch@1b000000 lan5: entered allmulticast mode
  1063. [ 41.257027] rtl83xx-switch switch@1b000000 lan5: entered promiscuous mode
  1064. [ 41.264893] switch: port 5(lan5) entered blocking state
  1065. [ 41.270803] switch: port 5(lan5) entered forwarding state
  1066. [ 41.317313] Setting up RTL9300 port isolation for independent operation
  1067. [ 41.324702] Port 0: traffic matrix set to 0x1fffffef
  1068. [ 41.330300] Port 1: traffic matrix set to 0x1fffffdf
  1069. [ 41.335833] Port 2: traffic matrix set to 0x1fffffbf
  1070. [ 41.341388] Port 3: traffic matrix set to 0x1fffff7f
  1071. [ 41.346957] Port 4: traffic matrix set to 0x1ffffffe
  1072. [ 41.352484] Port 5: traffic matrix set to 0x1ffffffd
  1073. [ 41.358033] Port 6: traffic matrix set to 0x1ffffffb
  1074. [ 41.363560] Port 7: traffic matrix set to 0x1ffffff7
  1075. [ 41.369110] Port 8: traffic matrix set to 0x1fffffff
  1076. [ 41.374637] Port 9: traffic matrix set to 0x1fffffff
  1077. [ 41.380186] Port 10: traffic matrix set to 0x1fffffff
  1078. [ 41.385810] Port 11: traffic matrix set to 0x1fffffff
  1079. [ 41.391468] Port 12: traffic matrix set to 0x1fffffff
  1080. [ 41.397132] Port 13: traffic matrix set to 0x1fffffff
  1081. [ 41.402751] Port 14: traffic matrix set to 0x1fffffff
  1082. [ 41.408396] Port 15: traffic matrix set to 0x1fffffff
  1083. [ 41.414020] Port 16: traffic matrix set to 0x1fffffff
  1084. [ 41.419665] Port 17: traffic matrix set to 0x1fffffff
  1085. [ 41.425291] Port 18: traffic matrix set to 0x1fffffff
  1086. [ 41.430936] Port 19: traffic matrix set to 0x1fffffff
  1087. [ 41.436560] Port 20: traffic matrix set to 0x1fffffff
  1088. [ 41.442206] Port 21: traffic matrix set to 0x1fffffff
  1089. [ 41.447867] Port 22: traffic matrix set to 0x1fffffff
  1090. [ 41.453491] Port 23: traffic matrix set to 0x1fffffff
  1091. [ 41.459136] Port 24: traffic matrix set to 0x1fffffff
  1092. [ 41.464761] Port 25: traffic matrix set to 0x1fffffff
  1093. [ 41.470407] Port 26: traffic matrix set to 0x1fffffff
  1094. [ 41.476031] Port 27: traffic matrix set to 0x1fffffff
  1095. [ 41.481675] CPU port 28: traffic matrix set to 0xfffffff
  1096. [ 41.487623] === Port Pairing Debug ===
  1097. [ 41.491796] Port 0 traffic matrix: 0x1fffffef
  1098. [ 41.496639] Port 1 traffic matrix: 0x1fffffdf
  1099. [ 41.501521] Port 2 traffic matrix: 0x1fffffbf
  1100. [ 41.506373] Port 3 traffic matrix: 0x1fffff7f
  1101. [ 41.511250] Port 4 traffic matrix: 0x1ffffffe
  1102. [ 41.516098] Port 5 traffic matrix: 0x1ffffffd
  1103. [ 41.520971] Port 6 traffic matrix: 0x1ffffffb
  1104. [ 41.525823] Port 7 traffic matrix: 0x1ffffff7
  1105. [ 41.530696] Port 8 traffic matrix: 0x1fffffff
  1106. [ 41.535551] === MAC Configuration Debug ===
  1107. [ 41.540227] Port 0: MAC_CTRL=0x00000033, FORCE_MODE=0x00000016
  1108. [ 41.546720] Port 1: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1109. [ 41.553232] Port 2: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1110. [ 41.559753] Port 3: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1111. [ 41.566241] Port 4: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1112. [ 41.572752] Port 5: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1113. [ 41.579274] Port 6: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1114. [ 41.585760] Port 7: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1115. [ 41.592272] Port isolation control registers:
  1116. [ 41.597151] Port 0 VLAN_PB: 0x00010004
  1117. [ 41.601322] Port 1 VLAN_PB: 0x00000000
  1118. [ 41.605482] Port 2 VLAN_PB: 0x00000000
  1119. [ 41.609687] Port 3 VLAN_PB: 0x00000000
  1120. [ 41.613856] Port 4 VLAN_PB: 0x00000000
  1121. [ 41.618055] Port 5 VLAN_PB: 0x00000000
  1122. [ 41.622221] Port 6 VLAN_PB: 0x00000000
  1123. [ 41.626380] Port 7 VLAN_PB: 0x00000000
  1124. [ 41.630575] === Trunk/LAG Configuration Debug ===
  1125. [ 41.635811] Trunk mode control: 0x00000000
  1126. [ 41.640388] === Special Configuration Debug ===
  1127. [ 41.645427] Mirror control: 0x00000000
  1128. [ 41.649622] === PHY Polling Debug ===
  1129. [ 41.653696] PHY polling control: 0x0f110101
  1130. [ 41.658372] Port 0: PHY polling ENABLED
  1131. [ 41.662639] Port 8: PHY polling ENABLED
  1132. [ 41.666930] Port 16: PHY polling ENABLED
  1133. [ 41.671293] Port 20: PHY polling ENABLED
  1134. [ 41.675646] Port 24: PHY polling ENABLED
  1135. [ 41.680035] Port 25: PHY polling ENABLED
  1136. [ 41.684397] Port 26: PHY polling ENABLED
  1137. [ 41.688785] Port 27: PHY polling ENABLED
  1138. [ 41.693149] Port 0 SMI config: 0x00000000
  1139. [ 41.697654] Port 1 SMI config: 0x00000400
  1140. [ 41.702120] Port 2 SMI config: 0x00200000
  1141. [ 41.706568] Port 3 SMI config: 0x00000c00
  1142. [ 41.711061] Port 4 SMI config: 0x00018820
  1143. [ 41.715522] Port 5 SMI config: 0x00000000
  1144. [ 41.720015] Port 6 SMI config: 0x00f00000
  1145. [ 41.724475] Port 7 SMI config: 0x00000000
  1146. [ 41.728963] Setting up PHY polling for all ports
  1147. [ 41.734095] PHY polling mask set to: 0x0f110101
  1148. [ 41.739157] === Direct Link Status Debug ===
  1149. [ 41.743907] MAC_LINK_STS register: 0x11000001
  1150. [ 41.748776] Port 0: Link UP (bit 0 set)
  1151. [ 41.753044] Port 24: Link UP (bit 24 set) - PHANTOM!
  1152. [ 41.758592] Port 28: Link UP (bit 28 set) - PHANTOM!
  1153. [ 41.764113] Port 0 speed status: 0x00000002
  1154. [ 41.768790] Port 1 speed status: 0x00000002
  1155. [ 41.773442] Port 2 speed status: 0x00000002
  1156. [ 41.778144] Port 3 speed status: 0x00000002
  1157. [ 41.782799] Port 4 speed status: 0x00000002
  1158. [ 41.787484] Port 5 speed status: 0x00000002
  1159. [ 41.792138] Port 6 speed status: 0x00000002
  1160. [ 41.796780] Port 7 speed status: 0x00000002
  1161. [ 41.801477] rtl83xx-switch switch@1b000000 lan6: configuring for phy/usxgmii link mode
  1162. [ 41.810336] rtl93xx_phylink_mac_config port 25, mode 0, phy-mode usxgmii, speed -1, link 0
  1163. [ 41.819577] rtl93xx_phylink_mac_config SDS is 7
  1164. [ 41.824613] rtl93xx_phylink_mac_config: Configuring port 25 SDS 7 for USXGMII
  1165. [ 41.832584] rtl9300_serdes_setup: port 25, sds 7, mode usxgmii (30)
  1166. [ 41.839600] rtl9300_sds_rst 30
  1167. [ 41.862982] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 7
  1168. [ 41.929157] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  1169. [ 41.936168] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  1170. [ 41.943982] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  1171. [ 41.951128] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  1172. [ 41.958848] rtl9300_phy_enable_10g_1g set medium: 00000002
  1173. [ 41.965948] rtl9300_phy_enable_10g_1g set medium after: 00000002
  1174. [ 41.974654] rtl9300_serdes_mac_link_config: registers before 00000000 00001203
  1175. [ 41.986716] rtl9300_serdes_mac_link_config: registers after 00000000 00001003
  1176. [ 41.994688] rtl9300_force_sds_mode: SDS: 7, mode 30
  1177. [ 42.000147] rtl9300_force_sds_mode: serdes 7 forcing to d
  1178. [ 42.012170] Configuring USXGMII for independent operation on SDS 7
  1179. [ 42.048097] rtl9300_force_sds_mode: serdes 7 forced to d DONE
  1180. [ 42.054507] start_1.1.1 initial value for sds 7
  1181. [ 42.060572] Before calibration - SDS 7 coupling: 0x051f
  1182. [ 42.066388] start_1.1.1 initial value for sds 7
  1183. [ 42.128474] end_1.1.1 --
  1184. [ 42.131307] start_1.1.2 Load DFE init. value
  1185. [ 42.138072] end_1.1.2
  1186. [ 42.140600] start_1.1.3 disable LEQ training,enable DFE clock
  1187. [ 42.159011] end_1.1.3 --
  1188. [ 42.161832] start_1.1.4 offset cali setting
  1189. [ 42.168507] end_1.1.4
  1190. [ 42.171030] start_1.1.5 LEQ and DFE setting
  1191. [ 42.189703] end_1.1.5
  1192. [ 42.201248] start_1.2.1 ForegroundOffsetCal_Manual
  1193. [ 42.210601] end_1.2.1
  1194. [ 42.221603] start_1.2.3 Foreground Calibration
  1195. [ 42.240079] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  1196. [ 42.248763] rtl9300_do_rx_calibration_2_3: end_1.2.3
  1197. [ 42.254289] start_1.4.1
  1198. [ 42.477900] end_1.4.1
  1199. [ 42.480628] start_1.4.2
  1200. [ 42.493161] vth_set_bin = 2
  1201. [ 42.495891] vth_set_bin = 2
  1202. [ 42.500035] Vth Maunal = 0
  1203. [ 42.618944] Tap0 Sign : +
  1204. [ 42.621957] tap0_coef_bin = 18
  1205. [ 42.625857] tap0 manual = 0
  1206. [ 42.635261] end_1.4.2
  1207. [ 42.660361] After calibration - SDS 7 coupling: 0x051f
  1208. [ 42.668619] Forcing SerDes 7 coupling bits to independent mode
  1209. [ 42.680130] Final SDS 7 coupling reg 0x20.18: 0x053f (should be 0x053f)
  1210. [ 42.691518] USXGMII final coupling check for SDS 7:
  1211. [ 42.697979] Reg 0x20.18: 0x053f
  1212. [ 42.702666] Reg 0x21.11: 0x000f
  1213. [ 42.707376] SDS 7 force mode register: 0xd
  1214. [ 42.711941] SDS 7 mode select register: 0x1e
  1215. [ 42.717712] SDS 7 lane coupling reg 0x20.18: 0x053f
  1216. [ 42.724137] SDS 7 analog coupling reg 0x21.11: 0x000f
  1217. [ 42.730972] 8021q: adding VLAN 0 to HW filter on device lan6
  1218. [ 42.796267] rtl83xx-switch switch@1b000000 lan6: Link is Up - 1Gbps/Full - flow control off
  1219. [ 42.806931] switch: port 6(lan6) entered blocking state
  1220. [ 42.812781] switch: port 6(lan6) entered disabled state
  1221. [ 42.818701] rtl83xx-switch switch@1b000000 lan6: entered allmulticast mode
  1222. [ 42.827291] rtl83xx-switch switch@1b000000 lan6: entered promiscuous mode
  1223. [ 42.835161] switch: port 6(lan6) entered blocking state
  1224. [ 42.841094] switch: port 6(lan6) entered forwarding state
  1225. [ 42.887214] Setting up RTL9300 port isolation for independent operation
  1226. [ 42.894608] Port 0: traffic matrix set to 0x1fffffef
  1227. [ 42.900208] Port 1: traffic matrix set to 0x1fffffdf
  1228. [ 42.905740] Port 2: traffic matrix set to 0x1fffffbf
  1229. [ 42.911294] Port 3: traffic matrix set to 0x1fffff7f
  1230. [ 42.916825] Port 4: traffic matrix set to 0x1ffffffe
  1231. [ 42.922375] Port 5: traffic matrix set to 0x1ffffffd
  1232. [ 42.927951] Port 6: traffic matrix set to 0x1ffffffb
  1233. [ 42.933475] Port 7: traffic matrix set to 0x1ffffff7
  1234. [ 42.939030] Port 8: traffic matrix set to 0x1fffffff
  1235. [ 42.944561] Port 9: traffic matrix set to 0x1fffffff
  1236. [ 42.950110] Port 10: traffic matrix set to 0x1fffffff
  1237. [ 42.955734] Port 11: traffic matrix set to 0x1fffffff
  1238. [ 42.961380] Port 12: traffic matrix set to 0x1fffffff
  1239. [ 42.967048] Port 13: traffic matrix set to 0x1fffffff
  1240. [ 42.972674] Port 14: traffic matrix set to 0x1fffffff
  1241. [ 42.978320] Port 15: traffic matrix set to 0x1fffffff
  1242. [ 42.983944] Port 16: traffic matrix set to 0x1fffffff
  1243. [ 42.989590] Port 17: traffic matrix set to 0x1fffffff
  1244. [ 42.995214] Port 18: traffic matrix set to 0x1fffffff
  1245. [ 43.000859] Port 19: traffic matrix set to 0x1fffffff
  1246. [ 43.006483] Port 20: traffic matrix set to 0x1fffffff
  1247. [ 43.012130] Port 21: traffic matrix set to 0x1fffffff
  1248. [ 43.017794] Port 22: traffic matrix set to 0x1fffffff
  1249. [ 43.023414] Port 23: traffic matrix set to 0x1fffffff
  1250. [ 43.029060] Port 24: traffic matrix set to 0x1fffffff
  1251. [ 43.034684] Port 25: traffic matrix set to 0x1fffffff
  1252. [ 43.040341] Port 26: traffic matrix set to 0x1fffffff
  1253. [ 43.045963] Port 27: traffic matrix set to 0x1fffffff
  1254. [ 43.051623] CPU port 28: traffic matrix set to 0xfffffff
  1255. [ 43.057578] === Port Pairing Debug ===
  1256. [ 43.061744] Port 0 traffic matrix: 0x1fffffef
  1257. [ 43.066579] Port 1 traffic matrix: 0x1fffffdf
  1258. [ 43.071453] Port 2 traffic matrix: 0x1fffffbf
  1259. [ 43.076304] Port 3 traffic matrix: 0x1fffff7f
  1260. [ 43.081177] Port 4 traffic matrix: 0x1ffffffe
  1261. [ 43.086029] Port 5 traffic matrix: 0x1ffffffd
  1262. [ 43.090902] Port 6 traffic matrix: 0x1ffffffb
  1263. [ 43.095755] Port 7 traffic matrix: 0x1ffffff7
  1264. [ 43.100628] Port 8 traffic matrix: 0x1fffffff
  1265. [ 43.105484] === MAC Configuration Debug ===
  1266. [ 43.110159] Port 0: MAC_CTRL=0x00000033, FORCE_MODE=0x00000016
  1267. [ 43.116652] Port 1: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1268. [ 43.123165] Port 2: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1269. [ 43.129686] Port 3: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1270. [ 43.136173] Port 4: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1271. [ 43.142685] Port 5: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1272. [ 43.149216] Port 6: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1273. [ 43.155712] Port 7: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1274. [ 43.162227] Port isolation control registers:
  1275. [ 43.167102] Port 0 VLAN_PB: 0x00010004
  1276. [ 43.171272] Port 1 VLAN_PB: 0x00000000
  1277. [ 43.175432] Port 2 VLAN_PB: 0x00000000
  1278. [ 43.179627] Port 3 VLAN_PB: 0x00000000
  1279. [ 43.183797] Port 4 VLAN_PB: 0x00000000
  1280. [ 43.187991] Port 5 VLAN_PB: 0x00000000
  1281. [ 43.192162] Port 6 VLAN_PB: 0x00000000
  1282. [ 43.196321] Port 7 VLAN_PB: 0x00000000
  1283. [ 43.200516] === Trunk/LAG Configuration Debug ===
  1284. [ 43.205753] Trunk mode control: 0x00000000
  1285. [ 43.210329] === Special Configuration Debug ===
  1286. [ 43.215368] Mirror control: 0x00000000
  1287. [ 43.219563] === PHY Polling Debug ===
  1288. [ 43.223637] PHY polling control: 0x0f110101
  1289. [ 43.228314] Port 0: PHY polling ENABLED
  1290. [ 43.232580] Port 8: PHY polling ENABLED
  1291. [ 43.236837] Port 16: PHY polling ENABLED
  1292. [ 43.241226] Port 20: PHY polling ENABLED
  1293. [ 43.245589] Port 24: PHY polling ENABLED
  1294. [ 43.249976] Port 25: PHY polling ENABLED
  1295. [ 43.254338] Port 26: PHY polling ENABLED
  1296. [ 43.258748] Port 27: PHY polling ENABLED
  1297. [ 43.263117] Port 0 SMI config: 0x00000000
  1298. [ 43.267608] Port 1 SMI config: 0x00000400
  1299. [ 43.272070] Port 2 SMI config: 0x00200000
  1300. [ 43.276519] Port 3 SMI config: 0x00000c00
  1301. [ 43.281003] Port 4 SMI config: 0x00018820
  1302. [ 43.285463] Port 5 SMI config: 0x00000000
  1303. [ 43.289947] Port 6 SMI config: 0x00f00000
  1304. [ 43.294407] Port 7 SMI config: 0x00000000
  1305. [ 43.298891] Setting up PHY polling for all ports
  1306. [ 43.304027] PHY polling mask set to: 0x0f110101
  1307. [ 43.309090] === Direct Link Status Debug ===
  1308. [ 43.313840] MAC_LINK_STS register: 0x11000001
  1309. [ 43.318710] Port 0: Link UP (bit 0 set)
  1310. [ 43.322976] Port 24: Link UP (bit 24 set) - PHANTOM!
  1311. [ 43.328523] Port 28: Link UP (bit 28 set) - PHANTOM!
  1312. [ 43.334044] Port 0 speed status: 0x00000002
  1313. [ 43.338722] Port 1 speed status: 0x00000002
  1314. [ 43.343375] Port 2 speed status: 0x00000002
  1315. [ 43.348051] Port 3 speed status: 0x00000002
  1316. [ 43.352705] Port 4 speed status: 0x00000002
  1317. [ 43.357381] Port 5 speed status: 0x00000002
  1318. [ 43.362034] Port 6 speed status: 0x00000002
  1319. [ 43.366678] Port 7 speed status: 0x00000002
  1320. [ 43.371385] rtl83xx-switch switch@1b000000 lan7: configuring for phy/usxgmii link mode
  1321. [ 43.380268] rtl93xx_phylink_mac_config port 26, mode 0, phy-mode usxgmii, speed -1, link 0
  1322. [ 43.389515] rtl93xx_phylink_mac_config SDS is 8
  1323. [ 43.394554] rtl93xx_phylink_mac_config: Configuring port 26 SDS 8 for USXGMII
  1324. [ 43.402516] rtl9300_serdes_setup: port 26, sds 8, mode usxgmii (30)
  1325. [ 43.409527] rtl9300_sds_rst 30
  1326. [ 43.432906] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 8
  1327. [ 43.499096] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  1328. [ 43.506110] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  1329. [ 43.513913] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  1330. [ 43.521047] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  1331. [ 43.528762] rtl9300_phy_enable_10g_1g set medium: 00000002
  1332. [ 43.535863] rtl9300_phy_enable_10g_1g set medium after: 00000002
  1333. [ 43.544569] rtl9300_serdes_mac_link_config: registers before 00000000 00001203
  1334. [ 43.556631] rtl9300_serdes_mac_link_config: registers after 00000000 00001003
  1335. [ 43.564604] rtl9300_force_sds_mode: SDS: 8, mode 30
  1336. [ 43.570062] rtl9300_force_sds_mode: serdes 8 forcing to d
  1337. [ 43.582085] Configuring USXGMII for independent operation on SDS 8
  1338. [ 43.617970] rtl9300_force_sds_mode: serdes 8 forced to d DONE
  1339. [ 43.624368] start_1.1.1 initial value for sds 8
  1340. [ 43.630430] Before calibration - SDS 8 coupling: 0x051f
  1341. [ 43.636241] start_1.1.1 initial value for sds 8
  1342. [ 43.698244] end_1.1.1 --
  1343. [ 43.701071] start_1.1.2 Load DFE init. value
  1344. [ 43.707841] end_1.1.2
  1345. [ 43.710366] start_1.1.3 disable LEQ training,enable DFE clock
  1346. [ 43.728760] end_1.1.3 --
  1347. [ 43.731580] start_1.1.4 offset cali setting
  1348. [ 43.738249] end_1.1.4
  1349. [ 43.740779] start_1.1.5 LEQ and DFE setting
  1350. [ 43.759454] end_1.1.5
  1351. [ 43.770993] start_1.2.1 ForegroundOffsetCal_Manual
  1352. [ 43.780375] end_1.2.1
  1353. [ 43.791390] start_1.2.3 Foreground Calibration
  1354. [ 43.809880] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  1355. [ 43.818569] rtl9300_do_rx_calibration_2_3: end_1.2.3
  1356. [ 43.824090] start_1.4.1
  1357. [ 44.047775] end_1.4.1
  1358. [ 44.050509] start_1.4.2
  1359. [ 44.063037] vth_set_bin = 3
  1360. [ 44.065761] vth_set_bin = 3
  1361. [ 44.069903] Vth Maunal = 0
  1362. [ 44.188815] Tap0 Sign : +
  1363. [ 44.191828] tap0_coef_bin = 21
  1364. [ 44.195728] tap0 manual = 0
  1365. [ 44.205132] end_1.4.2
  1366. [ 44.230231] After calibration - SDS 8 coupling: 0x051f
  1367. [ 44.238490] Forcing SerDes 8 coupling bits to independent mode
  1368. [ 44.250010] Final SDS 8 coupling reg 0x20.18: 0x053f (should be 0x053f)
  1369. [ 44.261402] USXGMII final coupling check for SDS 8:
  1370. [ 44.267856] Reg 0x20.18: 0x053f
  1371. [ 44.272540] Reg 0x21.11: 0x000f
  1372. [ 44.277247] SDS 8 force mode register: 0xd
  1373. [ 44.281803] SDS 8 mode select register: 0x1e
  1374. [ 44.287570] SDS 8 lane coupling reg 0x20.18: 0x053f
  1375. [ 44.293999] SDS 8 analog coupling reg 0x21.11: 0x000f
  1376. [ 44.300835] 8021q: adding VLAN 0 to HW filter on device lan7
  1377. [ 44.371194] rtl83xx-switch switch@1b000000 lan7: Link is Up - 1Gbps/Full - flow control off
  1378. [ 44.381752] switch: port 7(lan7) entered blocking state
  1379. [ 44.387690] switch: port 7(lan7) entered disabled state
  1380. [ 44.393561] rtl83xx-switch switch@1b000000 lan7: entered allmulticast mode
  1381. [ 44.402208] rtl83xx-switch switch@1b000000 lan7: entered promiscuous mode
  1382. [ 44.410145] switch: port 7(lan7) entered blocking state
  1383. [ 44.415985] switch: port 7(lan7) entered forwarding state
  1384. [ 44.462378] Setting up RTL9300 port isolation for independent operation
  1385. [ 44.469840] Port 0: traffic matrix set to 0x1fffffef
  1386. [ 44.475375] Port 1: traffic matrix set to 0x1fffffdf
  1387. [ 44.480952] Port 2: traffic matrix set to 0x1fffffbf
  1388. [ 44.486486] Port 3: traffic matrix set to 0x1fffff7f
  1389. [ 44.492041] Port 4: traffic matrix set to 0x1ffffffe
  1390. [ 44.497608] Port 5: traffic matrix set to 0x1ffffffd
  1391. [ 44.503136] Port 6: traffic matrix set to 0x1ffffffb
  1392. [ 44.508685] Port 7: traffic matrix set to 0x1ffffff7
  1393. [ 44.514212] Port 8: traffic matrix set to 0x1fffffff
  1394. [ 44.519762] Port 9: traffic matrix set to 0x1fffffff
  1395. [ 44.525289] Port 10: traffic matrix set to 0x1fffffff
  1396. [ 44.530936] Port 11: traffic matrix set to 0x1fffffff
  1397. [ 44.536560] Port 12: traffic matrix set to 0x1fffffff
  1398. [ 44.542204] Port 13: traffic matrix set to 0x1fffffff
  1399. [ 44.547866] Port 14: traffic matrix set to 0x1fffffff
  1400. [ 44.553490] Port 15: traffic matrix set to 0x1fffffff
  1401. [ 44.559135] Port 16: traffic matrix set to 0x1fffffff
  1402. [ 44.564760] Port 17: traffic matrix set to 0x1fffffff
  1403. [ 44.570406] Port 18: traffic matrix set to 0x1fffffff
  1404. [ 44.576030] Port 19: traffic matrix set to 0x1fffffff
  1405. [ 44.581685] Port 20: traffic matrix set to 0x1fffffff
  1406. [ 44.587351] Port 21: traffic matrix set to 0x1fffffff
  1407. [ 44.592970] Port 22: traffic matrix set to 0x1fffffff
  1408. [ 44.598615] Port 23: traffic matrix set to 0x1fffffff
  1409. [ 44.604240] Port 24: traffic matrix set to 0x1fffffff
  1410. [ 44.609884] Port 25: traffic matrix set to 0x1fffffff
  1411. [ 44.615509] Port 26: traffic matrix set to 0x1fffffff
  1412. [ 44.621154] Port 27: traffic matrix set to 0x1fffffff
  1413. [ 44.626779] CPU port 28: traffic matrix set to 0xfffffff
  1414. [ 44.632711] === Port Pairing Debug ===
  1415. [ 44.636915] Port 0 traffic matrix: 0x1fffffef
  1416. [ 44.641760] Port 1 traffic matrix: 0x1fffffdf
  1417. [ 44.646596] Port 2 traffic matrix: 0x1fffffbf
  1418. [ 44.651471] Port 3 traffic matrix: 0x1fffff7f
  1419. [ 44.656322] Port 4 traffic matrix: 0x1ffffffe
  1420. [ 44.661195] Port 5 traffic matrix: 0x1ffffffd
  1421. [ 44.666048] Port 6 traffic matrix: 0x1ffffffb
  1422. [ 44.670920] Port 7 traffic matrix: 0x1ffffff7
  1423. [ 44.675773] Port 8 traffic matrix: 0x1fffffff
  1424. [ 44.680649] === MAC Configuration Debug ===
  1425. [ 44.685304] Port 0: MAC_CTRL=0x00000033, FORCE_MODE=0x00000016
  1426. [ 44.691827] Port 1: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1427. [ 44.698360] Port 2: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1428. [ 44.704850] Port 3: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1429. [ 44.711363] Port 4: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1430. [ 44.717884] Port 5: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1431. [ 44.724371] Port 6: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1432. [ 44.730882] Port 7: MAC_CTRL=0x00000000, FORCE_MODE=0x00000194
  1433. [ 44.737403] Port isolation control registers:
  1434. [ 44.742250] Port 0 VLAN_PB: 0x00010004
  1435. [ 44.746409] Port 1 VLAN_PB: 0x00000000
  1436. [ 44.750604] Port 2 VLAN_PB: 0x00000000
  1437. [ 44.754775] Port 3 VLAN_PB: 0x00000000
  1438. [ 44.758968] Port 4 VLAN_PB: 0x00000000
  1439. [ 44.763139] Port 5 VLAN_PB: 0x00000000
  1440. [ 44.767333] Port 6 VLAN_PB: 0x00000000
  1441. [ 44.771503] Port 7 VLAN_PB: 0x00000000
  1442. [ 44.775664] === Trunk/LAG Configuration Debug ===
  1443. [ 44.780924] Trunk mode control: 0x00000000
  1444. [ 44.785477] === Special Configuration Debug ===
  1445. [ 44.790540] Mirror control: 0x00000000
  1446. [ 44.794712] === PHY Polling Debug ===
  1447. [ 44.798817] PHY polling control: 0x0f110101
  1448. [ 44.803471] Port 0: PHY polling ENABLED
  1449. [ 44.807766] Port 8: PHY polling ENABLED
  1450. [ 44.812028] Port 16: PHY polling ENABLED
  1451. [ 44.816380] Port 20: PHY polling ENABLED
  1452. [ 44.820794] Port 24: PHY polling ENABLED
  1453. [ 44.825158] Port 25: PHY polling ENABLED
  1454. [ 44.829574] Port 26: PHY polling ENABLED
  1455. [ 44.833944] Port 27: PHY polling ENABLED
  1456. [ 44.838340] Port 0 SMI config: 0x00000000
  1457. [ 44.842800] Port 1 SMI config: 0x00000400
  1458. [ 44.847284] Port 2 SMI config: 0x00200000
  1459. [ 44.851744] Port 3 SMI config: 0x00000c00
  1460. [ 44.856194] Port 4 SMI config: 0x00018820
  1461. [ 44.860679] Port 5 SMI config: 0x00000000
  1462. [ 44.865138] Port 6 SMI config: 0x00f00000
  1463. [ 44.869622] Port 7 SMI config: 0x00000000
  1464. [ 44.874081] Setting up PHY polling for all ports
  1465. [ 44.879241] PHY polling mask set to: 0x0f110101
  1466. [ 44.884281] === Direct Link Status Debug ===
  1467. [ 44.889055] MAC_LINK_STS register: 0x11000001
  1468. [ 44.893902] Port 0: Link UP (bit 0 set)
  1469. [ 44.898192] Port 24: Link UP (bit 24 set) - PHANTOM!
  1470. [ 44.903713] Port 28: Link UP (bit 28 set) - PHANTOM!
  1471. [ 44.909270] Port 0 speed status: 0x00000002
  1472. [ 44.913922] Port 1 speed status: 0x00000002
  1473. [ 44.918603] Port 2 speed status: 0x00000002
  1474. [ 44.923251] Port 3 speed status: 0x00000002
  1475. [ 44.927928] Port 4 speed status: 0x00000002
  1476. [ 44.932582] Port 5 speed status: 0x00000002
  1477. [ 44.937258] Port 6 speed status: 0x00000002
  1478. [ 44.941912] Port 7 speed status: 0x00000002
  1479. [ 44.946574] rtl83xx-switch switch@1b000000 lan8: configuring for phy/usxgmii link mode
  1480. [ 44.955426] rtl93xx_phylink_mac_config port 27, mode 0, phy-mode usxgmii, speed -1, link 0
  1481. [ 44.964665] rtl93xx_phylink_mac_config SDS is 9
  1482. [ 44.969734] rtl93xx_phylink_mac_config: Configuring port 27 SDS 9 for USXGMII
  1483. [ 44.977704] rtl9300_serdes_setup: port 27, sds 9, mode usxgmii (30)
  1484. [ 44.984683] rtl9300_sds_rst 30
  1485. [ 45.008069] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 9
  1486. [ 45.074252] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  1487. [ 45.081297] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  1488. [ 45.089122] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  1489. [ 45.096220] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  1490. [ 45.103931] rtl9300_phy_enable_10g_1g set medium: 00000002
  1491. [ 45.111070] rtl9300_phy_enable_10g_1g set medium after: 00000002
  1492. [ 45.119784] rtl9300_serdes_mac_link_config: registers before 00000000 00001203
  1493. [ 45.131856] rtl9300_serdes_mac_link_config: registers after 00000000 00001003
  1494. [ 45.139842] rtl9300_force_sds_mode: SDS: 9, mode 30
  1495. [ 45.145270] rtl9300_force_sds_mode: serdes 9 forcing to d
  1496. [ 45.157302] Configuring USXGMII for independent operation on SDS 9
  1497. [ 45.193159] rtl9300_force_sds_mode: serdes 9 forced to d DONE
  1498. [ 45.199588] start_1.1.1 initial value for sds 9
  1499. [ 45.205627] Before calibration - SDS 9 coupling: 0x051f
  1500. [ 45.211466] start_1.1.1 initial value for sds 9
  1501. [ 45.273465] end_1.1.1 --
  1502. [ 45.276288] start_1.1.2 Load DFE init. value
  1503. [ 45.283058] end_1.1.2
  1504. [ 45.285581] start_1.1.3 disable LEQ training,enable DFE clock
  1505. [ 45.303985] end_1.1.3 --
  1506. [ 45.306805] start_1.1.4 offset cali setting
  1507. [ 45.313478] end_1.1.4
  1508. [ 45.316002] start_1.1.5 LEQ and DFE setting
  1509. [ 45.334686] end_1.1.5
  1510. [ 45.346225] start_1.2.1 ForegroundOffsetCal_Manual
  1511. [ 45.355585] end_1.2.1
  1512. [ 45.366594] start_1.2.3 Foreground Calibration
  1513. [ 45.385115] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  1514. [ 45.393816] rtl9300_do_rx_calibration_2_3: end_1.2.3
  1515. [ 45.399376] start_1.4.1
  1516. [ 45.622935] end_1.4.1
  1517. [ 45.625662] start_1.4.2
  1518. [ 45.638204] vth_set_bin = 7
  1519. [ 45.640925] vth_set_bin = 7
  1520. [ 45.645019] Vth Maunal = 0
  1521. [ 45.763920] Tap0 Sign : +
  1522. [ 45.766968] tap0_coef_bin = 0
  1523. [ 45.770875] tap0 manual = 0
  1524. [ 45.780179] end_1.4.2
  1525. [ 45.805281] After calibration - SDS 9 coupling: 0x051f
  1526. [ 45.813546] Forcing SerDes 9 coupling bits to independent mode
  1527. [ 45.825052] Final SDS 9 coupling reg 0x20.18: 0x053f (should be 0x053f)
  1528. [ 45.836442] USXGMII final coupling check for SDS 9:
  1529. [ 45.842900] Reg 0x20.18: 0x053f
  1530. [ 45.847619] Reg 0x21.11: 0x000f
  1531. [ 45.852302] SDS 9 force mode register: 0xd
  1532. [ 45.856885] SDS 9 mode select register: 0x1e
  1533. [ 45.862632] SDS 9 lane coupling reg 0x20.18: 0x053f
  1534. [ 45.869083] SDS 9 analog coupling reg 0x21.11: 0x000f
  1535. [ 45.875888] 8021q: adding VLAN 0 to HW filter on device lan8
  1536. [ 45.951214] rtl83xx-switch switch@1b000000 lan8: Link is Up - 1Gbps/Full - flow control off
  1537. [ 45.961836] switch: port 8(lan8) entered blocking state
  1538. [ 45.967779] switch: port 8(lan8) entered disabled state
  1539. [ 45.973658] rtl83xx-switch switch@1b000000 lan8: entered allmulticast mode
  1540. [ 45.982322] rtl83xx-switch switch@1b000000 lan8: entered promiscuous mode
  1541. [ 45.990261] switch: port 8(lan8) entered blocking state
  1542. [ 45.996108] switch: port 8(lan8) entered forwarding state
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