HW20120326

HW1
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module fadder(input a,b,c,output co,s);
    assign co = a & c | a & b | b & c ;
    assign s = b ^ a ^ c;
endmodule
-----------------------------------------------------------------------
module adder_4bits(input [3:0]a,b,input c,output [3:0]s,output co);
    wire co1,co2,co3;

    fadder bit1(a[0],b[0],c,co1,s[0]);
    fadder bit2(a[1],b[1],co1,co2,s[1]);
    fadder bit3(a[2],b[2],co2,co3,s[2]);
    fadder bit4(a[3],b[3],co3,co,s[3]);
endmodule
-----------------------------------------------------------------------
module sub_4b(input [3:0]x,y,output [3:0]d,output c,co);

assign c = 1 ;
adder_4bits a0(x,~y,c,d,co);

endmodule
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HW2
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module counter_mod7(EN,EVEN,Q,CK);

input CK,EN;
output reg [2:0]Q;
output EVEN;
parameter S0 = 3'b000 ,S1 = 3'b001 ,S2 = 3'b010 ,S3 = 3'b011 ,S4 = 3'b100 ,S5 = 3'b101 ,S6 = 3'b110 ;

assign EVEN = (Q == S0) | (Q == S1) | (Q == S2) | (Q == S3) ;
            //S0 | S1 | S2 | S3 ;

always @(posedge CK)
    begin
        case(Q)
            S0: if(EN) Q <= S1 ;
                else Q <= S0 ;
            S1: if(EN) Q <= S2 ;
                else Q <= S1 ;
            S2: if(EN) Q <= S3 ;
                else Q <= S2 ;
            S3: if(EN) Q <= S4 ;
                else Q <= S3 ;
            S4: if(EN) Q <= S5 ;
                else Q <= S4 ;
            S5: if(EN) Q <= S6 ;
                else Q <= S5 ;
            S6: if(EN) Q <= S0 ;
                else Q <= S6 ;
            default: Q <= S0 ;
        endcase
    end
endmodule