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Oct 16th, 2019
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  1.         else:
  2.             # LiteDRAM port ------------------------------------------------------------------------
  3.             port = self.sdram.crossbar.get_port()
  4.             port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
  5.  
  6.             # Parameters ---------------------------------------------------------------------------
  7.             main_ram_size = 2**(geom_settings.bankbits +
  8.                                 geom_settings.rowbits +
  9.                                 geom_settings.colbits)*phy.settings.databits//8
  10.             main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
  11.             # Register the memory region (so it shows up in generated .h file):
  12.             self.add_memory_region("main_ram", self.mem_map["main_ram"], main_ram_size)
  13.  
  14.             # LiteDRAM AXI port --------------------------------------------------------------------
  15.             # FIXME: figure out how to specify offset here!!!
  16.             axi2native = LiteDRAMAXI2Native(self.cpu.mem_axi, port)
  17.             self.submodules += axi2native
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