task 4

library IEEE;
use IEEE.std_logic_1164.all;
use work.fsm_pkg.all;

architecture behavior of fsm is

signal s_state : fsm_state := START;
signal next_state : fsm_state:=START;
signal next_output : std_logic_vector(1 downto 0):="00";

begin

fsm_seq : process(CLK,RST)
begin
if(RST = '1' and rising_edge(CLK)) then
	s_state <= START;
	OUTPUT<= "00";
elsif rising_edge(CLK) then
s_state <=next_state;
OUTPUT <= next_output;
end if;
end process fsm_seq;

fsm_comb: process(s_state,INPUT)
begin
case s_state is
when START => if(INPUT="00") then
	next_state <=S1;
	next_output<= "11";
end if;
	STATE <= START;

when S1=>if(INPUT="00")then
	next_state <=S0;
	next_output<= "10";
elsif(INPUT="10")then
	next_state<=S2;
	next_output<="00";
end if;
	STATE <=S1;
when S2=>if(INPUT="10")then
	next_state<=S2;
	next_output<="00";
elsif(INPUT="00")then
	next_state<=S1;
	next_output<="01";
	end if;
STATE<=S2;
when S0=>if(INPUT="00")then
	next_state<=S2;
	next_output<="01";
end if;
STATE<=S0;
end case;
end process fsm_comb;


end behavior;