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- Max Delay Paths
- --------------------------------------------------------------------------------------
- Slack (VIOLATED) : -0.288ns (required time - arrival time)
- Source: main_basesoc_soccontroller_reset_re_reg/C
- (rising edge-triggered cell FDRE clocked by main_crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: FD/D
- (rising edge-triggered cell FDRE clocked by clk200_p {rise@0.000ns fall@2.500ns period=5.000ns})
- Path Group: clk200_p
- Path Type: Setup (Max at Slow Process Corner)
- Requirement: 5.000ns (clk200_p rise@5.000ns - main_crg_clkout0 rise@0.000ns)
- Data Path Delay: 0.471ns (logic 0.302ns (64.127%) route 0.169ns (35.873%))
- Logic Levels: 1 (LUT2=1)
- Clock Path Skew: -4.708ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): 4.386ns = ( 9.386 - 5.000 )
- Source Clock Delay (SCD): 9.333ns
- Clock Pessimism Removal (CPR): 0.238ns
- Clock Uncertainty: 0.143ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.071ns
- Discrete Jitter (DJ): 0.113ns
- Phase Error (PE): 0.076ns
- Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
- ------------------------------------------------------------------- -------------------
- (clock main_crg_clkout0 rise edge)
- 0.000 0.000 r
- AD12 0.000 0.000 r clk200_p (IN)
- net (fo=0) 0.000 0.000 clk200_p
- AD12 IBUFDS (Prop_ibufds_I_O) 0.906 0.906 r IBUFDS/O
- net (fo=1, routed) 2.299 3.205 main_crg_clkin
- BUFGCTRL_X0Y6 BUFG (Prop_bufg_I_O) 0.093 3.298 r main_crg_clkin_BUFG_inst/O
- net (fo=9, routed) 1.936 5.234 main_crg_clkin_BUFG
- MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
- 0.077 5.311 r MMCME2_ADV/CLKOUT0
- net (fo=1, routed) 2.469 7.780 main_crg_clkout0
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 7.873 r BUFG/O
- net (fo=6449, routed) 1.460 9.333 sys_clk
- SLICE_X122Y134 FDRE r main_basesoc_soccontroller_reset_re_reg/C
- ------------------------------------------------------------------- -------------------
- SLICE_X122Y134 FDRE (Prop_fdre_C_Q) 0.259 9.592 r main_basesoc_soccontroller_reset_re_reg/Q
- net (fo=3, routed) 0.169 9.761 main_basesoc_soccontroller_reset
- SLICE_X123Y134 LUT2 (Prop_lut2_I0_O) 0.043 9.804 r FD_i_1/O
- net (fo=1, routed) 0.000 9.804 main_crg_reset
- SLICE_X123Y134 FDRE r FD/D
- ------------------------------------------------------------------- -------------------
- (clock clk200_p rise edge)
- 5.000 5.000 r
- AD12 0.000 5.000 r clk200_p (IN)
- net (fo=0) 0.000 5.000 clk200_p
- AD12 IBUFDS (Prop_ibufds_I_O) 0.803 5.803 r IBUFDS/O
- net (fo=1, routed) 2.173 7.976 main_crg_clkin
- BUFGCTRL_X0Y6 BUFG (Prop_bufg_I_O) 0.083 8.059 r main_crg_clkin_BUFG_inst/O
- net (fo=9, routed) 1.327 9.386 main_crg_clkin_BUFG
- SLICE_X123Y134 FDRE r FD/C
- clock pessimism 0.238 9.625
- clock uncertainty -0.143 9.482
- SLICE_X123Y134 FDRE (Setup_fdre_C_D) 0.034 9.516 FD
- -------------------------------------------------------------------
- required time 9.516
- arrival time -9.804
- -------------------------------------------------------------------
- slack -0.288
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