library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.to_unsigned;

entity Timer is
	port( S, U : in std_logic;
			LT, LS, LD, LJ : out std_logic_vector(3 downto 0) );
end Timer;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.to_unsigned;

entity Licznik is
	port( Clk, Sh : in std_logic;
			LT, LS, LD, LJ : out std_logic_vector(3 downto 0);
			R : out std_logic);
end Licznik;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity Detektor is
	port( U : in std_logic;
			U10 : out std_logic);
end Detektor;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity Sygnaly is
	port( S, U, U10 : in std_logic;
			R : inout std_logic;
			Clk, Sh : buffer std_logic);
end Sygnaly;



architecture struktura of Timer is
component Sygnaly
	port( S, U, U10 : in std_logic;
			R : inout std_logic;
			Clk, Sh : buffer std_logic);
end component;

component Detektor is
	port( U : in std_logic;
			U10 : out std_logic);
end component;

component Licznik is
	port( Clk, Sh : in std_logic;
			LT, LS, LD, LJ : out std_logic_vector(3 downto 0);
			R : out std_logic);
end component;

signal Clk, R, U10, Sh : std_logic;

begin
	Struct1: Sygnaly port map(S, U, U10, R, Clk, Sh);
	Struct2: Detektor port map(U, U10);
	Struct3: Licznik port map(Clk, Sh, LT, LS, LD, LJ, R);
end struktura;

architecture tablicowa of Licznik is
type liczba is array(0 to 3) of integer range 0 to 9;
begin
	process(Clk)
	variable tablica : liczba := (0,0,0,0);
	begin
		if Clk'event and Clk = '1' then
			if Sh = '0' then -- tutaj lecimy w gore
				for i in 3 downto 0 loop
					if not (tablica(i) = 9) then
						tablica(i) := tablica(i) + 1;
						exit;
					else tablica(i) := 0;
					end if;
				end loop;
				-- if tablica(0) = 9 and tablica(1) = 9 and tablica(2) = 9 and tablica(3) = 9 then ;
			LT <= std_logic_vector(to_unsigned(tablica(0), LT'length));
			LS <= std_logic_vector(to_unsigned(tablica(1), LS'length));
			LD <= std_logic_vector(to_unsigned(tablica(2), LD'length));
			LJ <= std_logic_vector(to_unsigned(tablica(3), LJ'length));

			else
				if not (tablica(0) = 0 and tablica(1) = 0 and tablica(2) = 0 and tablica(3) = 0) then
					for i in 3 downto 0 loop
						if not (tablica(i) = 0) then
							tablica(i) := tablica(i) - 1;
							exit;
						else tablica(i) := 9;
						-- wpisac cos na 9 9 9 9
						end if;
					end loop;
				LT <= std_logic_vector(to_unsigned(tablica(0), LT'length));
				LS <= std_logic_vector(to_unsigned(tablica(1), LS'length));
				LD <= std_logic_vector(to_unsigned(tablica(2), LD'length));
				LJ <= std_logic_vector(to_unsigned(tablica(3), LJ'length));
				else R <= '1';
				end if;
			end if;
		end if;
	end process;
end tablicowa;

architecture Detektor10Hz of Detektor is
	begin
	process
	variable flaga : boolean;
	begin
		if U = '0' then
		flaga := true;
			for i in 0 to 30 loop
				if U = '0' then
					wait for 10 ms;
				else
					flaga := false;
					exit;
				end if;
			end loop;

			if flaga = true then
				U10 <= '1';
				wait until U = '1';
				U10 <= '0';
				wait for 5 ms;
			end if;
		end if;
	end process;
end Detektor10Hz;

architecture sygnaly of Sygnaly is
begin
	process
	begin
	if S = '0' then
		Sh <= '1';
	end if;

	if R = '1' then
		Sh <= '0';
		R <= '0';
	end if;

	if Sh = '1' then
		Clk <= '1';
		wait for 500 ms;
		Clk <= '0';
		wait for 500 ms;
	end if;

	if U'event and U = '0' then
		Clk <= '1';
		Clk <= '0';
		wait for 5 ms;
	end if;

	if U10 = '1' then
		Clk <= '1';
		wait for 50 ms;
		Clk <= '0';
		wait for 50 ms;
	end if;
	end process;
end sygnaly;