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  1. /*
  2. * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42.  
  43. #include "skeleton.dtsi"
  44.  
  45. #include <dt-bindings/clock/sun8i-h3-ccu.h>
  46. #include <dt-bindings/interrupt-controller/arm-gic.h>
  47. #include <dt-bindings/pinctrl/sun4i-a10.h>
  48. #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49.  
  50. / {
  51. interrupt-parent = <&gic>;
  52.  
  53. cpus {
  54. #address-cells = <1>;
  55. #size-cells = <0>;
  56.  
  57. cpu@0 {
  58. compatible = "arm,cortex-a7";
  59. device_type = "cpu";
  60. reg = <0>;
  61. };
  62.  
  63. cpu@1 {
  64. compatible = "arm,cortex-a7";
  65. device_type = "cpu";
  66. reg = <1>;
  67. };
  68.  
  69. cpu@2 {
  70. compatible = "arm,cortex-a7";
  71. device_type = "cpu";
  72. reg = <2>;
  73. };
  74.  
  75. cpu@3 {
  76. compatible = "arm,cortex-a7";
  77. device_type = "cpu";
  78. reg = <3>;
  79. };
  80. };
  81.  
  82. timer {
  83. compatible = "arm,armv7-timer";
  84. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  85. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  86. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  87. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  88. };
  89.  
  90. clocks {
  91. #address-cells = <1>;
  92. #size-cells = <1>;
  93. ranges;
  94.  
  95. osc24M: osc24M_clk {
  96. #clock-cells = <0>;
  97. compatible = "fixed-clock";
  98. clock-frequency = <24000000>;
  99. clock-output-names = "osc24M";
  100. };
  101.  
  102. osc32k: osc32k_clk {
  103. #clock-cells = <0>;
  104. compatible = "fixed-clock";
  105. clock-frequency = <32768>;
  106. clock-output-names = "osc32k";
  107. };
  108.  
  109. apb0: apb0_clk {
  110. compatible = "fixed-factor-clock";
  111. #clock-cells = <0>;
  112. clock-div = <1>;
  113. clock-mult = <1>;
  114. clocks = <&osc24M>;
  115. clock-output-names = "apb0";
  116. };
  117.  
  118. apb0_gates: clk@01f01428 {
  119. compatible = "allwinner,sun8i-h3-apb0-gates-clk",
  120. "allwinner,sun4i-a10-gates-clk";
  121. reg = <0x01f01428 0x4>;
  122. #clock-cells = <1>;
  123. clocks = <&apb0>;
  124. clock-indices = <0>, <1>;
  125. clock-output-names = "apb0_pio", "apb0_ir";
  126. };
  127.  
  128. ir_clk: ir_clk@01f01454 {
  129. compatible = "allwinner,sun4i-a10-mod0-clk";
  130. reg = <0x01f01454 0x4>;
  131. #clock-cells = <0>;
  132. clocks = <&osc32k>, <&osc24M>;
  133. clock-output-names = "ir";
  134. };
  135. };
  136.  
  137. soc {
  138. compatible = "simple-bus";
  139. #address-cells = <1>;
  140. #size-cells = <1>;
  141. ranges;
  142.  
  143. dma: dma-controller@01c02000 {
  144. compatible = "allwinner,sun8i-h3-dma";
  145. reg = <0x01c02000 0x1000>;
  146. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  147. clocks = <&ccu CLK_BUS_DMA>;
  148. resets = <&ccu RST_BUS_DMA>;
  149. #dma-cells = <1>;
  150. };
  151.  
  152. mmc0: mmc@01c0f000 {
  153. compatible = "allwinner,sun7i-a20-mmc";
  154. reg = <0x01c0f000 0x1000>;
  155. clocks = <&ccu CLK_BUS_MMC0>,
  156. <&ccu CLK_MMC0>,
  157. <&ccu CLK_MMC0_OUTPUT>,
  158. <&ccu CLK_MMC0_SAMPLE>;
  159. clock-names = "ahb",
  160. "mmc",
  161. "output",
  162. "sample";
  163. resets = <&ccu RST_BUS_MMC0>;
  164. reset-names = "ahb";
  165. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  166. status = "disabled";
  167. #address-cells = <1>;
  168. #size-cells = <0>;
  169. };
  170.  
  171. mmc1: mmc@01c10000 {
  172. compatible = "allwinner,sun7i-a20-mmc";
  173. reg = <0x01c10000 0x1000>;
  174. clocks = <&ccu CLK_BUS_MMC1>,
  175. <&ccu CLK_MMC1>,
  176. <&ccu CLK_MMC1_OUTPUT>,
  177. <&ccu CLK_MMC1_SAMPLE>;
  178. clock-names = "ahb",
  179. "mmc",
  180. "output",
  181. "sample";
  182. resets = <&ccu RST_BUS_MMC1>;
  183. reset-names = "ahb";
  184. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  185. status = "disabled";
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. };
  189.  
  190. mmc2: mmc@01c11000 {
  191. compatible = "allwinner,sun7i-a20-mmc";
  192. reg = <0x01c11000 0x1000>;
  193. clocks = <&ccu CLK_BUS_MMC2>,
  194. <&ccu CLK_MMC2>,
  195. <&ccu CLK_MMC2_OUTPUT>,
  196. <&ccu CLK_MMC2_SAMPLE>;
  197. clock-names = "ahb",
  198. "mmc",
  199. "output",
  200. "sample";
  201. resets = <&ccu RST_BUS_MMC2>;
  202. reset-names = "ahb";
  203. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  204. status = "disabled";
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. };
  208.  
  209. usbphy: phy@01c19400 {
  210. compatible = "allwinner,sun8i-h3-usb-phy";
  211. reg = <0x01c19400 0x2c>,
  212. <0x01c1a800 0x4>,
  213. <0x01c1b800 0x4>,
  214. <0x01c1c800 0x4>,
  215. <0x01c1d800 0x4>;
  216. reg-names = "phy_ctrl",
  217. "pmu0",
  218. "pmu1",
  219. "pmu2",
  220. "pmu3";
  221. clocks = <&ccu CLK_USB_PHY0>,
  222. <&ccu CLK_USB_PHY1>,
  223. <&ccu CLK_USB_PHY2>,
  224. <&ccu CLK_USB_PHY3>;
  225. clock-names = "usb0_phy",
  226. "usb1_phy",
  227. "usb2_phy",
  228. "usb3_phy";
  229. resets = <&ccu RST_USB_PHY0>,
  230. <&ccu RST_USB_PHY1>,
  231. <&ccu RST_USB_PHY2>,
  232. <&ccu RST_USB_PHY3>;
  233. reset-names = "usb0_reset",
  234. "usb1_reset",
  235. "usb2_reset",
  236. "usb3_reset";
  237. status = "disabled";
  238. #phy-cells = <1>;
  239. };
  240.  
  241. ehci1: usb@01c1b000 {
  242. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  243. reg = <0x01c1b000 0x100>;
  244. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  245. clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
  246. resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
  247. phys = <&usbphy 1>;
  248. phy-names = "usb";
  249. status = "disabled";
  250. };
  251.  
  252. ohci1: usb@01c1b400 {
  253. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  254. reg = <0x01c1b400 0x100>;
  255. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  256. clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
  257. <&ccu CLK_USB_OHCI1>;
  258. resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
  259. phys = <&usbphy 1>;
  260. phy-names = "usb";
  261. status = "disabled";
  262. };
  263.  
  264. ehci2: usb@01c1c000 {
  265. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  266. reg = <0x01c1c000 0x100>;
  267. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  268. clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
  269. resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
  270. phys = <&usbphy 2>;
  271. phy-names = "usb";
  272. status = "disabled";
  273. };
  274.  
  275. ohci2: usb@01c1c400 {
  276. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  277. reg = <0x01c1c400 0x100>;
  278. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  279. clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
  280. <&ccu CLK_USB_OHCI2>;
  281. resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
  282. phys = <&usbphy 2>;
  283. phy-names = "usb";
  284. status = "disabled";
  285. };
  286.  
  287. ehci3: usb@01c1d000 {
  288. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  289. reg = <0x01c1d000 0x100>;
  290. interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
  291. clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
  292. resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
  293. phys = <&usbphy 3>;
  294. phy-names = "usb";
  295. status = "disabled";
  296. };
  297.  
  298. ohci3: usb@01c1d400 {
  299. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  300. reg = <0x01c1d400 0x100>;
  301. interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  302. clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
  303. <&ccu CLK_USB_OHCI3>;
  304. resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
  305. phys = <&usbphy 3>;
  306. phy-names = "usb";
  307. status = "disabled";
  308. };
  309.  
  310. ccu: clock@01c20000 {
  311. compatible = "allwinner,sun8i-h3-ccu";
  312. reg = <0x01c20000 0x400>;
  313. clocks = <&osc24M>, <&osc32k>;
  314. clock-names = "hosc", "losc";
  315. #clock-cells = <1>;
  316. #reset-cells = <1>;
  317. };
  318.  
  319. pio: pinctrl@01c20800 {
  320. compatible = "allwinner,sun8i-h3-pinctrl";
  321. reg = <0x01c20800 0x400>;
  322. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  323. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  324. clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
  325. clock-names = "apb", "hosc", "losc";
  326. gpio-controller;
  327. #gpio-cells = <3>;
  328. interrupt-controller;
  329. #interrupt-cells = <3>;
  330.  
  331. i2c0_pins: i2c0 {
  332. allwinner,pins = "PA11", "PA12";
  333. allwinner,function = "i2c0";
  334. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  335. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  336. };
  337.  
  338. i2c1_pins: i2c1 {
  339. allwinner,pins = "PA18", "PA19";
  340. allwinner,function = "i2c1";
  341. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  342. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  343. };
  344.  
  345. i2c2_pins: i2c2 {
  346. allwinner,pins = "PE12", "PE13";
  347. allwinner,function = "i2c2";
  348. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  349. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  350. };
  351.  
  352. mmc0_pins_a: mmc0@0 {
  353. allwinner,pins = "PF0", "PF1", "PF2", "PF3",
  354. "PF4", "PF5";
  355. allwinner,function = "mmc0";
  356. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  357. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  358. };
  359.  
  360. mmc0_cd_pin: mmc0_cd_pin@0 {
  361. allwinner,pins = "PF6";
  362. allwinner,function = "gpio_in";
  363. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  364. allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  365. };
  366.  
  367. mmc1_pins_a: mmc1@0 {
  368. allwinner,pins = "PG0", "PG1", "PG2", "PG3",
  369. "PG4", "PG5";
  370. allwinner,function = "mmc1";
  371. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  372. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  373. };
  374.  
  375. mmc2_8bit_pins: mmc2_8bit {
  376. allwinner,pins = "PC5", "PC6", "PC8",
  377. "PC9", "PC10", "PC11",
  378. "PC12", "PC13", "PC14",
  379. "PC15", "PC16";
  380. allwinner,function = "mmc2";
  381. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  382. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  383. };
  384.  
  385. spi0_pins: spi0 {
  386. allwinner,pins = "PC0", "PC1", "PC2", "PC3";
  387. allwinner,function = "spi0";
  388. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  389. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  390. };
  391.  
  392. spi1_pins: spi1 {
  393. allwinner,pins = "PA15", "PA16", "PA14", "PA13";
  394. allwinner,function = "spi1";
  395. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  396. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  397. };
  398.  
  399. uart0_pins_a: uart0@0 {
  400. allwinner,pins = "PA4", "PA5";
  401. allwinner,function = "uart0";
  402. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  403. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  404. };
  405.  
  406. uart1_pins: uart1 {
  407. allwinner,pins = "PG6", "PG7";
  408. allwinner,function = "uart1";
  409. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  410. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  411. };
  412.  
  413. uart1_rts_cts_pins: uart1_rts_cts {
  414. allwinner,pins = "PG8", "PG9";
  415. allwinner,function = "uart1";
  416. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  417. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  418. };
  419.  
  420. uart2_pins: uart2 {
  421. allwinner,pins = "PA0", "PA1";
  422. allwinner,function = "uart2";
  423. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  424. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  425. };
  426.  
  427. uart3_pins: uart3 {
  428. allwinner,pins = "PA13", "PA14";
  429. allwinner,function = "uart3";
  430. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  431. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  432. };
  433. };
  434.  
  435. timer@01c20c00 {
  436. compatible = "allwinner,sun4i-a10-timer";
  437. reg = <0x01c20c00 0xa0>;
  438. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  439. <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  440. clocks = <&osc24M>;
  441. };
  442.  
  443. spi0: spi@01c68000 {
  444. compatible = "allwinner,sun8i-h3-spi";
  445. reg = <0x01c68000 0x1000>;
  446. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  447. clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
  448. clock-names = "ahb", "mod";
  449. dmas = <&dma 23>, <&dma 23>;
  450. dma-names = "rx", "tx";
  451. pinctrl-names = "default";
  452. pinctrl-0 = <&spi0_pins>;
  453. resets = <&ccu RST_BUS_SPI0>;
  454. status = "disabled";
  455. #address-cells = <1>;
  456. #size-cells = <0>;
  457. };
  458.  
  459. spi1: spi@01c69000 {
  460. compatible = "allwinner,sun8i-h3-spi";
  461. reg = <0x01c69000 0x1000>;
  462. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  463. clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
  464. clock-names = "ahb", "mod";
  465. dmas = <&dma 24>, <&dma 24>;
  466. dma-names = "rx", "tx";
  467. pinctrl-names = "default";
  468. pinctrl-0 = <&spi1_pins>;
  469. resets = <&ccu RST_BUS_SPI1>;
  470. status = "disabled";
  471. #address-cells = <1>;
  472. #size-cells = <0>;
  473. };
  474.  
  475. wdt0: watchdog@01c20ca0 {
  476. compatible = "allwinner,sun6i-a31-wdt";
  477. reg = <0x01c20ca0 0x20>;
  478. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  479. };
  480.  
  481. codec: codec@01c22c00 {
  482. #sound-dai-cells = <0>;
  483. compatible = "allwinner,sun8i-h3-codec";
  484. reg = <0x01c22c00 0x400>;
  485. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  486. clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
  487. clock-names = "apb", "codec";
  488. resets = <&ccu RST_BUS_CODEC>;
  489. dmas = <&dma 15>, <&dma 15>;
  490. dma-names = "rx", "tx";
  491. allwinner,codec-analog-controls = <&codec_analog>;
  492. status = "disabled";
  493. };
  494.  
  495. pwm: pwm@01c21400 {
  496. compatible = "allwinner,sun8i-h3-pwm";
  497. reg = <0x01c21400 0x8>;
  498. clocks = <&osc24M>;
  499. #pwm-cells = <3>;
  500. status = "disabled";
  501. };
  502.  
  503. uart0: serial@01c28000 {
  504. compatible = "snps,dw-apb-uart";
  505. reg = <0x01c28000 0x400>;
  506. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  507. reg-shift = <2>;
  508. reg-io-width = <4>;
  509. clocks = <&ccu CLK_BUS_UART0>;
  510. resets = <&ccu RST_BUS_UART0>;
  511. dmas = <&dma 6>, <&dma 6>;
  512. dma-names = "rx", "tx";
  513. status = "disabled";
  514. };
  515.  
  516. uart1: serial@01c28400 {
  517. compatible = "snps,dw-apb-uart";
  518. reg = <0x01c28400 0x400>;
  519. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  520. reg-shift = <2>;
  521. reg-io-width = <4>;
  522. clocks = <&ccu CLK_BUS_UART1>;
  523. resets = <&ccu RST_BUS_UART1>;
  524. dmas = <&dma 7>, <&dma 7>;
  525. dma-names = "rx", "tx";
  526. status = "disabled";
  527. };
  528.  
  529. uart2: serial@01c28800 {
  530. compatible = "snps,dw-apb-uart";
  531. reg = <0x01c28800 0x400>;
  532. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  533. reg-shift = <2>;
  534. reg-io-width = <4>;
  535. clocks = <&ccu CLK_BUS_UART2>;
  536. resets = <&ccu RST_BUS_UART2>;
  537. dmas = <&dma 8>, <&dma 8>;
  538. dma-names = "rx", "tx";
  539. status = "disabled";
  540. };
  541.  
  542. uart3: serial@01c28c00 {
  543. compatible = "snps,dw-apb-uart";
  544. reg = <0x01c28c00 0x400>;
  545. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  546. reg-shift = <2>;
  547. reg-io-width = <4>;
  548. clocks = <&ccu CLK_BUS_UART3>;
  549. resets = <&ccu RST_BUS_UART3>;
  550. dmas = <&dma 9>, <&dma 9>;
  551. dma-names = "rx", "tx";
  552. status = "disabled";
  553. };
  554.  
  555. i2c0: i2c@01c2ac00 {
  556. compatible = "allwinner,sun6i-a31-i2c";
  557. reg = <0x01c2ac00 0x400>;
  558. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  559. clocks = <&ccu CLK_BUS_I2C0>;
  560. resets = <&ccu RST_BUS_I2C0>;
  561. pinctrl-names = "default";
  562. pinctrl-0 = <&i2c0_pins>;
  563. status = "disabled";
  564. #address-cells = <1>;
  565. #size-cells = <0>;
  566. };
  567.  
  568. i2c1: i2c@01c2b000 {
  569. compatible = "allwinner,sun6i-a31-i2c";
  570. reg = <0x01c2b000 0x400>;
  571. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  572. clocks = <&ccu CLK_BUS_I2C1>;
  573. resets = <&ccu RST_BUS_I2C1>;
  574. pinctrl-names = "default";
  575. pinctrl-0 = <&i2c1_pins>;
  576. status = "disabled";
  577. #address-cells = <1>;
  578. #size-cells = <0>;
  579. };
  580.  
  581. i2c2: i2c@01c2b400 {
  582. compatible = "allwinner,sun6i-a31-i2c";
  583. reg = <0x01c2b000 0x400>;
  584. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  585. clocks = <&ccu CLK_BUS_I2C2>;
  586. resets = <&ccu RST_BUS_I2C2>;
  587. pinctrl-names = "default";
  588. pinctrl-0 = <&i2c2_pins>;
  589. status = "disabled";
  590. #address-cells = <1>;
  591. #size-cells = <0>;
  592. };
  593.  
  594. gic: interrupt-controller@01c81000 {
  595. compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  596. reg = <0x01c81000 0x1000>,
  597. <0x01c82000 0x1000>,
  598. <0x01c84000 0x2000>,
  599. <0x01c86000 0x2000>;
  600. interrupt-controller;
  601. #interrupt-cells = <3>;
  602. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  603. };
  604.  
  605. rtc: rtc@01f00000 {
  606. compatible = "allwinner,sun6i-a31-rtc";
  607. reg = <0x01f00000 0x54>;
  608. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  609. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  610. };
  611.  
  612. apb0_reset: reset@01f014b0 {
  613. reg = <0x01f014b0 0x4>;
  614. compatible = "allwinner,sun6i-a31-clock-reset";
  615. #reset-cells = <1>;
  616. };
  617.  
  618. codec_analog: codec-analog@01f015c0 {
  619. compatible = "allwinner,sun8i-h3-codec-analog";
  620. reg = <0x01f015c0 0x4>;
  621. };
  622.  
  623. ir: ir@01f02000 {
  624. compatible = "allwinner,sun5i-a13-ir";
  625. clocks = <&apb0_gates 1>, <&ir_clk>;
  626. clock-names = "apb", "ir";
  627. resets = <&apb0_reset 1>;
  628. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  629. reg = <0x01f02000 0x40>;
  630. status = "disabled";
  631. };
  632.  
  633. r_pio: pinctrl@01f02c00 {
  634. compatible = "allwinner,sun8i-h3-r-pinctrl";
  635. reg = <0x01f02c00 0x400>;
  636. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  637. clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
  638. clock-names = "apb", "hosc", "losc";
  639. resets = <&apb0_reset 0>;
  640. gpio-controller;
  641. #gpio-cells = <3>;
  642. interrupt-controller;
  643. #interrupt-cells = <3>;
  644.  
  645. ir_pins_a: ir@0 {
  646. allwinner,pins = "PL11";
  647. allwinner,function = "s_cir_rx";
  648. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  649. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  650. };
  651. };
  652. };
  653. };
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