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  1. coreboot-4.7-347-ga3bbe88f74-dirty Fri Feb 23 09:48:17 UTC 2018 romstage starting...
  2. console init done.
  3.  
  4. Intel(R) 82945GC Chipset
  5. (G)MCH capable of up to DDR2-667
  6. Setting up static southbridge registers... RCBA done .... PMBASE done .... ACPI_CNTL: Enable ACPI BAR ... done DEFAULT_GPIOBASE | 1 ... done GC enable GPIOs , done done.
  7. Disabling Watchdog reboot... done.
  8. Setting up static northbridge registers... EPBAR, DEFAULT_EPBAR | 1 .... done MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1 ... done DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1 ... done X60BAR, DEFAULT_X60BAR | 1 ... done done.
  9. Waiting for MCHBAR to come up...ok
  10. PM1_CNT: 00001c00
  11. Enable SPD ROMs and DDR-II DRAM
  12. SMBus controller enabled.
  13. Setting up RAM controller.
  14. This mainboard supports Dual Channel Operation.
  15. Reading SPD using i2c block operation.
  16. fefffd84: 80 08 08 0e 0a 61 40 00 05 25 40 00 82 08 00 00 .....a@..%@.....
  17. fefffd94: 0c 08 70 01 02 00 03 30 45 3d 50 3c 1e 3c 2d 01 ..p....0E=P<.<-.
  18. fefffda4: 17 25 05 12 3c 1e 1e 00 06 3c 7f 80 14 1e 00 00 .%..<....<......
  19. fefffdb4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 dd ................
  20. EEPROM with 0x0100 bytes
  21. SPD contains 0x80 bytes
  22. Revision : 1.2
  23. Type : 0x08
  24. Rows : 14
  25. Columns : 10
  26. Ranks : 2
  27. Module data width : x64
  28. SDRAM width : x8
  29. Banks : 8
  30. Voltage : 1.8V
  31. Supported CAS mask : 0x70
  32. Capacity : 2 GB
  33. The assembly supports self refresh: true
  34. General features : 50Ohm WEAK_DRIVER
  35. Burst length : BL8
  36. Dimm type : 2
  37. ECC support : 0
  38. Package : planar
  39. Manufacturer ID : 0
  40. Part number :
  41. Date : 2000 week 0
  42. Serial number : 0x00000000
  43. Row addr bits : 14
  44. Column addr bits : 10
  45. Number of ranks : 2
  46. DIMM Capacity : 2048 MB
  47. Width : x8
  48. Banks : 8
  49. CAS latencies : 4 5 6
  50. tCK at CL4 : 3.750 ns
  51. tAC at CL4 : 0.500 ns
  52. tCK at CL5 : 3.000 ns
  53. tAC at CL5 : 0.449 ns
  54. tCK at CL6 : 2.500 ns
  55. tAC at CL6 : 0.398 ns
  56. tCKmax : 0.796 ns
  57. tWRmin : 15.000 ns
  58. tRCDmin : 15.000 ns
  59. tRRDmin : 7.500 ns
  60. tRPmin : 15.000 ns
  61. tRASmin : 45.000 ns
  62. tRCmin : 60.000 ns
  63. tRFCmin : 127.500 ns
  64. tWTRmin : 7.500 ns
  65. tRTPmin : 7.500 ns
  66. tDS : 0.046 ns
  67. tDH : 0.117 ns
  68. tDQSQmax : 0.199 ns
  69. tQHSmax : 0.296 ns
  70. tPLL : 0.000 us
  71. tRR : 7812.500 us
  72. DDR II Channel 0 Socket 0: x8DDS
  73. DIMM 0 side 0 = 1024 MB
  74. DIMM 0 side 1 = 1024 MB
  75. Reading SPD using i2c block operation.
  76. fefffd84: 80 08 08 0e 0a 61 40 00 05 30 45 00 82 08 00 00 .....a@..0E.....
  77. fefffd94: 0c 04 30 03 02 00 03 3d 50 00 00 3c 1e 3c 2d 80 ..0....=P..<.<-.
  78. fefffda4: 20 27 10 17 3c 1e 1e 00 00 37 69 80 18 22 00 00 '..<....7i.."..
  79. fefffdb4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 b7 ................
  80. EEPROM with 0x0100 bytes
  81. SPD contains 0x80 bytes
  82. Revision : 1.2
  83. Type : 0x08
  84. Rows : 14
  85. Columns : 10
  86. Ranks : 2
  87. Module data width : x64
  88. SDRAM width : x8
  89. Banks : 4
  90. Voltage : 1.8V
  91. Supported CAS mask : 0x30
  92. Capacity : 1 GB
  93. The assembly supports self refresh: true
  94. General features : 50Ohm WEAK_DRIVER
  95. Burst length : BL8
  96. Dimm type : 2
  97. ECC support : 0
  98. Package : planar
  99. Manufacturer ID : 0
  100. Part number :
  101. Date : 2000 week 0
  102. Serial number : 0x00000000
  103. Row addr bits : 14
  104. Column addr bits : 10
  105. Number of ranks : 2
  106. DIMM Capacity : 1024 MB
  107. Width : x8
  108. Banks : 4
  109. CAS latencies : 4 5
  110. tCK at CL4 : 3.750 ns
  111. tAC at CL4 : 0.500 ns
  112. tCK at CL5 : 3.000 ns
  113. tAC at CL5 : 0.449 ns
  114. tCKmax : 0.796 ns
  115. tWRmin : 15.000 ns
  116. tRCDmin : 15.000 ns
  117. tRRDmin : 7.500 ns
  118. tRPmin : 15.000 ns
  119. tRASmin : 45.000 ns
  120. tRCmin : 55.000 ns
  121. tRFCmin : 105.000 ns
  122. tWTRmin : 7.500 ns
  123. tRTPmin : 7.500 ns
  124. tDS : 0.097 ns
  125. tDH : 0.167 ns
  126. tDQSQmax : 0.238 ns
  127. tQHSmax : 0.339 ns
  128. tPLL : 0.000 us
  129. tRR : 7812.500 us
  130. DDR II Channel 0 Socket 1: x8DDS
  131. DIMM 1 side 0 = 512 MB
  132. DIMM 1 side 1 = 512 MB
  133. Reading SPD using i2c block operation.
  134. fefffd84: 80 08 08 0e 0a 61 40 00 05 25 40 00 82 08 00 00 .....a@..%@.....
  135. fefffd94: 0c 08 70 01 02 00 03 30 45 3d 50 3c 1e 3c 2d 01 ..p....0E=P<.<-.
  136. fefffda4: 17 25 05 12 3c 1e 1e 00 06 3c 7f 80 14 1e 00 00 .%..<....<......
  137. fefffdb4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 dd ................
  138. EEPROM with 0x0100 bytes
  139. SPD contains 0x80 bytes
  140. Revision : 1.2
  141. Type : 0x08
  142. Rows : 14
  143. Columns : 10
  144. Ranks : 2
  145. Module data width : x64
  146. SDRAM width : x8
  147. Banks : 8
  148. Voltage : 1.8V
  149. Supported CAS mask : 0x70
  150. Capacity : 2 GB
  151. The assembly supports self refresh: true
  152. General features : 50Ohm WEAK_DRIVER
  153. Burst length : BL8
  154. Dimm type : 2
  155. ECC support : 0
  156. Package : planar
  157. Manufacturer ID : 0
  158. Part number :
  159. Date : 2000 week 0
  160. Serial number : 0x00000000
  161. Row addr bits : 14
  162. Column addr bits : 10
  163. Number of ranks : 2
  164. DIMM Capacity : 2048 MB
  165. Width : x8
  166. Banks : 8
  167. CAS latencies : 4 5 6
  168. tCK at CL4 : 3.750 ns
  169. tAC at CL4 : 0.500 ns
  170. tCK at CL5 : 3.000 ns
  171. tAC at CL5 : 0.449 ns
  172. tCK at CL6 : 2.500 ns
  173. tAC at CL6 : 0.398 ns
  174. tCKmax : 0.796 ns
  175. tWRmin : 15.000 ns
  176. tRCDmin : 15.000 ns
  177. tRRDmin : 7.500 ns
  178. tRPmin : 15.000 ns
  179. tRASmin : 45.000 ns
  180. tRCmin : 60.000 ns
  181. tRFCmin : 127.500 ns
  182. tWTRmin : 7.500 ns
  183. tRTPmin : 7.500 ns
  184. tDS : 0.046 ns
  185. tDH : 0.117 ns
  186. tDQSQmax : 0.199 ns
  187. tQHSmax : 0.296 ns
  188. tPLL : 0.000 us
  189. tRR : 7812.500 us
  190. DDR II Channel 1 Socket 0: x8DDS
  191. DIMM 2 side 0 = 1024 MB
  192. DIMM 2 side 1 = 1024 MB
  193. Reading SPD using i2c block operation.
  194. fefffd84: 80 08 08 0e 0a 61 40 00 05 30 45 00 82 08 00 00 .....a@..0E.....
  195. fefffd94: 0c 04 30 03 02 00 03 3d 50 00 00 3c 1e 3c 2d 80 ..0....=P..<.<-.
  196. fefffda4: 20 27 10 17 3c 1e 1e 00 00 37 69 80 18 22 00 00 '..<....7i.."..
  197. fefffdb4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 b7 ................
  198. EEPROM with 0x0100 bytes
  199. SPD contains 0x80 bytes
  200. Revision : 1.2
  201. Type : 0x08
  202. Rows : 14
  203. Columns : 10
  204. Ranks : 2
  205. Module data width : x64
  206. SDRAM width : x8
  207. Banks : 4
  208. Voltage : 1.8V
  209. Supported CAS mask : 0x30
  210. Capacity : 1 GB
  211. The assembly supports self refresh: true
  212. General features : 50Ohm WEAK_DRIVER
  213. Burst length : BL8
  214. Dimm type : 2
  215. ECC support : 0
  216. Package : planar
  217. Manufacturer ID : 0
  218. Part number :
  219. Date : 2000 week 0
  220. Serial number : 0x00000000
  221. Row addr bits : 14
  222. Column addr bits : 10
  223. Number of ranks : 2
  224. DIMM Capacity : 1024 MB
  225. Width : x8
  226. Banks : 4
  227. CAS latencies : 4 5
  228. tCK at CL4 : 3.750 ns
  229. tAC at CL4 : 0.500 ns
  230. tCK at CL5 : 3.000 ns
  231. tAC at CL5 : 0.449 ns
  232. tCKmax : 0.796 ns
  233. tWRmin : 15.000 ns
  234. tRCDmin : 15.000 ns
  235. tRRDmin : 7.500 ns
  236. tRPmin : 15.000 ns
  237. tRASmin : 45.000 ns
  238. tRCmin : 55.000 ns
  239. tRFCmin : 105.000 ns
  240. tWTRmin : 7.500 ns
  241. tRTPmin : 7.500 ns
  242. tDS : 0.097 ns
  243. tDH : 0.167 ns
  244. tDQSQmax : 0.238 ns
  245. tQHSmax : 0.339 ns
  246. tPLL : 0.000 us
  247. tRR : 7812.500 us
  248. DDR II Channel 1 Socket 1: x8DDS
  249. DIMM 3 side 0 = 512 MB
  250. DIMM 3 side 1 = 512 MB
  251. Memory will be driven at 667MT with CAS=5 clocks
  252. tRAS = 15 cycles
  253. tRP = 5 cycles
  254. tRCD = 5 cycles
  255. tWR = 5 cycles
  256. tRFC = 43 cycles
  257. Refresh: 7.8us
  258. Setting Memory Frequency... CLKCFG = 0x20000002, CLKCFG = 0x20000032, ok
  259. Setting mode of operation for memory channels...Dual Channel Interleaved.
  260. DCC = 0x00000402
  261. Programming Clock Crossing...MEM=667 FSB=800... ok
  262. Setting RAM size...
  263. C0DRB = 0x60504020
  264. C1DRB = 0x60504020
  265. TOLUD = 0x00d0
  266. Setting row attributes...
  267. C0DRA = 0x3333
  268. C1DRA = 0x3333
  269. DIMM0 has 8 banks.
  270. DIMM2 has 8 banks.
  271. Initializing System Memory IO...
  272. Programming Dual Channel RCOMP
  273. Table Index: 18
  274. Programming DLL Timings...
  275. Enabling System Memory IO...
  276. jedec enable sequence: bank 0
  277. Apply NOP
  278. Sending RAM command 0x00010402...done
  279. RAM read: 00000000
  280. All Banks Precharge
  281. Sending RAM command 0x00020402...done
  282. RAM read: 00000000
  283. Extended Mode Register Set(2)
  284. Sending RAM command 0x00240402...done
  285. RAM read: 00000000
  286. Extended Mode Register Set(3)
  287. Sending RAM command 0x00440402...done
  288. RAM read: 00000000
  289. Extended Mode Register Set
  290. Sending RAM command 0x00040402...done
  291. RAM read: 00000400
  292. MRS: Reset DLLs
  293. Sending RAM command 0x00030402...done
  294. RAM read: 00009598
  295. All Banks Precharge
  296. Sending RAM command 0x00020402...done
  297. RAM read: 00000000
  298. CAS before RAS
  299. Sending RAM command 0x00060402...done
  300. RAM read: 00000000
  301. RAM read: 00000000
  302. MRS: Enable DLLs
  303. Sending RAM command 0x00030402...done
  304. RAM read: 00008598
  305. Extended Mode Register Set: ODT/OCD
  306. Sending RAM command 0x00040402...done
  307. RAM read: 00003c00
  308. Extended Mode Register Set: OCD Exit
  309. Sending RAM command 0x00040402...done
  310. RAM read: 00000400
  311. jedec enable sequence: bank 1
  312. bankaddr from bank size of rank 0
  313. Apply NOP
  314. Sending RAM command 0x00010402...done
  315. RAM read: 80000000
  316. All Banks Precharge
  317. Sending RAM command 0x00020402...done
  318. RAM read: 80000000
  319. Extended Mode Register Set(2)
  320. Sending RAM command 0x00240402...done
  321. RAM read: 80000000
  322. Extended Mode Register Set(3)
  323. Sending RAM command 0x00440402...done
  324. RAM read: 80000000
  325. Extended Mode Register Set
  326. Sending RAM command 0x00040402...done
  327. RAM read: 80000400
  328. MRS: Reset DLLs
  329. Sending RAM command 0x00030402...done
  330. RAM read: 80009598
  331. All Banks Precharge
  332. Sending RAM command 0x00020402...done
  333. RAM read: 80000000
  334. CAS before RAS
  335. Sending RAM command 0x00060402...done
  336. RAM read: 80000000
  337. RAM read: 80000000
  338. MRS: Enable DLLs
  339. Sending RAM command 0x00030402...done
  340. RAM read: 80008598
  341. Extended Mode Register Set: ODT/OCD
  342. Sending RAM command 0x00040402...done
  343. RAM read: 80003c00
  344. Extended Mode Register Set: OCD Exit
  345. Sending RAM command 0x00040402...done
  346. RAM read: 80000400
  347. jedec enable sequence: bank 2
  348. bankaddr from bank size of rank 1
  349. Apply NOP
  350. Sending RAM command 0x00010402...done
  351. RAM read: 00000000
  352. All Banks Precharge
  353. Sending RAM command 0x00020402...done
  354. RAM read: 00000000
  355. Extended Mode Register Set(2)
  356. Sending RAM command 0x00240402...done
  357. RAM read: 00000000
  358. Extended Mode Register Set(3)
  359. Sending RAM command 0x00440402...done
  360. RAM read: 00000000
  361. Extended Mode Register Set
  362. Sending RAM command 0x00040402...done
  363. RAM read: 00000400
  364. MRS: Reset DLLs
  365. Sending RAM command 0x00030402...done
  366. RAM read: 00009598
  367. All Banks Precharge
  368. Sending RAM command 0x00020402...done
  369. RAM read: 00000000
  370. CAS before RAS
  371. Sending RAM command 0x00060402...done
  372. RAM read: 00000000
  373. RAM read: 00000000
  374. MRS: Enable DLLs
  375. Sending RAM command 0x00030402...done
  376. RAM read: 00008598
  377. Extended Mode Register Set: ODT/OCD
  378. Sending RAM command 0x00040402...done
  379. RAM read: 00003c00
  380. Extended Mode Register Set: OCD Exit
  381. Sending RAM command 0x00040402...done
  382. RAM read: 00000400
  383. jedec enable sequence: bank 3
  384. bankaddr from bank size of rank 2
  385. Apply NOP
  386. Sending RAM command 0x00010402...done
  387. RAM read: 40000000
  388. All Banks Precharge
  389. Sending RAM command 0x00020402...done
  390. RAM read: 40000000
  391. Extended Mode Register Set(2)
  392. Sending RAM command 0x00240402...done
  393. RAM read: 40000000
  394. Extended Mode Register Set(3)
  395. Sending RAM command 0x00440402...done
  396. RAM read: 40000000
  397. Extended Mode Register Set
  398. Sending RAM command 0x00040402...done
  399. RAM read: 40000400
  400. MRS: Reset DLLs
  401. Sending RAM command 0x00030402...done
  402. RAM read: 40009598
  403. All Banks Precharge
  404. Sending RAM command 0x00020402...done
  405. RAM read: 40000000
  406. CAS before RAS
  407. Sending RAM command 0x00060402...done
  408. RAM read: 40000000
  409. RAM read: 40000000
  410. MRS: Enable DLLs
  411. Sending RAM command 0x00030402...done
  412. RAM read: 40008598
  413. Extended Mode Register Set: ODT/OCD
  414. Sending RAM command 0x00040402...done
  415. RAM read: 40003c00
  416. Extended Mode Register Set: OCD Exit
  417. Sending RAM command 0x00040402...done
  418. RAM read: 40000400
  419. jedec enable sequence: bank 4
  420. Apply NOP
  421. Sending RAM command 0x00010402...done
  422. RAM read: 00000040
  423. All Banks Precharge
  424. Sending RAM command 0x00020402...done
  425. RAM read: 00000040
  426. Extended Mode Register Set(2)
  427. Sending RAM command 0x00240402...done
  428. RAM read: 00000040
  429. Extended Mode Register Set(3)
  430. Sending RAM command 0x00440402...done
  431. RAM read: 00000040
  432. Extended Mode Register Set
  433. Sending RAM command 0x00040402...done
  434. RAM read: 00000440
  435. MRS: Reset DLLs
  436. Sending RAM command 0x00030402...done
  437. RAM read: 000095d8
  438. All Banks Precharge
  439. Sending RAM command 0x00020402...done
  440. RAM read: 00000040
  441. CAS before RAS
  442. Sending RAM command 0x00060402...done
  443. RAM read: 00000040
  444. RAM read: 00000040
  445. MRS: Enable DLLs
  446. Sending RAM command 0x00030402...done
  447. RAM read: 000085d8
  448. Extended Mode Register Set: ODT/OCD
  449. Sending RAM command 0x00040402...done
  450. RAM read: 00003c40
  451. Extended Mode Register Set: OCD Exit
  452. Sending RAM command 0x00040402...done
  453. RAM read: 00000440
  454. jedec enable sequence: bank 5
  455. bankaddr from bank size of rank 4
  456. Apply NOP
  457. Sending RAM command 0x00010402...done
  458. RAM read: 80000040
  459. All Banks Precharge
  460. Sending RAM command 0x00020402...done
  461. RAM read: 80000040
  462. Extended Mode Register Set(2)
  463. Sending RAM command 0x00240402...done
  464. RAM read: 80000040
  465. Extended Mode Register Set(3)
  466. Sending RAM command 0x00440402...done
  467. RAM read: 80000040
  468. Extended Mode Register Set
  469. Sending RAM command 0x00040402...done
  470. RAM read: 80000440
  471. MRS: Reset DLLs
  472. Sending RAM command 0x00030402...done
  473. RAM read: 800095d8
  474. All Banks Precharge
  475. Sending RAM command 0x00020402...done
  476. RAM read: 80000040
  477. CAS before RAS
  478. Sending RAM command 0x00060402...done
  479. RAM read: 80000040
  480. RAM read: 80000040
  481. MRS: Enable DLLs
  482. Sending RAM command 0x00030402...done
  483. RAM read: 800085d8
  484. Extended Mode Register Set: ODT/OCD
  485. Sending RAM command 0x00040402...done
  486. RAM read: 80003c40
  487. Extended Mode Register Set: OCD Exit
  488. Sending RAM command 0x00040402...done
  489. RAM read: 80000440
  490. jedec enable sequence: bank 6
  491. bankaddr from bank size of rank 5
  492. Apply NOP
  493. Sending RAM command 0x00010402...done
  494. RAM read: 00000040
  495. All Banks Precharge
  496. Sending RAM command 0x00020402...done
  497. RAM read: 00000040
  498. Extended Mode Register Set(2)
  499. Sending RAM command 0x00240402...done
  500. RAM read: 00000040
  501. Extended Mode Register Set(3)
  502. Sending RAM command 0x00440402...done
  503. RAM read: 00000040
  504. Extended Mode Register Set
  505. Sending RAM command 0x00040402...done
  506. RAM read: 00000440
  507. MRS: Reset DLLs
  508. Sending RAM command 0x00030402...done
  509. RAM read: 000095d8
  510. All Banks Precharge
  511. Sending RAM command 0x00020402...done
  512. RAM read: 00000040
  513. CAS before RAS
  514. Sending RAM command 0x00060402...done
  515. RAM read: 00000040
  516. RAM read: 00000040
  517. MRS: Enable DLLs
  518. Sending RAM command 0x00030402...done
  519. RAM read: 000085d8
  520. Extended Mode Register Set: ODT/OCD
  521. Sending RAM command 0x00040402...done
  522. RAM read: 00003c40
  523. Extended Mode Register Set: OCD Exit
  524. Sending RAM command 0x00040402...done
  525. RAM read: 00000440
  526. jedec enable sequence: bank 7
  527. bankaddr from bank size of rank 6
  528. Apply NOP
  529. Sending RAM command 0x00010402...done
  530. RAM read: 40000040
  531. All Banks Precharge
  532. Sending RAM command 0x00020402...done
  533. RAM read: 40000040
  534. Extended Mode Register Set(2)
  535. Sending RAM command 0x00240402...done
  536. RAM read: 40000040
  537. Extended Mode Register Set(3)
  538. Sending RAM command 0x00440402...done
  539. RAM read: 40000040
  540. Extended Mode Register Set
  541. Sending RAM command 0x00040402...done
  542. RAM read: 40000440
  543. MRS: Reset DLLs
  544. Sending RAM command 0x00030402...done
  545. RAM read: 400095d8
  546. All Banks Precharge
  547. Sending RAM command 0x00020402...done
  548. RAM read: 40000040
  549. CAS before RAS
  550. Sending RAM command 0x00060402...done
  551. RAM read: 40000040
  552. RAM read: 40000040
  553. MRS: Enable DLLs
  554. Sending RAM command 0x00030402...done
  555. RAM read: 400085d8
  556. Extended Mode Register Set: ODT/OCD
  557. Sending RAM command 0x00040402...done
  558. RAM read: 40003c40
  559. Extended Mode Register Set: OCD Exit
  560. Sending RAM command 0x00040402...done
  561. RAM read: 40000440
  562. Normal Operation
  563. Sending RAM command 0x000f0202...done
  564. receive_enable_autoconfig() for channel 0
  565. find_strobes_low()
  566. set_receive_enable() medium=0x3, coarse=0▒
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