--TEST BENCH


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tescik IS
END tescik;

ARCHITECTURE behavior OF tescik IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT DISPLAY
    PORT(
         CLK_i : IN  std_logic;
         RST_i : IN  std_logic;
         SW : IN  std_logic_vector(7 downto 0);
         BTN : IN  std_logic_vector(3 downto 0);
         AN : OUT  std_logic_vector(3 downto 0);
         SEG : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal CLK_i : std_logic := '0';
   signal RST_i : std_logic := '0';
   signal SW : std_logic_vector(7 downto 0) := (others => '0');
   signal BTN : std_logic_vector(3 downto 0) := (others => '0');

 	--Outputs
   signal AN : std_logic_vector(3 downto 0);
   signal SEG : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant CLK_i_period : time := 50 ms;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
   uut: DISPLAY PORT MAP (
          CLK_i => CLK_i,
          RST_i => RST_i,
          SW => SW,
          BTN => BTN,
          AN => AN,
          SEG => SEG
        );

   -- Clock process definitions
   CLK_i_process :process
   begin
		CLK_i <= '0';
		wait for CLK_i_period/2;
		CLK_i <= '1';
		wait for CLK_i_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ms;

		SW <= "00000001";
		BTN <= "1110";

		wait for 100 ms;

		SW <= "00000001";
		BTN <= "1101";

		wait for 100 ms;

		SW <= "00000010";
		BTN <= "1011";

		wait for 100 ms;

		SW <= "00000010";
		BTN <= "0111";

		wait for clk_i_period*10;

      wait;
   end process;

	resecix : process
		begin

		wait for 300 ms;

		RST_i <= '1';

		wait for 100 ms;

		RST_i <= '0';

		wait;
	end process;


END;