module traffic_tb;

    reg clock = 0;

    initial begin
        $dumpvars;
        #3000 $finish;
    end

    always #10 clock=!clock;

    wire red_a, green_a, yellow_a, red_b, green_b, yellow_b;

    traffic uut (clock, red_a, green_a, yellow_a, red_b, green_b, yellow_b);
endmodule