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-- Company:
-- Engineer:
--
-- Create Date:    10:30:01 12/18/2013
-- Design Name:
-- Module Name:    LCD_BANNER - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LCD_BANNER is
    Port ( iREADY : in  STD_LOGIC;
				iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           oEN : out  STD_LOGIC;
           oDATA : out  STD_LOGIC_VECTOR (7 downto 0));
end LCD_BANNER;

architecture Behavioral of LCD_BANNER is
type tSTATES is (sCLEAR, sWAIT_LCD, sSEND_CHAR, sNEXT_CHAR, sWAIT_HS);
	signal sSTATE : tSTATES :=sCLEAR;

constant cBR_CHAR:std_logic_vector(4 downto 0) :="11111";
constant cBR_HSEC:std_logic_vector(16 downto 0) :="10110111000110110";

constant cK : std_logic_vector(7 downto 0):="01001011";
constant ci : std_logic_vector(7 downto 0):="01101001";
constant cm : std_logic_vector(7 downto 0):="01101101";
constant cN : std_logic_vector(7 downto 0):="01001110";
constant co : std_logic_vector(7 downto 0):="01101111";
constant cv : std_logic_vector(7 downto 0):="01110110";
constant ca : std_logic_vector(7 downto 0):="01100001";
constant ck : std_logic_vector(7 downto 0):="01101011";
constant cCLEAR : std_logic_vector(7 downto 0):="00011011";
constant cBLANK : std_logic_vector(7 downto 0):="00100000";

	signal sDAT : std_logic_vector(7 downto 0) :="00000000";
	signal sEN : std_logic :='0';

	signal sSW : std_logic_vector(7 downto 0):="00000000";
	signal sHSEC_CNT : std_logic_vector(16 downto 0):="00000000000000000";
	signal sHSEC_EN : std_logic:='0';
	signal sCHAR_CNT : std_logic_vector(4 downto 0):="00000";
	signal sCHAR_EN : std_logic:='0';

	signal sADRESS : integer RANGE 0 to 31;
	type tMEMORY is array (0 to 31) of std_logic_vector(7 downto 0);
	signal sRAM : tMEMORY;
begin
sADRESS <= CONV_INTEGER(sCHAR_CNT);
process(iCLK,inRST) begin
if (inRST= '0') then
			sHSEC_CNT <= (others=>'0');
			sHSEC_EN <= '0';

				sRAM(0)<=cK;
				sRAM(1)<=ci;
				sRAM(2)<=cm;
				sRAM(3)<=cBLANK;
				sRAM(4)<=cBLANK;
				sRAM(5)<=cBLANK;
				sRAM(6)<=cBLANK;
				sRAM(7)<=cBLANK;
				sRAM(8)<=cBLANK;
				sRAM(9)<=cBLANK;
				sRAM(10)<=cBLANK;
				sRAM(11)<=cBLANK;
				sRAM(12)<=cBLANK;
				sRAM(13)<=cBLANK;
				sRAM(14)<=cBLANK;
				sRAM(15)<=sSW;
				sRAM(16)<=cN;
				sRAM(17)<=co;
				sRAM(18)<=cv;
				sRAM(19)<=ca;
				sRAM(20)<=ck;
				sRAM(21)<=cBLANK;
				sRAM(22)<=cBLANK;
				sRAM(23)<=cBLANK;
				sRAM(24)<=cBLANK;
				sRAM(25)<=cBLANK;
				sRAM(26)<=cBLANK;
				sRAM(27)<=cBLANK;
				sRAM(28)<=cBLANK;
				sRAM(29)<=cBLANK;
				sRAM(30)<=cBLANK;
				sRAM(31)<=cBLANK;
		elsif (iCLK'event and iCLK ='1') then
		if(sCHAR_EN='1') then
		sRAM(15)<=sSW;
			if (sHSEC_CNT = cBR_HSEC) then
					sHSEC_EN <= '1';
					sHSEC_CNT <= (others=>'0');
					sRAM <=sRAM(1 to 14)&sRAM(0)&sRAM(15)&sRAM(17 to 30)&sRAM(16)&sRAM(31);
			else
				sHSEC_CNT <= sHSEC_CNT + 1;
				sHSEC_EN <='0';
			end if;

		end if;
	end if;
	end process;

	--dozvola sledeceg stanja
process (iCLK, inRST) begin

			if (inRST= '0') then
				sCHAR_CNT <= (others=>'0');
				sCHAR_EN <= '0';
			elsif (iCLK'event and iCLK ='1') then
			if(sSTATE= sNEXT_CHAR) then
				if (sCHAR_CNT = cBR_CHAR) then
					sCHAR_EN <= '1';
					sCHAR_CNT <= (others=>'0');
				else
					sCHAR_CNT<= sCHAR_CNT + 1;
					sCHAR_EN <='0';
				end if;

		end if;
	end if;
	end process;

	--stanja

process (iCLK, inRST) begin

		if (inRST= '0') then
			sSTATE <= sCLEAR;
			sEN <= '0';
			sDAT <= "00011011";
		elsif (iCLK'event and iCLK ='1') then

			case(sSTATE) is

				when sCLEAR =>
						if (iREADY='0') then
							sSTATE <= sCLEAR;
						else
							sDAT <= cCLEAR;
							sSTATE <= sWAIT_LCD;
						end if;
				when sWAIT_LCD =>
						if(iREADY='1') then
							sEN <= '1';
							sSTATE <= sSEND_CHAR;
						else
							sEN <= '0';
							sSTATE <= sWAIT_LCD;
						end if;
				when sSEND_CHAR =>
						if(iREADY='1') then
							sDAT <= sRAM(sADRESS);
							sSTATE <= sSEND_CHAR;
						else
							sEN<='0';
							sSTATE <= sNEXT_CHAR;
						end if;
				when sNEXT_CHAR =>
						if(sCHAR_CNT = cBR_CHAR) then
							sSTATE <= sWAIT_HS;
						else
							sSTATE <= sWAIT_LCD;
						end if;
				when sWAIT_HS =>
						if(sHSEC_EN='1') then
							sSTATE <= sCLEAR;
						else
							sSTATE <= sWAIT_HS;
						end if;
			end case;
	end if;
	end process;

	oDAT <= cCLEAR when sSTATE = sCLEAR else
					  sRAM(sADRESS) when sSTATE = sSEND_CHAR else
					  "00000000";
		oEn<=sEN;
end Behavioral;