USE work.class_proj.all;
LIBRARY ieee;

USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity icache_tb is
end entity;

architecture tb of icache_tb is
component icache IS
    port(pc: in std_logic_vector(15 DOWNTO 0);
        inst1In,inst2In,inst3In,inst4In: IN instruction;
        inst1Out,inst2Out,inst3Out,inst4Out: OUT instruction;
        set_index: BUFFER integer;
        icread: IN std_logic;
        icwrite: IN std_logic;
        clk: IN std_logic;
        reset: IN std_logic;
        ichit: OUT std_logic);
END component;

signal clk: std_logic:='0';
signal icwrite,icread,reset,ichit: std_logic;
signal pc: std_logic_vector(15  downto 0);
signal inst1In,inst2In,inst3In,inst4In,inst1out,inst2out,inst3out,inst4out: instruction;

begin
UUT: icache
port map(clk=>clk,icwrite=>icwrite,icread=>icread,reset=>reset,ichit=>ichit,
pc=>pc,inst1In=>inst1In,inst2In=>inst2In,inst3In=>inst3In,inst4In=>inst4In,inst1out=>inst1out,
inst2out=>inst2out,inst3out=>inst3out,inst4out=>inst4out);
process
begin
pc<="0000000000000001";
inst1In.opcode<="0001"; inst1In.op1<="0110"; inst1In.op2<="0101"; inst1In.op3<="1001";
inst2In.opcode<="0011"; inst2In.op1<="0001"; inst2In.op2<="0101"; inst2In.op3<="0011";
inst3In.opcode<="0100"; inst3In.op1<="0101"; inst3In.op2<="0011"; inst3In.op3<="0111";
inst4In.opcode<="0010"; inst4In.op1<="0111"; inst4In.op2<="0000"; inst4In.op3<="0100";
clk<='1'; reset<='0'; icwrite<='1'; icread<='0'; wait for 10ns;
clk<='0'; reset<='0'; icwrite<='0'; icread<='1'; wait for 10ns;
clk<='1'; reset<='0'; icwrite<='0'; icread<='1'; wait for 10ns;
wait;
end process;
end tb; '

ARCHITECTURE DMICache OF icache IS
    TYPE L1ICache IS array (0 to 1023) OF icblock;
    SIGNAL instcache : L1ICache;

BEGIN

    PROCESS(clk)

    VARIABLE i: integer;
IF clk'EVENT and (clk = '1') THEN

            -- icache set index
            set_index <= to_integer(unsigned(pc(12 DOWNTO 3)));

            -- Reset all valid bits to 0
            IF (reset = '1') THEN
                FOR i IN 0 TO 1023 LOOP
                    instcache(i).valid <= '0';
                END LOOP;
            END IF;

            -- Fill block
            IF ( (reset = '0') and (icwrite = '1') ) THEN
                instcache(set_index).inst1 <= inst1In; --(The simulation stops here with an error)
                instcache(set_index).inst2 <= inst2In;
                instcache(set_index).inst3 <= inst3In;
                instcache(set_index).inst4 <= inst4In;
                instcache(set_index).tag <= pc(15 DOWNTO 13);
                instcache(set_index).valid <= '1';
            END IF;