//module: sat_counter_8bit
//developed by: Raju Pusapati

module sat_counter_8bit(
clk,
count);

input             clk;
output wire [7:0] count;

reg [7:0]   c = 8'b0;
parameter sat = 8'b11111111;


always @(posedge clk) begin

	if (c != sat) begin
		c <= c+1'b1;
	end

end

assign count = c;

endmodule