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  1. /dts-v1/;
  2.  
  3. / {
  4. model = "Amlogic";
  5. amlogic-dt-id = "s4_s905w2_2g";
  6. compatible = "amlogic, s4";
  7. interrupt-parent = <0x1>;
  8. #address-cells = <0x2>;
  9. #size-cells = <0x2>;
  10.  
  11. custom_maps {
  12. mapnum = <0x6>;
  13. map0 = <0x2>;
  14. map1 = <0x3>;
  15. map2 = <0x4>;
  16. map3 = <0x5>;
  17. map4 = <0x6>;
  18. map5 = <0x7>;
  19. phandle = <0x47>;
  20.  
  21. map_0 {
  22. mapname = "amlogic-remote-1";
  23. customcode = <0xfb04>;
  24. release_delay = <0x50>;
  25. size = <0x33>;
  26. keymap = <0x47000b 0x130002 0x100003 0x110004 0xf0005 0xc0006 0xd0007 0xb0008 0x80009 0x9000a 0x5c0061 0x51003d 0x50003e 0x40003f 0x4d0040 0x430041 0x170042 0x43 0x10044 0x160057 0x49000e 0x60082 0x140083 0x440067 0x1d006c 0x1c0069 0x48006a 0x53007d 0x450068 0x19006d 0x520077 0x5007a 0x59007b 0x1b0078 0x40079 0x1a0074 0xa000f 0xe0071 0x1f0066 0x1e0084 0x70085 0x120086 0x540087 0x20088 0x4f001e 0x420030 0x5d002e 0x4c0020 0x580089 0x1500d9 0x55008c>;
  27. phandle = <0x2>;
  28. };
  29.  
  30. map_1 {
  31. mapname = "amlogic-remote-2";
  32. customcode = <0xfe01>;
  33. release_delay = <0x50>;
  34. size = <0x35>;
  35. keymap = <0x10002 0x20003 0x30004 0x40005 0x50006 0x60007 0x70008 0x80009 0x9000a 0xa000b 0x1f01d2 0x15008b 0x16000f 0xc0192 0xd0193 0xe0073 0xf0072 0x110066 0x1c006a 0x1b0069 0x190067 0x1a006c 0x1d001c 0x170071 0x4900db 0x43009e 0x1201d5 0x1401d6 0x1801d7 0x590166 0x5a00a6 0x100074 0x4200a5 0x4400a3 0x1e00a8 0x4b00d0 0x5800a4 0x460082 0x400083 0x380046 0x5701d0 0x5b01d1 0x54018e 0x4c018f 0x4e0190 0x550191 0x5300ed 0x5200ee 0x3900d4 0x4100d5 0xb00d6 0xd8 0x1300d9>;
  36. phandle = <0x3>;
  37. };
  38.  
  39. map_2 {
  40. mapname = "amlogic-remote-3";
  41. customcode = <0x7f80>;
  42. fn_key_scancode = <0x52>;
  43. cursor_left_scancode = <0x25>;
  44. cursor_right_scancode = <0x27>;
  45. cursor_up_scancode = <0x26>;
  46. cursor_down_scancode = <0x28>;
  47. cursor_ok_scancode = <0xd>;
  48. release_delay = <0x50>;
  49. size = <0x1f>;
  50. keymap = <0x310002 0x320003 0x330004 0x340005 0x350006 0x360007 0x370008 0x380009 0x39000a 0x30000b 0x49008b 0x4e0073 0x560072 0x530066 0x27006a 0x250069 0x260067 0x28006c 0x4d0071 0x1b009e 0x510074 0x520077 0x44000e 0xbd0079 0xbb0078 0x580053 0x9004b 0x11004c 0x54004d 0x4f0040 0xd0061>;
  51. phandle = <0x4>;
  52. };
  53.  
  54. map_3 {
  55. mapname = "amlogic-remote-4";
  56. customcode = <0x7788>;
  57. release_delay = <0x50>;
  58. vendor = <0x2>;
  59. product = <0x2>;
  60. version = <0x200>;
  61. size = <0x26>;
  62. keymap = <0x10002 0x20003 0x30004 0x40005 0x50006 0x60007 0x70008 0x80009 0x9000a 0xa000b 0x5801d7 0x290166 0x74009c 0x4600d9 0xf008d 0x150067 0x16006c 0x170069 0x18006a 0x19001c 0x470066 0x48009e 0x32008a 0x210074 0x6001d2 0x250071 0x230073 0x240072 0x6300bb 0x6400bc 0x6700bd 0x6800be 0x330192 0x340193 0x4b018e 0x4a018f 0x490190 0x4c0191>;
  63. phandle = <0x5>;
  64. };
  65.  
  66. map_4 {
  67. mapname = "amlogic-remote-5";
  68. customcode = <0xbf00>;
  69. cursor_left_scancode = <0x5a>;
  70. cursor_right_scancode = <0x1b>;
  71. cursor_up_scancode = <0x6>;
  72. cursor_down_scancode = <0x1a>;
  73. cursor_ok_scancode = <0x55>;
  74. release_delay = <0x50>;
  75. size = <0x8>;
  76. keymap = <0x60067 0x16006c 0x5a0069 0x1b006a 0x50066 0x1a0061 0x15005e 0x55005c>;
  77. phandle = <0x6>;
  78. };
  79.  
  80. map_5 {
  81. mapname = "amlogic-remote-6";
  82. customcode = <0x4040>;
  83. fn_key_scancode = <0x47>;
  84. cursor_left_scancode = <0x10>;
  85. cursor_right_scancode = <0x11>;
  86. cursor_up_scancode = <0xb>;
  87. cursor_down_scancode = <0xe>;
  88. cursor_ok_scancode = <0xd>;
  89. release_delay = <0x50>;
  90. size = <0xd>;
  91. keymap = <0x4d0074 0x430071 0xb0067 0xe006c 0x100069 0x11006a 0xd0061 0x1a0066 0x45008b 0x42009e 0x180073 0x170072 0x470077>;
  92. phandle = <0x7>;
  93. };
  94. };
  95.  
  96. bifrost {
  97. compatible = "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
  98. #cooling-cells = <0x2>;
  99. reg = <0x0 0xfe400000 0x0 0x4000 0x0 0xfe002000 0x0 0x1000 0x0 0xff800000 0x0 0x1000 0x0 0xff63c000 0x0 0x1000 0x0 0xfe002000 0x0 0x1000>;
  100. interrupt-parent = <0x1>;
  101. interrupts = <0x0 0x90 0x4 0x0 0x91 0x4 0x0 0x92 0x4>;
  102. interrupt-names = "GPU", "MMU", "JOB";
  103. num_of_pp = <0x2>;
  104. sc_mpp = <0x1>;
  105. tbl = <0x8 0x9 0xa 0xb 0xc 0xc>;
  106. clk_cntl_reg = <0x57>;
  107. clocks = <0xd 0x91>;
  108. clock-names = "gpu_mux";
  109. assigned-clocks = <0xd 0x8b 0xd 0x8d 0xd 0x91>;
  110. assigned-clock-parents = <0xd 0xf 0x0 0xd 0x8d>;
  111. assigned-clock-rates = <0x0 0x1dcd6500 0x0>;
  112. phandle = <0x4c>;
  113.  
  114. clk125_cfg {
  115. clk_freq = <0x7735940>;
  116. clk_parent = "fclk_div4";
  117. clkp_freq = <0x1dcd6500>;
  118. clk_reg = <0xa03>;
  119. voltage = <0x47e>;
  120. keep_count = <0x5>;
  121. threshold = <0x1e 0x78>;
  122. };
  123.  
  124. dvfs250_cfg {
  125. clk_freq = <0xee6b280>;
  126. clk_parent = "fclk_div4";
  127. clkp_freq = <0x1dcd6500>;
  128. clk_reg = <0xa01>;
  129. voltage = <0x47e>;
  130. keep_count = <0x5>;
  131. threshold = <0x0 0x4c>;
  132. };
  133.  
  134. dvfs285_cfg {
  135. clk_freq = <0x1107a76d>;
  136. clk_parent = "fclk_div7";
  137. clkp_freq = <0x1107a76d>;
  138. clk_reg = <0xe00>;
  139. voltage = <0x47e>;
  140. keep_count = <0x5>;
  141. threshold = <0x0 0x4c>;
  142. phandle = <0x8>;
  143. };
  144.  
  145. dvfs400_cfg {
  146. clk_freq = <0x17d78400>;
  147. clk_parent = "fclk_div5";
  148. clkp_freq = <0x17d78400>;
  149. clk_reg = <0xc00>;
  150. voltage = <0x47e>;
  151. keep_count = <0x5>;
  152. threshold = <0x98 0xcf>;
  153. phandle = <0x9>;
  154. };
  155.  
  156. dvfs500_cfg {
  157. clk_freq = <0x1dcd6500>;
  158. clk_parent = "fclk_div4";
  159. clkp_freq = <0x1dcd6500>;
  160. clk_reg = <0xa00>;
  161. voltage = <0x47e>;
  162. keep_count = <0x5>;
  163. threshold = <0x26 0xc2>;
  164. phandle = <0xa>;
  165. };
  166.  
  167. dvfs666_cfg {
  168. clk_freq = <0x27bc86aa>;
  169. clk_parent = "fclk_div3";
  170. clkp_freq = <0x27bc86aa>;
  171. clk_reg = <0x800>;
  172. voltage = <0x47e>;
  173. keep_count = <0x5>;
  174. threshold = <0x96 0xcb>;
  175. phandle = <0xb>;
  176. };
  177.  
  178. dvfs800_cfg {
  179. clk_freq = <0x2faf0800>;
  180. clk_parent = "fclk_div2p5";
  181. clkp_freq = <0x2faf0800>;
  182. clk_reg = <0x600>;
  183. voltage = <0x47e>;
  184. keep_count = <0x5>;
  185. threshold = <0xe6 0xff>;
  186. phandle = <0xc>;
  187. };
  188.  
  189. dvfs850_cfg {
  190. clk_freq = <0x326cef80>;
  191. clk_parent = "gp0_pll";
  192. clkp_freq = <0x326cef80>;
  193. clk_reg = <0x200>;
  194. voltage = <0x47e>;
  195. keep_count = <0x5>;
  196. threshold = <0x9c 0xff>;
  197. };
  198. };
  199.  
  200. cpus {
  201. #address-cells = <0x2>;
  202. #size-cells = <0x0>;
  203.  
  204. cpu@0 {
  205. device_type = "cpu";
  206. compatible = "arm,cortex-a55", "arm,armv8";
  207. reg = <0x0 0x0>;
  208. enable-method = "psci";
  209. cpu-idle-states = <0xe 0xf>;
  210. dynamic-power-coefficient = <0xe6>;
  211. #cooling-cells = <0x2>;
  212. clocks = <0xd 0x1b 0xd 0x1a 0xd 0x3>;
  213. clock-names = "core_clk", "low_freq_clk_parent", "high_freq_clk_parent";
  214. cpu-supply = <0x10>;
  215. voltage-tolerance = <0x0>;
  216. clock-latency = <0xc350>;
  217. multi_tables_available;
  218. operating-points-v2 = <0x11 0x12 0x13 0x14>;
  219. phandle = <0x4b>;
  220. };
  221.  
  222. cpu@1 {
  223. device_type = "cpu";
  224. compatible = "arm,cortex-a55", "arm,armv8";
  225. reg = <0x0 0x1>;
  226. enable-method = "psci";
  227. cpu-idle-states = <0xe 0xf>;
  228. dynamic-power-coefficient = <0xe6>;
  229. #cooling-cells = <0x2>;
  230. clocks = <0xd 0x1b 0xd 0x1a 0xd 0x3>;
  231. clock-names = "core_clk", "low_freq_clk_parent", "high_freq_clk_parent";
  232. cpu-supply = <0x10>;
  233. voltage-tolerance = <0x0>;
  234. clock-latency = <0xc350>;
  235. multi_tables_available;
  236. operating-points-v2 = <0x11 0x12 0x13 0x14>;
  237. };
  238.  
  239. cpu@2 {
  240. device_type = "cpu";
  241. compatible = "arm,cortex-a55", "arm,armv8";
  242. reg = <0x0 0x2>;
  243. enable-method = "psci";
  244. cpu-idle-states = <0xe 0xf>;
  245. dynamic-power-coefficient = <0xe6>;
  246. #cooling-cells = <0x2>;
  247. clocks = <0xd 0x1b 0xd 0x1a 0xd 0x3>;
  248. clock-names = "core_clk", "low_freq_clk_parent", "high_freq_clk_parent";
  249. cpu-supply = <0x10>;
  250. voltage-tolerance = <0x0>;
  251. clock-latency = <0xc350>;
  252. multi_tables_available;
  253. operating-points-v2 = <0x11 0x12 0x13 0x14>;
  254. };
  255.  
  256. cpu@3 {
  257. device_type = "cpu";
  258. compatible = "arm,cortex-a55", "arm,armv8";
  259. reg = <0x0 0x3>;
  260. enable-method = "psci";
  261. cpu-idle-states = <0xe 0xf>;
  262. dynamic-power-coefficient = <0xe6>;
  263. #cooling-cells = <0x2>;
  264. clocks = <0xd 0x1b 0xd 0x1a 0xd 0x3>;
  265. clock-names = "core_clk", "low_freq_clk_parent", "high_freq_clk_parent";
  266. cpu-supply = <0x10>;
  267. voltage-tolerance = <0x0>;
  268. clock-latency = <0xc350>;
  269. multi_tables_available;
  270. operating-points-v2 = <0x11 0x12 0x13 0x14>;
  271. };
  272.  
  273. idle-states {
  274. entry-method = "arm,psci-0.2";
  275.  
  276. cpu-sleep-0 {
  277. compatible = "arm,idle-state";
  278. arm,psci-suspend-param = <0x10000>;
  279. local-timer-stop;
  280. entry-latency-us = <0xfa0>;
  281. exit-latency-us = <0x1388>;
  282. min-residency-us = <0x2710>;
  283. phandle = <0xe>;
  284. };
  285.  
  286. system-sleep-0 {
  287. compatible = "arm,idle-state";
  288. arm,psci-suspend-param = <0x0>;
  289. entry-latency-us = <0x3fffffff>;
  290. exit-latency-us = <0x40000000>;
  291. min-residency-us = <0xffffffff>;
  292. phandle = <0xf>;
  293. };
  294. };
  295. };
  296.  
  297. timer {
  298. compatible = "arm,armv8-timer";
  299. interrupts = <0x1 0xd 0xff08 0x1 0xe 0xff08 0x1 0xb 0xff08 0x1 0xa 0xff08>;
  300. };
  301.  
  302. timer_bc {
  303. compatible = "amlogic,bc-timer";
  304. status = "disabled";
  305. reg = <0x0 0xfe0100d8 0x0 0x4 0x0 0xfe0100dc 0x0 0x4>;
  306. timer_name = "Meson TimerD";
  307. clockevent-rating = <0x12c>;
  308. clockevent-shift = <0x14>;
  309. clockevent-features = <0x23>;
  310. interrupts = <0x0 0x3 0x1>;
  311. bit_enable = <0x7>;
  312. bit_mode = <0x6>;
  313. bit_resolution = <0x0>;
  314. resolution_1us = <0x1>;
  315. min_delta_ns = <0xa>;
  316. };
  317.  
  318. arm_pmu {
  319. compatible = "arm,armv8-pmuv3";
  320. private-interrupts;
  321. interrupts = <0x0 0xe9 0x4 0x0 0xea 0x4 0x0 0xeb 0x4 0x0 0xec 0x4>;
  322. reg = <0x0 0xff634680 0x0 0x4>;
  323. cpumasks = <0xf>;
  324. relax-timer-ns = <0x989680>;
  325. max-wait-cnt = <0x2710>;
  326. };
  327.  
  328. interrupt-controller@fff01000 {
  329. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  330. #interrupt-cells = <0x3>;
  331. #address-cells = <0x0>;
  332. interrupt-controller;
  333. reg = <0x0 0xfff01000 0x0 0x1000 0x0 0xfff02000 0x0 0x100>;
  334. interrupts = <0x1 0x9 0xf04>;
  335. phandle = <0x1>;
  336. };
  337.  
  338. psci {
  339. compatible = "arm,psci-0.2";
  340. method = "smc";
  341. };
  342.  
  343. pm {
  344. compatible = "amlogic, pm";
  345. status = "okay";
  346. device_name = "aml_pm";
  347. reg = <0x0 0xfe010288 0x0 0x4 0x0 0xfe0102dc 0x0 0x4>;
  348. };
  349.  
  350. cpu_info {
  351. compatible = "amlogic, cpuinfo";
  352. status = "okay";
  353. cpuinfo_cmd = <0x82000044>;
  354. };
  355.  
  356. aml_reboot {
  357. compatible = "aml, reboot";
  358. sys_reset = <0x84000009>;
  359. sys_poweroff = <0x84000008>;
  360. dis_nb_cpus_in_shutdown;
  361. };
  362.  
  363. secmon {
  364. compatible = "amlogic, secmon";
  365. memory-region = <0x15>;
  366. in_base_func = <0x82000020>;
  367. out_base_func = <0x82000021>;
  368. reserve_mem_size = <0x3300000>;
  369. };
  370.  
  371. cma_shrinker {
  372. compatible = "amlogic, cma-shrinker";
  373. status = "okay";
  374. adj = <0x0 0x64 0xc8 0xfa 0x384 0x3b6>;
  375. free = <0x1e00 0x5ee0 0x6f70 0x7f58 0x8000 0x8f10>;
  376. };
  377.  
  378. securitykey {
  379. compatible = "aml, securitykey";
  380. storage_query = <0x82000060>;
  381. storage_read = <0x82000061>;
  382. storage_write = <0x82000062>;
  383. storage_tell = <0x82000063>;
  384. storage_verify = <0x82000064>;
  385. storage_status = <0x82000065>;
  386. storage_list = <0x82000067>;
  387. storage_remove = <0x82000068>;
  388. storage_in_func = <0x82000023>;
  389. storage_out_func = <0x82000024>;
  390. storage_block_func = <0x82000025>;
  391. storage_size_func = <0x82000027>;
  392. storage_set_enctype = <0x8200006a>;
  393. storage_get_enctype = <0x8200006b>;
  394. storage_version = <0x8200006c>;
  395. };
  396.  
  397. xtal-clk {
  398. compatible = "fixed-clock";
  399. clock-frequency = <0x16e3600>;
  400. clock-output-names = "xtal";
  401. #clock-cells = <0x0>;
  402. phandle = <0x1a>;
  403. };
  404.  
  405. rtc@0xfe010288 {
  406. compatible = "amlogic,meson-vrtc";
  407. reg = <0x0 0xfe010288 0x0 0x4>;
  408. };
  409.  
  410. audio_data {
  411. compatible = "amlogic, audio_data";
  412. mem_in_base_cmd = <0x82000020>;
  413. query_licence_cmd = <0x82000050>;
  414. status = "okay";
  415. };
  416.  
  417. power-domains {
  418. compatible = "amlogic,s4-power-domain";
  419. #power-domain-cells = <0x1>;
  420. status = "okay";
  421. phandle = <0x27>;
  422. };
  423.  
  424. jtag {
  425. compatible = "amlogic, jtag";
  426. status = "okay";
  427. select = "disable";
  428. pinctrl-names = "jtag_a_pins", "jtag_b_pins";
  429. pinctrl-0 = <0x16>;
  430. pinctrl-1 = <0x17>;
  431. };
  432.  
  433. mhu@0 {
  434. status = "okay";
  435. compatible = "amlogic, meson_mhu_fifo";
  436. reg = <0x0 0xfe006000 0x0 0x800 0x0 0xfe006800 0x0 0x800 0x0 0xfe0070c0 0x0 0x40 0x0 0xfe007100 0x0 0x40 0x0 0xfe007140 0x0 0x40 0x0 0xfe007020 0x0 0x40>;
  437. interrupts = <0x0 0xf8 0x1>;
  438. mbox-irqctlr = <0x0>;
  439. mbox-nums = <0x2>;
  440. mbox-names = "ao_dev", "ap_to_ao";
  441. mboxes = <0x18 0x0 0x18 0x1>;
  442. mbox-id = <0x2 0x3>;
  443. #mbox-cells = <0x1>;
  444. phandle = <0x18>;
  445. };
  446.  
  447. pwm_j-regulator {
  448. compatible = "pwm-regulator";
  449. pwms = <0x19 0x1 0x5dc 0x0>;
  450. regulator-name = "vddcpu0";
  451. regulator-min-microvolt = <0xa8368>;
  452. regulator-max-microvolt = <0x1001a8>;
  453. regulator-always-on;
  454. max-duty-cycle = <0x5dc>;
  455. voltage-table = <0x1001a8 0x0 0xfda98 0x3 0xfb388 0x6 0xf8c78 0x9 0xf6568 0xc 0xf3e58 0xe 0xf1748 0x11 0xef038 0x14 0xec928 0x17 0xea218 0x1a 0xe7b08 0x1d 0xe53f8 0x1f 0xe2ce8 0x22 0xe05d8 0x25 0xddec8 0x28 0xdb7b8 0x2b 0xd90a8 0x2d 0xd6998 0x30 0xd4288 0x33 0xd1b78 0x36 0xcf468 0x38 0xccd58 0x3b 0xca648 0x3e 0xc7f38 0x41 0xc5828 0x44 0xc3118 0x46 0xc0a08 0x49 0xbe2f8 0x4c 0xbbbe8 0x4f 0xb94d8 0x51 0xb6dc8 0x54 0xb46b8 0x57 0xb1fa8 0x59 0xaf898 0x5c 0xad188 0x5f 0xaaa78 0x62 0xa8368 0x64>;
  456. status = "okay";
  457. phandle = <0x10>;
  458. };
  459.  
  460. s805x2_opp_table0 {
  461. compatible = "operating-points-v2";
  462. status = "okay";
  463. opp-shared;
  464. phandle = <0x11>;
  465.  
  466. opp00 {
  467. opp-hz = <0x0 0x5f5e100>;
  468. opp-microvolt = <0xbbbe8>;
  469. };
  470.  
  471. opp01 {
  472. opp-hz = <0x0 0xee6b280>;
  473. opp-microvolt = <0xbbbe8>;
  474. };
  475.  
  476. opp02 {
  477. opp-hz = <0x0 0x1dcd6500>;
  478. opp-microvolt = <0xbbbe8>;
  479. };
  480.  
  481. opp03 {
  482. opp-hz = <0x0 0x27b25a80>;
  483. opp-microvolt = <0xbbbe8>;
  484. };
  485.  
  486. opp04 {
  487. opp-hz = <0x0 0x3b9aca00>;
  488. opp-microvolt = <0xbbbe8>;
  489. };
  490.  
  491. opp05 {
  492. opp-hz = <0x0 0x47868c00>;
  493. opp-microvolt = <0xbbbe8>;
  494. };
  495.  
  496. opp06 {
  497. opp-hz = <0x0 0x53af5700>;
  498. opp-microvolt = <0xc3118>;
  499. };
  500.  
  501. opp07 {
  502. opp-hz = <0x0 0x59682f00>;
  503. opp-microvolt = <0xca648>;
  504. };
  505.  
  506. opp08 {
  507. opp-hz = <0x0 0x5fd82200>;
  508. opp-microvolt = <0xd4288>;
  509. };
  510.  
  511. opp09 {
  512. opp-hz = <0x0 0x6590fa00>;
  513. opp-microvolt = <0xddec8>;
  514. };
  515.  
  516. opp10 {
  517. opp-hz = <0x0 0x6b49d200>;
  518. opp-microvolt = <0xf6568>;
  519. };
  520. };
  521.  
  522. s805x2_opp_table1 {
  523. compatible = "operating-points-v2";
  524. status = "okay";
  525. opp-shared;
  526. phandle = <0x12>;
  527.  
  528. opp00 {
  529. opp-hz = <0x0 0x5f5e100>;
  530. opp-microvolt = <0xbbbe8>;
  531. };
  532.  
  533. opp01 {
  534. opp-hz = <0x0 0xee6b280>;
  535. opp-microvolt = <0xbbbe8>;
  536. };
  537.  
  538. opp02 {
  539. opp-hz = <0x0 0x1dcd6500>;
  540. opp-microvolt = <0xbbbe8>;
  541. };
  542.  
  543. opp03 {
  544. opp-hz = <0x0 0x27b25a80>;
  545. opp-microvolt = <0xbbbe8>;
  546. };
  547.  
  548. opp04 {
  549. opp-hz = <0x0 0x3b9aca00>;
  550. opp-microvolt = <0xbbbe8>;
  551. };
  552.  
  553. opp05 {
  554. opp-hz = <0x0 0x47868c00>;
  555. opp-microvolt = <0xbbbe8>;
  556. };
  557.  
  558. opp06 {
  559. opp-hz = <0x0 0x53af5700>;
  560. opp-microvolt = <0xc3118>;
  561. };
  562.  
  563. opp07 {
  564. opp-hz = <0x0 0x59682f00>;
  565. opp-microvolt = <0xca648>;
  566. };
  567.  
  568. opp08 {
  569. opp-hz = <0x0 0x5fd82200>;
  570. opp-microvolt = <0xd4288>;
  571. };
  572.  
  573. opp09 {
  574. opp-hz = <0x0 0x6590fa00>;
  575. opp-microvolt = <0xddec8>;
  576. };
  577.  
  578. opp10 {
  579. opp-hz = <0x0 0x6b49d200>;
  580. opp-microvolt = <0xf6568>;
  581. };
  582. };
  583.  
  584. s805x2_opp_table2 {
  585. compatible = "operating-points-v2";
  586. status = "okay";
  587. opp-shared;
  588. phandle = <0x13>;
  589.  
  590. opp00 {
  591. opp-hz = <0x0 0x5f5e100>;
  592. opp-microvolt = <0xb94d8>;
  593. };
  594.  
  595. opp01 {
  596. opp-hz = <0x0 0xee6b280>;
  597. opp-microvolt = <0xb94d8>;
  598. };
  599.  
  600. opp02 {
  601. opp-hz = <0x0 0x1dcd6500>;
  602. opp-microvolt = <0xb94d8>;
  603. };
  604.  
  605. opp03 {
  606. opp-hz = <0x0 0x27b25a80>;
  607. opp-microvolt = <0xb94d8>;
  608. };
  609.  
  610. opp04 {
  611. opp-hz = <0x0 0x3b9aca00>;
  612. opp-microvolt = <0xb94d8>;
  613. };
  614.  
  615. opp05 {
  616. opp-hz = <0x0 0x47868c00>;
  617. opp-microvolt = <0xb94d8>;
  618. };
  619.  
  620. opp06 {
  621. opp-hz = <0x0 0x53af5700>;
  622. opp-microvolt = <0xb94d8>;
  623. };
  624.  
  625. opp07 {
  626. opp-hz = <0x0 0x59682f00>;
  627. opp-microvolt = <0xbbbe8>;
  628. };
  629.  
  630. opp08 {
  631. opp-hz = <0x0 0x5fd82200>;
  632. opp-microvolt = <0xc3118>;
  633. };
  634.  
  635. opp09 {
  636. opp-hz = <0x0 0x6590fa00>;
  637. opp-microvolt = <0xca648>;
  638. };
  639.  
  640. opp10 {
  641. opp-hz = <0x0 0x6b49d200>;
  642. opp-microvolt = <0xf3e58>;
  643. };
  644. };
  645.  
  646. s805x2_opp_table3 {
  647. compatible = "operating-points-v2";
  648. status = "okay";
  649. opp-shared;
  650. phandle = <0x14>;
  651.  
  652. opp00 {
  653. opp-hz = <0x0 0x5f5e100>;
  654. opp-microvolt = <0xb94d8>;
  655. };
  656.  
  657. opp01 {
  658. opp-hz = <0x0 0xee6b280>;
  659. opp-microvolt = <0xb94d8>;
  660. };
  661.  
  662. opp02 {
  663. opp-hz = <0x0 0x1dcd6500>;
  664. opp-microvolt = <0xb94d8>;
  665. };
  666.  
  667. opp03 {
  668. opp-hz = <0x0 0x27b25a80>;
  669. opp-microvolt = <0xb94d8>;
  670. };
  671.  
  672. opp04 {
  673. opp-hz = <0x0 0x3b9aca00>;
  674. opp-microvolt = <0xb94d8>;
  675. };
  676.  
  677. opp05 {
  678. opp-hz = <0x0 0x47868c00>;
  679. opp-microvolt = <0xb94d8>;
  680. };
  681.  
  682. opp06 {
  683. opp-hz = <0x0 0x53af5700>;
  684. opp-microvolt = <0xb94d8>;
  685. };
  686.  
  687. opp07 {
  688. opp-hz = <0x0 0x59682f00>;
  689. opp-microvolt = <0xb94d8>;
  690. };
  691.  
  692. opp08 {
  693. opp-hz = <0x0 0x5fd82200>;
  694. opp-microvolt = <0xbbbe8>;
  695. };
  696.  
  697. opp09 {
  698. opp-hz = <0x0 0x6590fa00>;
  699. opp-microvolt = <0xc5828>;
  700. };
  701.  
  702. opp10 {
  703. opp-hz = <0x0 0x6b49d200>;
  704. opp-microvolt = <0xe53f8>;
  705. };
  706. };
  707.  
  708. s905y4_opp_table0 {
  709. compatible = "operating-points-v2";
  710. status = "okay";
  711. opp-shared;
  712.  
  713. opp00 {
  714. opp-hz = <0x0 0x5f5e100>;
  715. opp-microvolt = <0xbbbe8>;
  716. };
  717.  
  718. opp01 {
  719. opp-hz = <0x0 0xee6b280>;
  720. opp-microvolt = <0xbbbe8>;
  721. };
  722.  
  723. opp02 {
  724. opp-hz = <0x0 0x1dcd6500>;
  725. opp-microvolt = <0xbbbe8>;
  726. };
  727.  
  728. opp03 {
  729. opp-hz = <0x0 0x27b25a80>;
  730. opp-microvolt = <0xbbbe8>;
  731. };
  732.  
  733. opp04 {
  734. opp-hz = <0x0 0x3b9aca00>;
  735. opp-microvolt = <0xbbbe8>;
  736. };
  737.  
  738. opp05 {
  739. opp-hz = <0x0 0x47868c00>;
  740. opp-microvolt = <0xbbbe8>;
  741. };
  742.  
  743. opp06 {
  744. opp-hz = <0x0 0x53af5700>;
  745. opp-microvolt = <0xc3118>;
  746. };
  747.  
  748. opp07 {
  749. opp-hz = <0x0 0x59682f00>;
  750. opp-microvolt = <0xca648>;
  751. };
  752.  
  753. opp08 {
  754. opp-hz = <0x0 0x5fd82200>;
  755. opp-microvolt = <0xd4288>;
  756. };
  757.  
  758. opp09 {
  759. opp-hz = <0x0 0x6590fa00>;
  760. opp-microvolt = <0xddec8>;
  761. };
  762.  
  763. opp10 {
  764. opp-hz = <0x0 0x6b49d200>;
  765. opp-microvolt = <0xea218>;
  766. };
  767.  
  768. opp11 {
  769. opp-hz = <0x0 0x71b9c500>;
  770. opp-microvolt = <0xef038>;
  771. };
  772.  
  773. opp12 {
  774. opp-hz = <0x0 0x77729d00>;
  775. opp-microvolt = <0xf6568>;
  776. };
  777. };
  778.  
  779. s905y4_opp_table1 {
  780. compatible = "operating-points-v2";
  781. status = "okay";
  782. opp-shared;
  783.  
  784. opp00 {
  785. opp-hz = <0x0 0x5f5e100>;
  786. opp-microvolt = <0xbbbe8>;
  787. };
  788.  
  789. opp01 {
  790. opp-hz = <0x0 0xee6b280>;
  791. opp-microvolt = <0xbbbe8>;
  792. };
  793.  
  794. opp02 {
  795. opp-hz = <0x0 0x1dcd6500>;
  796. opp-microvolt = <0xbbbe8>;
  797. };
  798.  
  799. opp03 {
  800. opp-hz = <0x0 0x27b25a80>;
  801. opp-microvolt = <0xbbbe8>;
  802. };
  803.  
  804. opp04 {
  805. opp-hz = <0x0 0x3b9aca00>;
  806. opp-microvolt = <0xbbbe8>;
  807. };
  808.  
  809. opp05 {
  810. opp-hz = <0x0 0x47868c00>;
  811. opp-microvolt = <0xbbbe8>;
  812. };
  813.  
  814. opp06 {
  815. opp-hz = <0x0 0x53af5700>;
  816. opp-microvolt = <0xc3118>;
  817. };
  818.  
  819. opp07 {
  820. opp-hz = <0x0 0x59682f00>;
  821. opp-microvolt = <0xca648>;
  822. };
  823.  
  824. opp08 {
  825. opp-hz = <0x0 0x5fd82200>;
  826. opp-microvolt = <0xd4288>;
  827. };
  828.  
  829. opp09 {
  830. opp-hz = <0x0 0x6590fa00>;
  831. opp-microvolt = <0xddec8>;
  832. };
  833.  
  834. opp10 {
  835. opp-hz = <0x0 0x6b49d200>;
  836. opp-microvolt = <0xea218>;
  837. };
  838.  
  839. opp11 {
  840. opp-hz = <0x0 0x71b9c500>;
  841. opp-microvolt = <0xef038>;
  842. };
  843.  
  844. opp12 {
  845. opp-hz = <0x0 0x77729d00>;
  846. opp-microvolt = <0xf6568>;
  847. };
  848. };
  849.  
  850. s905y4_opp_table2 {
  851. compatible = "operating-points-v2";
  852. status = "okay";
  853. opp-shared;
  854.  
  855. opp00 {
  856. opp-hz = <0x0 0x5f5e100>;
  857. opp-microvolt = <0xb94d8>;
  858. };
  859.  
  860. opp01 {
  861. opp-hz = <0x0 0xee6b280>;
  862. opp-microvolt = <0xb94d8>;
  863. };
  864.  
  865. opp02 {
  866. opp-hz = <0x0 0x1dcd6500>;
  867. opp-microvolt = <0xb94d8>;
  868. };
  869.  
  870. opp03 {
  871. opp-hz = <0x0 0x27b25a80>;
  872. opp-microvolt = <0xb94d8>;
  873. };
  874.  
  875. opp04 {
  876. opp-hz = <0x0 0x3b9aca00>;
  877. opp-microvolt = <0xb94d8>;
  878. };
  879.  
  880. opp05 {
  881. opp-hz = <0x0 0x47868c00>;
  882. opp-microvolt = <0xb94d8>;
  883. };
  884.  
  885. opp06 {
  886. opp-hz = <0x0 0x53af5700>;
  887. opp-microvolt = <0xb94d8>;
  888. };
  889.  
  890. opp07 {
  891. opp-hz = <0x0 0x59682f00>;
  892. opp-microvolt = <0xbbbe8>;
  893. };
  894.  
  895. opp08 {
  896. opp-hz = <0x0 0x5fd82200>;
  897. opp-microvolt = <0xc3118>;
  898. };
  899.  
  900. opp09 {
  901. opp-hz = <0x0 0x6590fa00>;
  902. opp-microvolt = <0xca648>;
  903. };
  904.  
  905. opp10 {
  906. opp-hz = <0x0 0x6b49d200>;
  907. opp-microvolt = <0xe2ce8>;
  908. };
  909.  
  910. opp11 {
  911. opp-hz = <0x0 0x71b9c500>;
  912. opp-microvolt = <0xea218>;
  913. };
  914.  
  915. opp12 {
  916. opp-hz = <0x0 0x77729d00>;
  917. opp-microvolt = <0xf3e58>;
  918. };
  919. };
  920.  
  921. s905y4_opp_table3 {
  922. compatible = "operating-points-v2";
  923. status = "okay";
  924. opp-shared;
  925.  
  926. opp00 {
  927. opp-hz = <0x0 0x5f5e100>;
  928. opp-microvolt = <0xb94d8>;
  929. };
  930.  
  931. opp01 {
  932. opp-hz = <0x0 0xee6b280>;
  933. opp-microvolt = <0xb94d8>;
  934. };
  935.  
  936. opp02 {
  937. opp-hz = <0x0 0x1dcd6500>;
  938. opp-microvolt = <0xb94d8>;
  939. };
  940.  
  941. opp03 {
  942. opp-hz = <0x0 0x27b25a80>;
  943. opp-microvolt = <0xb94d8>;
  944. };
  945.  
  946. opp04 {
  947. opp-hz = <0x0 0x3b9aca00>;
  948. opp-microvolt = <0xb94d8>;
  949. };
  950.  
  951. opp05 {
  952. opp-hz = <0x0 0x47868c00>;
  953. opp-microvolt = <0xb94d8>;
  954. };
  955.  
  956. opp06 {
  957. opp-hz = <0x0 0x53af5700>;
  958. opp-microvolt = <0xb94d8>;
  959. };
  960.  
  961. opp07 {
  962. opp-hz = <0x0 0x59682f00>;
  963. opp-microvolt = <0xb94d8>;
  964. };
  965.  
  966. opp08 {
  967. opp-hz = <0x0 0x5fd82200>;
  968. opp-microvolt = <0xbbbe8>;
  969. };
  970.  
  971. opp09 {
  972. opp-hz = <0x0 0x6590fa00>;
  973. opp-microvolt = <0xc5828>;
  974. };
  975.  
  976. opp10 {
  977. opp-hz = <0x0 0x6b49d200>;
  978. opp-microvolt = <0xd90a8>;
  979. };
  980.  
  981. opp11 {
  982. opp-hz = <0x0 0x71b9c500>;
  983. opp-microvolt = <0xddec8>;
  984. };
  985.  
  986. opp12 {
  987. opp-hz = <0x0 0x77729d00>;
  988. opp-microvolt = <0xe53f8>;
  989. };
  990. };
  991.  
  992. cpufreq-meson {
  993. compatible = "amlogic, cpufreq-meson";
  994. status = "okay";
  995. };
  996.  
  997. saradc@fe026000 {
  998. compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc";
  999. status = "okay";
  1000. #io-channel-cells = <0x1>;
  1001. clocks = <0x1a 0xd 0x136 0xd 0x104 0xd 0x102>;
  1002. clock-names = "clkin", "core", "adc_clk", "adc_sel";
  1003. interrupts = <0x0 0xb5 0x1>;
  1004. reg = <0x0 0xfe026000 0x0 0x48>;
  1005. phandle = <0xa2>;
  1006. };
  1007.  
  1008. soc {
  1009. compatible = "simple-bus";
  1010. #address-cells = <0x2>;
  1011. #size-cells = <0x2>;
  1012. ranges;
  1013.  
  1014. apb4@fe000000 {
  1015. compatible = "simple-bus";
  1016. reg = <0x0 0xfe000000 0x0 0x480000>;
  1017. #address-cells = <0x2>;
  1018. #size-cells = <0x2>;
  1019. ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
  1020.  
  1021. clock-controller {
  1022. compatible = "amlogic,s4-clkc";
  1023. #clock-cells = <0x1>;
  1024. reg = <0x0 0x0 0x0 0x49c 0x0 0x8000 0x0 0x348 0x0 0xe140 0x0 0x24>;
  1025. reg-names = "basic", "pll", "cpu_clk";
  1026. clocks = <0x1a>;
  1027. clock-names = "xtal";
  1028. status = "okay";
  1029. phandle = <0xd>;
  1030. };
  1031.  
  1032. meson_clk_msr@48000 {
  1033. compatible = "amlogic,meson-s4-clk-measure";
  1034. reg = <0x0 0x48000 0x0 0x1c>;
  1035. };
  1036.  
  1037. watchdog@2100 {
  1038. compatible = "amlogic,meson-sc2-wdt";
  1039. status = "okay";
  1040. amlogic,feed_watchdog_mode = <0x1>;
  1041. reg = <0x0 0x2100 0x0 0x10>;
  1042. clocks = <0x1a>;
  1043. };
  1044.  
  1045. pinctrl@4000 {
  1046. compatible = "amlogic,meson-s4-periphs-pinctrl";
  1047. #address-cells = <0x2>;
  1048. #size-cells = <0x2>;
  1049. ranges;
  1050. phandle = <0x1b>;
  1051.  
  1052. bank@4000 {
  1053. reg = <0x0 0x4000 0x0 0x4c 0x0 0x40c0 0x0 0x220>;
  1054. reg-names = "mux", "gpio";
  1055. gpio-controller;
  1056. #gpio-cells = <0x2>;
  1057. gpio-ranges = <0x1b 0x0 0x0 0x52>;
  1058. phandle = <0x1d>;
  1059. };
  1060.  
  1061. i2c0_pins1 {
  1062.  
  1063. mux {
  1064. groups = "i2c0_sda", "i2c0_scl";
  1065. function = "i2c0";
  1066. drive-strength-microamp = <0xbb8>;
  1067. bias-disable;
  1068. };
  1069. };
  1070.  
  1071. i2c1_pins1 {
  1072.  
  1073. mux {
  1074. groups = "i2c1_sda_c", "i2c1_scl_c";
  1075. function = "i2c1";
  1076. drive-strength-microamp = <0xbb8>;
  1077. bias-disable;
  1078. };
  1079. };
  1080.  
  1081. i2c1_pins2 {
  1082. phandle = <0x20>;
  1083.  
  1084. mux {
  1085. groups = "i2c1_sda_d", "i2c1_scl_d";
  1086. function = "i2c1";
  1087. drive-strength-microamp = <0xbb8>;
  1088. bias-disable;
  1089. };
  1090. };
  1091.  
  1092. i2c1_pins3 {
  1093.  
  1094. mux {
  1095. groups = "i2c1_sda_h", "i2c1_scl_h";
  1096. function = "i2c1";
  1097. drive-strength-microamp = <0xbb8>;
  1098. bias-disable;
  1099. };
  1100. };
  1101.  
  1102. i2c1_pins4 {
  1103.  
  1104. mux {
  1105. groups = "i2c1_sda_x", "i2c1_scl_x";
  1106. function = "i2c1";
  1107. drive-strength-microamp = <0xbb8>;
  1108. bias-disable;
  1109. };
  1110. };
  1111.  
  1112. i2c2_pins1 {
  1113.  
  1114. mux {
  1115. groups = "i2c2_sda_d", "i2c2_scl_d";
  1116. function = "i2c2";
  1117. drive-strength-microamp = <0xbb8>;
  1118. bias-disable;
  1119. };
  1120. };
  1121.  
  1122. i2c2_pins2 {
  1123.  
  1124. mux {
  1125. groups = "i2c2_sda_h8", "i2c2_scl_h9";
  1126. function = "i2c2";
  1127. drive-strength-microamp = <0xbb8>;
  1128. bias-disable;
  1129. };
  1130. };
  1131.  
  1132. i2c2_pins3 {
  1133.  
  1134. mux {
  1135. groups = "i2c2_sda_h0", "i2c2_scl_h1";
  1136. function = "i2c2";
  1137. drive-strength-microamp = <0xbb8>;
  1138. bias-disable;
  1139. };
  1140. };
  1141.  
  1142. i2c3_pins1 {
  1143.  
  1144. mux {
  1145. groups = "i2c3_sda_x", "i2c3_scl_x";
  1146. function = "i2c3";
  1147. drive-strength-microamp = <0xbb8>;
  1148. bias-disable;
  1149. };
  1150. };
  1151.  
  1152. i2c3_pins2 {
  1153. phandle = <0x21>;
  1154.  
  1155. mux {
  1156. groups = "i2c3_sda_z", "i2c3_scl_z";
  1157. function = "i2c3";
  1158. drive-strength-microamp = <0xbb8>;
  1159. bias-disable;
  1160. };
  1161. };
  1162.  
  1163. i2c4_pins1 {
  1164.  
  1165. mux {
  1166. groups = "i2c4_sda_c", "i2c4_scl_c";
  1167. function = "i2c4";
  1168. drive-strength-microamp = <0xbb8>;
  1169. bias-disable;
  1170. };
  1171. };
  1172.  
  1173. i2c4_pins2 {
  1174.  
  1175. mux {
  1176. groups = "i2c4_sda_d", "i2c4_scl_d";
  1177. function = "i2c4";
  1178. drive-strength-microamp = <0xbb8>;
  1179. bias-disable;
  1180. };
  1181. };
  1182.  
  1183. i2c4_pins3 {
  1184. phandle = <0x22>;
  1185.  
  1186. mux {
  1187. groups = "i2c4_sda_z", "i2c4_scl_z";
  1188. function = "i2c4";
  1189. drive-strength-microamp = <0xbb8>;
  1190. bias-disable;
  1191. };
  1192. };
  1193.  
  1194. a_uart {
  1195. phandle = <0x3e>;
  1196.  
  1197. mux {
  1198. groups = "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts";
  1199. function = "uart_a";
  1200. };
  1201. };
  1202.  
  1203. c_uart {
  1204. phandle = <0x3f>;
  1205.  
  1206. mux {
  1207. groups = "uart_c_tx", "uart_c_rx";
  1208. function = "uart_c";
  1209. };
  1210. };
  1211.  
  1212. d_uart1 {
  1213. phandle = <0x40>;
  1214.  
  1215. mux {
  1216. groups = "uart_d_tx_h", "uart_d_rx_h";
  1217. function = "uart_d";
  1218. };
  1219. };
  1220.  
  1221. d_uart2 {
  1222.  
  1223. mux {
  1224. groups = "uart_d_tx_z", "uart_d_rx_z";
  1225. function = "uart_d";
  1226. };
  1227. };
  1228.  
  1229. e_uart1 {
  1230. phandle = <0x41>;
  1231.  
  1232. mux {
  1233. groups = "uart_e_tx_h", "uart_e_rx_h";
  1234. function = "uart_e";
  1235. };
  1236. };
  1237.  
  1238. e_uart2 {
  1239.  
  1240. mux {
  1241. groups = "uart_e_tx_z11", "uart_e_rx_z12";
  1242. function = "uart_e";
  1243. };
  1244. };
  1245.  
  1246. e_uart3 {
  1247.  
  1248. mux {
  1249. groups = "uart_e_tx_z8", "uart_e_rx_z9";
  1250. function = "uart_e";
  1251. };
  1252. };
  1253.  
  1254. emmc_pins {
  1255. phandle = <0x30>;
  1256.  
  1257. mux-0 {
  1258. groups = "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", "emmc_cmd";
  1259. function = "emmc";
  1260. bias-pull-up;
  1261. drive-strength-microamp = <0xfa0>;
  1262. };
  1263.  
  1264. mux-1 {
  1265. groups = "emmc_clk";
  1266. function = "emmc";
  1267. bias-pull-up;
  1268. drive-strength-microamp = <0xfa0>;
  1269. };
  1270. };
  1271.  
  1272. emmc_ds_pins {
  1273. phandle = <0x31>;
  1274.  
  1275. mux {
  1276. groups = "emmc_nand_ds";
  1277. function = "emmc";
  1278. bias-pull-down;
  1279. drive-strength-microamp = <0xfa0>;
  1280. };
  1281. };
  1282.  
  1283. emmc_clk_gate_pins {
  1284. phandle = <0x32>;
  1285.  
  1286. mux {
  1287. groups = "GPIOB_8";
  1288. function = "gpio_periphs";
  1289. bias-pull-down;
  1290. drive-strength-microamp = <0xfa0>;
  1291. };
  1292. };
  1293.  
  1294. all_nand_pins {
  1295. phandle = <0x3b>;
  1296.  
  1297. mux {
  1298. groups = "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", "nand_ce0", "nand_ale", "nand_cle", "nand_wen_clk", "nand_ren_wr";
  1299. function = "nand";
  1300. input-enable;
  1301. };
  1302. };
  1303.  
  1304. nand_cs {
  1305. phandle = <0x3c>;
  1306.  
  1307. mux {
  1308. groups = "nand_ce0";
  1309. function = "nand";
  1310. };
  1311. };
  1312.  
  1313. sd_to_ao_uart_clr_pins {
  1314. phandle = <0x36>;
  1315.  
  1316. mux {
  1317. groups = "GPIOD_0", "GPIOD_1";
  1318. function = "gpio_periphs";
  1319. };
  1320. };
  1321.  
  1322. sdcard_pins {
  1323. phandle = <0x33>;
  1324.  
  1325. mux {
  1326. groups = "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", "sdcard_clk_c", "sdcard_cmd_c";
  1327. function = "sdcard";
  1328. bias-pull-up;
  1329. drive-strength-microamp = <0xfa0>;
  1330. };
  1331. };
  1332.  
  1333. ao_to_sd_uart_pins {
  1334. phandle = <0x37>;
  1335.  
  1336. mux {
  1337. groups = "uart_b_tx_c", "uart_b_rx_c";
  1338. function = "uart_b";
  1339. bias-pull-up;
  1340. input-enable;
  1341. };
  1342. };
  1343.  
  1344. ao_uart_pins {
  1345. phandle = <0x38>;
  1346.  
  1347. mux {
  1348. groups = "uart_b_tx_d", "uart_b_rx_d";
  1349. function = "uart_b";
  1350. bias-pull-up;
  1351. input-enable;
  1352. };
  1353. };
  1354.  
  1355. sd_clr_all_pins {
  1356.  
  1357. mux {
  1358. groups = "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_5";
  1359. function = "gpio_periphs";
  1360. output-high;
  1361. };
  1362.  
  1363. mux1 {
  1364. groups = "GPIOC_4";
  1365. function = "gpio_periphs";
  1366. output-low;
  1367. };
  1368. };
  1369.  
  1370. sd_clr_noall_pins {
  1371.  
  1372. mux {
  1373. groups = "GPIOC_0", "GPIOC_1", "GPIOC_4", "GPIOC_5";
  1374. function = "gpio_periphs";
  1375. output-high;
  1376. };
  1377. };
  1378.  
  1379. sd_1bit_pins {
  1380. phandle = <0x35>;
  1381.  
  1382. mux {
  1383. groups = "sdcard_d0_c", "sdcard_clk_c", "sdcard_cmd_c";
  1384. function = "sdcard";
  1385. bias-pull-up;
  1386. drive-strength-microamp = <0xfa0>;
  1387. };
  1388. };
  1389.  
  1390. sdcard_clk_gate_pins {
  1391. phandle = <0x34>;
  1392.  
  1393. mux {
  1394. groups = "GPIOC_4";
  1395. function = "gpio_periphs";
  1396. bias-pull-down;
  1397. drive-strength-microamp = <0xfa0>;
  1398. };
  1399. };
  1400.  
  1401. sd_iso7816_pins {
  1402.  
  1403. mux {
  1404. groups = "iso7816_clk_h", "iso7816_data_h";
  1405. function = "iso7816";
  1406. input-enable;
  1407. bias-pull-down;
  1408. };
  1409. };
  1410.  
  1411. sdio_pins {
  1412. phandle = <0x39>;
  1413.  
  1414. mux {
  1415. groups = "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd";
  1416. function = "sdio";
  1417. bias-pull-up;
  1418. drive-strength-microamp = <0xfa0>;
  1419. };
  1420. };
  1421.  
  1422. sdio_clk_gate_pins {
  1423. phandle = <0x3a>;
  1424.  
  1425. mux {
  1426. groups = "GPIOX_4";
  1427. function = "gpio_periphs";
  1428. bias-pull-down;
  1429. drive-strength-microamp = <0xfa0>;
  1430. };
  1431. };
  1432.  
  1433. hdmitx_hpd {
  1434. phandle = <0x43>;
  1435.  
  1436. mux {
  1437. groups = "hdmitx_hpd_in";
  1438. function = "hdmitx";
  1439. bias-disable;
  1440. };
  1441. };
  1442.  
  1443. hdmitx_hpd_gpio {
  1444.  
  1445. mux {
  1446. groups = "GPIOH_1";
  1447. function = "gpio_periphs";
  1448. bias-disable;
  1449. };
  1450. };
  1451.  
  1452. hdmitx_ddc {
  1453. phandle = <0x44>;
  1454.  
  1455. mux {
  1456. groups = "hdmitx_sda", "hdmitx_sck";
  1457. function = "hdmitx";
  1458. bias-disable;
  1459. drive-strength = <0x3>;
  1460. };
  1461. };
  1462.  
  1463. dtvdemod_if_agc_pins {
  1464.  
  1465. mux {
  1466. groups = "dtv_a_if_agc_z6", "dtv_b_if_agc";
  1467. function = "dtv";
  1468. };
  1469. };
  1470.  
  1471. ee_ceca {
  1472. phandle = <0x45>;
  1473.  
  1474. mux {
  1475. groups = "ao_cec_a";
  1476. function = "ao_cec_a";
  1477. };
  1478. };
  1479.  
  1480. ee_cecb {
  1481. phandle = <0x46>;
  1482.  
  1483. mux {
  1484. groups = "ao_cec_b";
  1485. function = "ao_cec_b";
  1486. };
  1487. };
  1488.  
  1489. jtag_a_pin {
  1490. phandle = <0x16>;
  1491.  
  1492. mux {
  1493. groups = "jtag_1_tdi", "jtag_1_tdo", "jtag_1_clk", "jtag_1_tms";
  1494. function = "jtag_1";
  1495. };
  1496. };
  1497.  
  1498. jtag_b_pin {
  1499. phandle = <0x17>;
  1500.  
  1501. mux {
  1502. groups = "jtag_2_tdi", "jtag_2_tdo", "jtag_2_clk", "jtag_2_tms";
  1503. function = "jtag_2";
  1504. };
  1505. };
  1506.  
  1507. pwm_a_pins {
  1508.  
  1509. mux {
  1510. groups = "pwm_a_d";
  1511. function = "pwm_a";
  1512. };
  1513. };
  1514.  
  1515. pwm_b_pins1 {
  1516.  
  1517. mux {
  1518. groups = "pwm_b_d";
  1519. function = "pwm_b";
  1520. };
  1521. };
  1522.  
  1523. pwm_b_pins2 {
  1524.  
  1525. mux {
  1526. groups = "pwm_b_x";
  1527. function = "pwm_b";
  1528. };
  1529. };
  1530.  
  1531. pwm_c_pins1 {
  1532.  
  1533. mux {
  1534. groups = "pwm_c_d";
  1535. function = "pwm_c";
  1536. };
  1537. };
  1538.  
  1539. pwm_c_pins2 {
  1540.  
  1541. mux {
  1542. groups = "pwm_c_x";
  1543. function = "pwm_c";
  1544. };
  1545. };
  1546.  
  1547. pwm_d_pins1 {
  1548.  
  1549. mux {
  1550. groups = "pwm_d_d";
  1551. function = "pwm_d";
  1552. };
  1553. };
  1554.  
  1555. pwm_d_pins2 {
  1556.  
  1557. mux {
  1558. groups = "pwm_d_h";
  1559. function = "pwm_d";
  1560. };
  1561. };
  1562.  
  1563. pwm_e_pins1 {
  1564. phandle = <0x1f>;
  1565.  
  1566. mux {
  1567. groups = "pwm_e_x";
  1568. function = "pwm_e";
  1569. drive-strength-microamp = <0x1f4>;
  1570. };
  1571. };
  1572.  
  1573. pwm_e_pins2 {
  1574.  
  1575. mux {
  1576. groups = "pwm_e_z";
  1577. function = "pwm_e";
  1578. };
  1579. };
  1580.  
  1581. pwm_f_pins1 {
  1582.  
  1583. mux {
  1584. groups = "pwm_f_x";
  1585. function = "pwm_f";
  1586. };
  1587. };
  1588.  
  1589. pwm_f_pins2 {
  1590.  
  1591. mux {
  1592. groups = "pwm_f_z";
  1593. function = "pwm_f";
  1594. };
  1595. };
  1596.  
  1597. pwm_g_pins1 {
  1598.  
  1599. mux {
  1600. groups = "pwm_g_d";
  1601. function = "pwm_g";
  1602. };
  1603. };
  1604.  
  1605. pwm_g_pins2 {
  1606.  
  1607. mux {
  1608. groups = "pwm_g_z";
  1609. function = "pwm_g";
  1610. };
  1611. };
  1612.  
  1613. pwm_h_pins {
  1614.  
  1615. mux {
  1616. groups = "pwm_h";
  1617. function = "pwm_h";
  1618. };
  1619. };
  1620.  
  1621. pwm_i_pins1 {
  1622.  
  1623. mux {
  1624. groups = "pwm_i_d";
  1625. function = "pwm_i";
  1626. };
  1627. };
  1628.  
  1629. pwm_i_pins2 {
  1630.  
  1631. mux {
  1632. groups = "pwm_i_h";
  1633. function = "pwm_i";
  1634. };
  1635. };
  1636.  
  1637. pwm_j_pins {
  1638.  
  1639. mux {
  1640. groups = "pwm_j";
  1641. function = "pwm_j";
  1642. };
  1643. };
  1644.  
  1645. pwm_a_hiz_pins {
  1646.  
  1647. mux {
  1648. groups = "pwm_a_hiz";
  1649. function = "pwm_a_hiz";
  1650. };
  1651. };
  1652.  
  1653. pwm_b_hiz_pins {
  1654.  
  1655. mux {
  1656. groups = "pwm_b_hiz";
  1657. function = "pwm_b_hiz";
  1658. };
  1659. };
  1660.  
  1661. pwm_c_hiz_pins {
  1662.  
  1663. mux {
  1664. groups = "pwm_c_hiz";
  1665. function = "pwm_b_hiz";
  1666. };
  1667. };
  1668.  
  1669. pwm_g_hiz_pins {
  1670.  
  1671. mux {
  1672. groups = "pwm_g_hiz";
  1673. function = "pwm_g_hiz";
  1674. };
  1675. };
  1676.  
  1677. remote_pin {
  1678. phandle = <0x48>;
  1679.  
  1680. mux {
  1681. groups = "remote_in";
  1682. function = "remote_in";
  1683. bias-disable;
  1684. };
  1685. };
  1686.  
  1687. spicc0_pins_x {
  1688. phandle = <0x1c>;
  1689.  
  1690. mux {
  1691. groups = "spi_a_mosi_x", "spi_a_miso_x", "spi_a_clk_x";
  1692. function = "spi_a";
  1693. drive-strength = <0x2>;
  1694. };
  1695. };
  1696.  
  1697. spicc0_pins_h {
  1698.  
  1699. mux {
  1700. groups = "spi_a_mosi_h", "spi_a_miso_h", "spi_a_clk_h";
  1701. function = "spi_a";
  1702. drive-strength = <0x2>;
  1703. };
  1704. };
  1705.  
  1706. spicc0_pins_z {
  1707.  
  1708. mux {
  1709. groups = "spi_a_mosi_z", "spi_a_miso_z", "spi_a_clk_z";
  1710. function = "spi_a";
  1711. drive-strength = <0x2>;
  1712. };
  1713. };
  1714.  
  1715. spifc_pins {
  1716. phandle = <0x1e>;
  1717.  
  1718. mux {
  1719. groups = "spif_hold", "spif_mo", "spif_mi", "spif_clk", "spif_wp", "spif_cs";
  1720. function = "spif";
  1721. drive-strength-microamp = <0xbb8>;
  1722. };
  1723. };
  1724.  
  1725. irblaster_pin {
  1726.  
  1727. mux {
  1728. groups = "remote_out";
  1729. function = "remote_out";
  1730. };
  1731. };
  1732.  
  1733. spdifin {
  1734.  
  1735. mux {
  1736. groups = "spdif_in";
  1737. function = "spdif_in";
  1738. };
  1739. };
  1740.  
  1741. tdm_a {
  1742. phandle = <0x29>;
  1743.  
  1744. mux {
  1745. groups = "tdm_sclk0", "tdm_fs0", "tdm_d0", "tdm_d1";
  1746. function = "tdm";
  1747. };
  1748. };
  1749.  
  1750. pdmin {
  1751. phandle = <0x2f>;
  1752.  
  1753. mux {
  1754. groups = "pdm_dclk_d", "pdm_din0_d";
  1755. function = "pdm";
  1756. };
  1757. };
  1758.  
  1759. spdifout {
  1760. phandle = <0x2d>;
  1761.  
  1762. mux {
  1763. groups = "spdif_out_h";
  1764. function = "spdif_out";
  1765. };
  1766. };
  1767.  
  1768. spdifout_a_mute {
  1769. phandle = <0x2e>;
  1770.  
  1771. mux {
  1772. groups = "GPIOH_4";
  1773. function = "gpio_periphs";
  1774. output-low;
  1775. };
  1776. };
  1777.  
  1778. dvb_s_ts0_pins {
  1779. phandle = <0x84>;
  1780.  
  1781. tsin_a {
  1782. groups = "tsin_a_sop", "tsin_a_valid", "tsin_a_clk", "tsin_a_din0";
  1783. function = "tsin_a";
  1784. };
  1785. };
  1786. };
  1787.  
  1788. interrupt-controller@4080 {
  1789. compatible = "amlogic,meson-s4-gpio-intc", "amlogic,meson-gpio-intc";
  1790. reg = <0x0 0x4080 0x0 0x20>;
  1791. interrupt-controller;
  1792. #interrupt-cells = <0x2>;
  1793. amlogic,channel-interrupts = <0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15>;
  1794. };
  1795.  
  1796. spi@50000 {
  1797. compatible = "amlogic,meson-g12-spicc";
  1798. reg = <0x0 0x50000 0x0 0x44>;
  1799. interrupts = <0x0 0xb7 0x4>;
  1800. clocks = <0xd 0x122 0xd 0xe0>;
  1801. clock-names = "core", "async";
  1802. #address-cells = <0x1>;
  1803. #size-cells = <0x0>;
  1804. status = "disabled";
  1805. pinctrl-names = "default";
  1806. pinctrl-0 = <0x1c>;
  1807. cs-gpios = <0x1d 0x3a 0x0>;
  1808. };
  1809.  
  1810. spi@56000 {
  1811. compatible = "amlogic,meson-spifc";
  1812. status = "disabled";
  1813. reg = <0x0 0x56000 0x0 0x80>;
  1814. clock-names = "default";
  1815. clocks = <0xd 0x114>;
  1816. pinctrl-names = "default";
  1817. pinctrl-0 = <0x1e>;
  1818. #address-cells = <0x1>;
  1819. #size-cells = <0x0>;
  1820.  
  1821. spi-nor@0 {
  1822. compatible = "jedec,spi-nor";
  1823. status = "disabled";
  1824. reg = <0x0>;
  1825. spi-max-frequency = <0xf42400>;
  1826. };
  1827. };
  1828.  
  1829. pwm@58000 {
  1830. compatible = "amlogic,meson-v2-pwm";
  1831. reg = <0x0 0x58000 0x0 0x24>;
  1832. #pwm-cells = <0x3>;
  1833. clocks = <0xd 0xe6 0xd 0xe9>;
  1834. clock-names = "clkin0", "clkin1";
  1835. status = "disabled";
  1836. };
  1837.  
  1838. pwm@5a000 {
  1839. compatible = "amlogic,meson-v2-pwm";
  1840. reg = <0x0 0x5a000 0x0 0x24>;
  1841. #pwm-cells = <0x3>;
  1842. clocks = <0xd 0xec 0xd 0xef>;
  1843. clock-names = "clkin0", "clkin1";
  1844. status = "disabled";
  1845. };
  1846.  
  1847. pwm@5c000 {
  1848. compatible = "amlogic,meson-v2-pwm";
  1849. reg = <0x0 0x5c000 0x0 0x24>;
  1850. #pwm-cells = <0x3>;
  1851. clocks = <0xd 0xf2 0xd 0xf5>;
  1852. clock-names = "clkin0", "clkin1";
  1853. status = "okay";
  1854. pinctrl-0 = <0x1f>;
  1855. pinctrl-names = "default";
  1856. phandle = <0x51>;
  1857. };
  1858.  
  1859. pwm@5e000 {
  1860. compatible = "amlogic,meson-v2-pwm";
  1861. reg = <0x0 0x5e000 0x0 0x24>;
  1862. #pwm-cells = <0x3>;
  1863. clocks = <0xd 0xf8 0xd 0xfb>;
  1864. clock-names = "clkin0", "clkin1";
  1865. status = "disabled";
  1866. };
  1867.  
  1868. pwm@60000 {
  1869. compatible = "amlogic,meson-v2-pwm";
  1870. reg = <0x0 0x60000 0x0 0x24>;
  1871. #pwm-cells = <0x3>;
  1872. clocks = <0xd 0xfe 0xd 0x101>;
  1873. clock-names = "clkin0", "clkin1";
  1874. status = "okay";
  1875. phandle = <0x19>;
  1876. };
  1877.  
  1878. i2c@66000 {
  1879. compatible = "amlogic,meson-i2c";
  1880. reg = <0x0 0x66000 0x0 0x48>;
  1881. interrupts = <0x0 0xa0 0x1>;
  1882. #address-cells = <0x1>;
  1883. #size-cells = <0x0>;
  1884. clocks = <0xd 0x127>;
  1885. status = "disabled";
  1886. };
  1887.  
  1888. i2c@68000 {
  1889. compatible = "amlogic,meson-i2c";
  1890. reg = <0x0 0x68000 0x0 0x48>;
  1891. interrupts = <0x0 0xa1 0x1>;
  1892. #address-cells = <0x1>;
  1893. #size-cells = <0x0>;
  1894. clocks = <0xd 0x128>;
  1895. status = "disable";
  1896. pinctrl-names = "default";
  1897. pinctrl-0 = <0x20>;
  1898. clock-frequency = <0x493e0>;
  1899.  
  1900. tlc59116@60 {
  1901. compatible = "amlogic,tlc59116_led";
  1902. reg = <0x60>;
  1903. status = "disable";
  1904.  
  1905. led0 {
  1906. default_colors = <0x0 0x0 0x0>;
  1907. r_io_number = <0x0>;
  1908. g_io_number = <0xa>;
  1909. b_io_number = <0x5>;
  1910. };
  1911.  
  1912. led1 {
  1913. default_colors = <0x0 0x0 0x0>;
  1914. r_io_number = <0x1>;
  1915. g_io_number = <0xb>;
  1916. b_io_number = <0x6>;
  1917. };
  1918.  
  1919. led2 {
  1920. default_colors = <0x0 0x0 0x0>;
  1921. r_io_number = <0x2>;
  1922. g_io_number = <0xc>;
  1923. b_io_number = <0x7>;
  1924. };
  1925.  
  1926. led3 {
  1927. default_colors = <0x0 0x0 0x0>;
  1928. r_io_number = <0x3>;
  1929. g_io_number = <0xd>;
  1930. b_io_number = <0x8>;
  1931. };
  1932. };
  1933. };
  1934.  
  1935. i2c@6a000 {
  1936. compatible = "amlogic,meson-i2c";
  1937. reg = <0x0 0x6a000 0x0 0x48>;
  1938. interrupts = <0x0 0xa2 0x1>;
  1939. #address-cells = <0x1>;
  1940. #size-cells = <0x0>;
  1941. clocks = <0xd 0x129>;
  1942. status = "disabled";
  1943. };
  1944.  
  1945. i2c@6c000 {
  1946. compatible = "amlogic,meson-i2c";
  1947. reg = <0x0 0x6c000 0x0 0x48>;
  1948. interrupts = <0x0 0xa3 0x1>;
  1949. #address-cells = <0x1>;
  1950. #size-cells = <0x0>;
  1951. clocks = <0xd 0x12a>;
  1952. status = "okay";
  1953. pinctrl-names = "default";
  1954. pinctrl-0 = <0x21>;
  1955. clock-frequency = <0x493e0>;
  1956. phandle = <0x83>;
  1957. };
  1958.  
  1959. i2c@6e000 {
  1960. compatible = "amlogic,meson-i2c";
  1961. reg = <0x0 0x6e000 0x0 0x48>;
  1962. interrupts = <0x0 0xa4 0x1>;
  1963. #address-cells = <0x1>;
  1964. #size-cells = <0x0>;
  1965. clocks = <0xd 0x12b>;
  1966. status = "okay";
  1967. pinctrl-names = "default";
  1968. pinctrl-0 = <0x22>;
  1969. clock-frequency = <0x493e0>;
  1970. phandle = <0x82>;
  1971. };
  1972.  
  1973. serial@7a000 {
  1974. compatible = "amlogic,meson-uart";
  1975. reg = <0x0 0x7a000 0x0 0x18>;
  1976. interrupts = <0x0 0xa9 0x1>;
  1977. status = "okay";
  1978. clocks = <0x1a>;
  1979. clock-names = "clk_uart";
  1980. xtal_tick_en = <0x2>;
  1981. fifosize = <0x40>;
  1982. support-sysrq = <0x0>;
  1983. };
  1984.  
  1985. mdio-multiplexer@28000 {
  1986. compatible = "amlogic,g12a-mdio-mux";
  1987. reg = <0x0 0x28000 0x0 0xa4>;
  1988. clocks = <0xd 0x10a 0x1a 0xd 0x32>;
  1989. clock-names = "pclk", "clkin0", "clkin1";
  1990. mdio-parent-bus = <0x23>;
  1991. #address-cells = <0x1>;
  1992. #size-cells = <0x0>;
  1993. enet_type = <0x5>;
  1994. tx_amp_src = <0xfe010330>;
  1995.  
  1996. mdio@0 {
  1997. reg = <0x0>;
  1998. #address-cells = <0x1>;
  1999. #size-cells = <0x0>;
  2000. };
  2001.  
  2002. mdio@1 {
  2003. reg = <0x1>;
  2004. #address-cells = <0x1>;
  2005. #size-cells = <0x0>;
  2006.  
  2007. ethernet_phy@8 {
  2008. compatible = "ethernet-phy-id0180.3301", "ethernet-phy-ieee802.3-c22";
  2009. interrupts = <0x0 0x4b 0x4>;
  2010. reg = <0x8>;
  2011. max-speed = <0x64>;
  2012. phandle = <0x3d>;
  2013. };
  2014. };
  2015. };
  2016.  
  2017. reset-controller@2000 {
  2018. compatible = "amlogic,meson-sc2-reset";
  2019. reg = <0x0 0x2000 0x0 0x98>;
  2020. #reset-cells = <0x1>;
  2021. phandle = <0x26>;
  2022. };
  2023.  
  2024. cpu_version {
  2025. compatible = "amlogic,meson-gx-ao-secure", "syscon";
  2026. reg = <0x0 0x10220 0x0 0x4>;
  2027. };
  2028. };
  2029.  
  2030. usb2phy@fe03a000 {
  2031. compatible = "amlogic,amlogic-new-usb2-v2";
  2032. status = "okay";
  2033. #phy-cells = <0x0>;
  2034. reg = <0x0 0xfe03a000 0x0 0x80 0x0 0xfe002000 0x0 0x100 0x0 0xfe03c000 0x0 0x2000 0x0 0xfe03e000 0x0 0x2000>;
  2035. pll-setting-1 = <0x9400414>;
  2036. pll-setting-2 = <0x927e0000>;
  2037. pll-setting-3 = <0xac5f69e5>;
  2038. pll-setting-4 = <0xbe18>;
  2039. pll-setting-5 = <0x7>;
  2040. pll-setting-6 = <0x78000>;
  2041. pll-setting-7 = <0xe0004>;
  2042. pll-setting-8 = <0xe000c>;
  2043. version = <0x3>;
  2044. phy20-reset-level-bit = <0x8>;
  2045. phy21-reset-level-bit = <0x9>;
  2046. usb-reset-bit = <0x4>;
  2047. reset-level = <0x40>;
  2048. portnum = <0x2>;
  2049. phandle = <0x24>;
  2050. };
  2051.  
  2052. usb3phy@fe03a080 {
  2053. compatible = "amlogic,amlogic-new-usb3-v2";
  2054. status = "okay";
  2055. #phy-cells = <0x0>;
  2056. reg = <0x0 0xfe03a080 0x0 0x20 0x0 0xfe002000 0x0 0x100>;
  2057. phy-reg = <0xfe02a000>;
  2058. phy-reg-size = <0x2000>;
  2059. usb2-phy-reg = <0xfe03a000>;
  2060. usb2-phy-reg-size = <0x80>;
  2061. clocks = <0xd 0x2d>;
  2062. clock-names = "pcie_refpll";
  2063. interrupts = <0x0 0x81 0x4>;
  2064. portnum = <0x0>;
  2065. otg = <0x1>;
  2066. phandle = <0x25>;
  2067. };
  2068.  
  2069. crg@fde00000 {
  2070. compatible = "amlogic, crg";
  2071. status = "okay";
  2072. reg = <0x0 0xfde00000 0x0 0x100000>;
  2073. interrupts = <0x0 0x82 0x4>;
  2074. usb-phy = <0x24 0x25>;
  2075. cpu-type = "gxl";
  2076. clock-src = "usb3.0";
  2077. clocks = <0xd 0x125>;
  2078. clock-names = "crg_general";
  2079. };
  2080.  
  2081. dummy {
  2082. #sound-dai-cells = <0x0>;
  2083. compatible = "amlogic, aml_dummy_codec";
  2084. status = "okay";
  2085. phandle = <0x9a>;
  2086. };
  2087.  
  2088. t9015 {
  2089. #sound-dai-cells = <0x0>;
  2090. compatible = "amlogic, s4_codec_T9015";
  2091. reg = <0x0 0xfe01a000 0x0 0x2000>;
  2092. tocodec_inout = <0x2>;
  2093. tdmout_index = <0x2>;
  2094. ch0_sel = <0x0>;
  2095. ch1_sel = <0x1>;
  2096. reset-names = "acodec";
  2097. resets = <0x26 0x58>;
  2098. status = "okay";
  2099. phandle = <0x9d>;
  2100. };
  2101.  
  2102. audiobus@0xFE330000 {
  2103. compatible = "amlogic, audio-controller", "simple-bus";
  2104. reg = <0x0 0xfe330000 0x0 0x3000>;
  2105. #address-cells = <0x2>;
  2106. #size-cells = <0x2>;
  2107. ranges = <0x0 0x0 0x0 0xfe330000 0x0 0x3000>;
  2108. power-domains = <0x27 0x7>;
  2109.  
  2110. audio_clocks {
  2111. compatible = "amlogic, sm1-audio-clocks";
  2112. #clock-cells = <0x1>;
  2113. reg = <0x0 0x0 0x0 0xb0>;
  2114. phandle = <0x28>;
  2115. };
  2116.  
  2117. ddr_manager {
  2118. compatible = "amlogic, t5-audio-ddr-manager";
  2119. interrupts = <0x0 0x20 0x1 0x0 0x21 0x1 0x0 0x22 0x1 0x0 0x2d 0x1 0x0 0x24 0x1 0x0 0x25 0x1 0x0 0x26 0x1 0x0 0x2e 0x1>;
  2120. interrupt-names = "toddr_a", "toddr_b", "toddr_c", "toddr_d", "frddr_a", "frddr_b", "frddr_c", "frddr_d";
  2121. };
  2122.  
  2123. pinctrl {
  2124. compatible = "amlogic, audio-pinctrl";
  2125.  
  2126. tdm_d0_pin {
  2127. phandle = <0x2a>;
  2128.  
  2129. mux {
  2130. groups = "tdm_d0";
  2131. function = "tdmouta_lane0";
  2132. };
  2133. };
  2134.  
  2135. tdm_d1_pin {
  2136. phandle = <0x2b>;
  2137.  
  2138. mux {
  2139. groups = "tdm_d1";
  2140. function = "tdmina_lane1";
  2141. };
  2142. };
  2143.  
  2144. tdm_clk_pin {
  2145. phandle = <0x2c>;
  2146.  
  2147. mux {
  2148. groups = "tdm_sclk0", "tdm_lrclk0";
  2149. function = "tdm_clk_outa";
  2150. };
  2151. };
  2152. };
  2153.  
  2154. tdm@0 {
  2155. compatible = "amlogic, t5-snd-tdma";
  2156. #sound-dai-cells = <0x0>;
  2157. dai-tdm-lane-slot-mask-in = <0x0 0x1>;
  2158. dai-tdm-lane-slot-mask-out = <0x1 0x0>;
  2159. dai-tdm-clk-sel = <0x0>;
  2160. clocks = <0x28 0x24 0xd 0x35>;
  2161. clock-names = "mclk", "clk_srcpll";
  2162. pinctrl-names = "tdm_pins";
  2163. pinctrl-0 = <0x29 0x2a 0x2b 0x2c>;
  2164. status = "okay";
  2165. phandle = <0x99>;
  2166. };
  2167.  
  2168. tdm@1 {
  2169. compatible = "amlogic, t5-snd-tdmb";
  2170. #sound-dai-cells = <0x0>;
  2171. dai-tdm-lane-slot-mask-in = <0x0 0x1 0x0 0x0>;
  2172. dai-tdm-lane-slot-mask-out = <0x1 0x1 0x1 0x1>;
  2173. dai-tdm-clk-sel = <0x1>;
  2174. clocks = <0x28 0x25 0xd 0x37>;
  2175. clock-names = "mclk", "clk_srcpll";
  2176. pinctrl-names = "tdm_pins";
  2177. pinctrl-0;
  2178. i2s2hdmi = <0x1>;
  2179. status = "okay";
  2180. phandle = <0x9b>;
  2181. };
  2182.  
  2183. tdm@2 {
  2184. compatible = "amlogic, t5-snd-tdmc";
  2185. #sound-dai-cells = <0x0>;
  2186. dai-tdm-lane-slot-mask-in = <0x1>;
  2187. dai-tdm-lane-slot-mask-out = <0x1>;
  2188. dai-tdm-clk-sel = <0x2>;
  2189. clocks = <0x28 0x26 0x28 0x3a 0xd 0x39>;
  2190. clock-names = "mclk", "mclk_pad", "clk_srcpll";
  2191. samesource_sel = <0x3>;
  2192. start_clk_enable = <0x1>;
  2193. clk_tuning_enable = <0x1>;
  2194. status = "okay";
  2195. phandle = <0x9c>;
  2196. };
  2197.  
  2198. spdif@0 {
  2199. compatible = "amlogic, tm2-revb-snd-spdif-a";
  2200. #sound-dai-cells = <0x0>;
  2201. clocks = <0xd 0x35 0xd 0x9 0x28 0x10 0x28 0x11 0x28 0x2a 0x28 0x2b>;
  2202. clock-names = "sysclk", "fixed_clk", "gate_spdifin", "gate_spdifout", "clk_spdifin", "clk_spdifout";
  2203. interrupts = <0x0 0x23 0x1>;
  2204. interrupt-names = "irq_spdifin";
  2205. pinctrl-names = "spdif_pins", "spdif_pins_mute";
  2206. pinctrl-0 = <0x2d>;
  2207. pinctrl-1 = <0x2e>;
  2208. clk_tuning_enable = <0x1>;
  2209. status = "okay";
  2210. phandle = <0x9f>;
  2211. };
  2212.  
  2213. spdif@1 {
  2214. compatible = "amlogic, tm2-revb-snd-spdif-b";
  2215. #sound-dai-cells = <0x0>;
  2216. clocks = <0xd 0x37 0x28 0x15 0x28 0x31>;
  2217. clock-names = "sysclk", "gate_spdifout", "clk_spdifout";
  2218. status = "okay";
  2219. phandle = <0xa0>;
  2220. };
  2221.  
  2222. pdm {
  2223. compatible = "amlogic, sm1-snd-pdm";
  2224. #sound-dai-cells = <0x0>;
  2225. clocks = <0x28 0x1 0xd 0x7 0xd 0x3b 0x28 0x2f 0x28 0x30>;
  2226. clock-names = "gate", "sysclk_srcpll", "dclk_srcpll", "pdm_dclk", "pdm_sysclk";
  2227. pinctrl-names = "pdm_pins";
  2228. pinctrl-0 = <0x2f>;
  2229. filter_mode = <0x1>;
  2230. status = "okay";
  2231. phandle = <0x9e>;
  2232. };
  2233.  
  2234. resample@0 {
  2235. compatible = "amlogic, t5-resample-a";
  2236. clocks = <0xd 0x3b 0x28 0x29 0x28 0x2c>;
  2237. clock-names = "resample_pll", "resample_src", "resample_clk";
  2238. resample_module = <0x4>;
  2239. status = "disabled";
  2240. };
  2241.  
  2242. resample@1 {
  2243. compatible = "amlogic, t5-resample-b";
  2244. clocks = <0xd 0x3b 0x28 0x29 0x28 0x32>;
  2245. clock-names = "resample_pll", "resample_src", "resample_clk";
  2246. capture_sample_rate = <0x3e80>;
  2247. status = "disabled";
  2248. };
  2249.  
  2250. vad {
  2251. compatible = "amlogic, snd-vad";
  2252. #sound-dai-cells = <0x0>;
  2253. clocks = <0x28 0x1b 0xd 0xb 0x28 0x35>;
  2254. clock-names = "gate", "pll", "clk";
  2255. interrupts = <0x0 0x27 0x1 0x0 0x2c 0x1>;
  2256. interrupt-names = "irq_wakeup", "irq_frame_sync";
  2257. src = <0x4>;
  2258. level = <0x1>;
  2259. status = "okay";
  2260. };
  2261.  
  2262. loopback@0 {
  2263. compatible = "amlogic, t5-loopbacka";
  2264. #sound-dai-cells = <0x0>;
  2265. clocks = <0x28 0x1 0xd 0x7 0xd 0x3b 0x28 0x2f 0x28 0x30 0xd 0x35 0x28 0x24>;
  2266. clock-names = "pdm_gate", "pdm_sysclk_srcpll", "pdm_dclk_srcpll", "pdm_dclk", "pdm_sysclk", "tdminlb_mpll", "tdminlb_mclk";
  2267. datain_src = <0x4>;
  2268. datain_chnum = <0x2>;
  2269. datain_chmask = <0x3>;
  2270. datain-lane-mask-in = <0x1 0x0 0x0 0x0>;
  2271. mclk-fs = <0x100>;
  2272. datalb_src = <0x1>;
  2273. datalb_chnum = <0x2>;
  2274. datalb_chmask = <0x3>;
  2275. datalb-lane-mask-in = <0x1 0x0 0x0 0x0>;
  2276. status = "okay";
  2277. phandle = <0xa1>;
  2278. };
  2279.  
  2280. loopback@1 {
  2281. compatible = "amlogic, t5-loopbackb";
  2282. #sound-dai-cells = <0x0>;
  2283. clocks = <0x28 0x1 0xd 0x7 0xd 0x3b 0x28 0x2f 0x28 0x30 0xd 0x35 0x28 0x24>;
  2284. clock-names = "pdm_gate", "pdm_sysclk_srcpll", "pdm_dclk_srcpll", "pdm_dclk", "pdm_sysclk", "tdminlb_mpll", "tdminlb_mclk";
  2285. mclk-fs = <0x100>;
  2286. datain_src = <0x4>;
  2287. datain_chnum = <0x4>;
  2288. datain_chmask = <0xf>;
  2289. datain-lane-mask-in = <0x1 0x0 0x1 0x0>;
  2290. datalb_src = <0x1>;
  2291. datalb_chnum = <0x2>;
  2292. datalb_chmask = <0x3>;
  2293. datalb-lane-mask-in = <0x1 0x0 0x0 0x0>;
  2294. status = "disabled";
  2295. };
  2296.  
  2297. effect {
  2298. compatible = "amlogic, snd-effect-v3";
  2299. #sound-dai-cells = <0x0>;
  2300. clocks = <0x28 0x16 0xd 0xb 0x28 0x34>;
  2301. clock-names = "gate", "srcpll", "eqdrc";
  2302. eqdrc_module = <0x2>;
  2303. lane_mask = <0x1>;
  2304. channel_mask = <0x3>;
  2305. status = "okay";
  2306. };
  2307. };
  2308.  
  2309. aml_snd_iomap {
  2310. compatible = "amlogic, snd-iomap";
  2311. status = "okay";
  2312. #address-cells = <0x2>;
  2313. #size-cells = <0x2>;
  2314. ranges;
  2315.  
  2316. pdm_bus {
  2317. reg = <0x0 0xfe331000 0x0 0x400>;
  2318. };
  2319.  
  2320. audiobus_base {
  2321. reg = <0x0 0xfe330000 0x0 0x1000>;
  2322. };
  2323.  
  2324. audiolocker_base {
  2325. reg = <0x0 0xfe331400 0x0 0x400>;
  2326. };
  2327.  
  2328. eqdrc_base {
  2329. reg = <0x0 0xfe332000 0x0 0x1000>;
  2330. };
  2331.  
  2332. vad_base {
  2333. reg = <0x0 0xfe331800 0x0 0x400>;
  2334. };
  2335.  
  2336. resampleA_base {
  2337. reg = <0x0 0xfe331c00 0x0 0x104>;
  2338. };
  2339.  
  2340. resampleB_base {
  2341. reg = <0x0 0xfe334000 0x0 0x104>;
  2342. };
  2343. };
  2344.  
  2345. dwc2_a@fdd00000 {
  2346. compatible = "amlogic,dwc2";
  2347. status = "okay";
  2348. device_name = "dwc2_a";
  2349. reg = <0x0 0xfdd00000 0x0 0x100000>;
  2350. interrupts = <0x0 0x83 0x4>;
  2351. pl-periph-id = <0x0>;
  2352. clock-src = "usb0";
  2353. port-id = <0x0>;
  2354. port-type = <0x2>;
  2355. port-speed = <0x0>;
  2356. port-config = <0x0>;
  2357. port-dma = <0x0>;
  2358. port-id-mode = <0x0>;
  2359. usb-fifo = <0x2d8>;
  2360. cpu-type = "v2";
  2361. phy-reg = <0xfe03a000>;
  2362. phy-reg-size = <0xa0>;
  2363. phy-interface = <0x2>;
  2364. clocks = <0xd 0x125 0xd 0x12f>;
  2365. clock-names = "usb_general", "usb1";
  2366. controller-type = <0x3>;
  2367. };
  2368.  
  2369. dolby_fw {
  2370. compatible = "amlogic, dolby_fw";
  2371. mem_size = <0x100000>;
  2372. status = "okay";
  2373. };
  2374.  
  2375. pcie@f5000000 {
  2376. compatible = "amlogic, amlogic-pcie-v2", "snps,dw-pcie";
  2377. reg = <0x0 0xf5000000 0x0 0x400000 0x0 0xfe02c000 0x0 0x2000 0x0 0xf5400000 0x0 0x200000 0x0 0xfe02a000 0x0 0x2000 0x0 0xfe002044 0x0 0x10>;
  2378. reg-names = "elbi", "cfg", "config", "phy", "reset";
  2379. interrupts = <0x0 0x8d 0x1>;
  2380. #interrupt-cells = <0x1>;
  2381. bus-range = <0x0 0xff>;
  2382. #address-cells = <0x3>;
  2383. #size-cells = <0x2>;
  2384. interrupt-map-mask = <0x0 0x0 0x0 0x0>;
  2385. interrupt-map = <0x0 0x0 0x0 0x0 0x1 0x0 0x8f 0x1>;
  2386. device_type = "pci";
  2387. ranges = <0x81000000 0x0 0x0 0x0 0xf5600000 0x0 0x100000 0x82000000 0x0 0xf5700000 0x0 0xf5700000 0x0 0x1900000>;
  2388. num-lanes = <0x1>;
  2389. pcie-num = <0x1>;
  2390. clocks = <0xd 0x2d 0xd 0x124 0xd 0x126>;
  2391. clock-names = "pcie_refpll", "pcie", "pcie_phy";
  2392. gpio-type = <0x2>;
  2393. pcie-apb-rst-bit = <0xe>;
  2394. pcie-phy-rst-bit = <0xd>;
  2395. pcie-ctrl-a-rst-bit = <0xc>;
  2396. pwr-ctl = <0x0>;
  2397. pcie-ctrl-sleep-shift = <0xf>;
  2398. pcie-hhi-mem-pd-shift = <0x1a>;
  2399. pcie-hhi-mem-pd-mask = <0xf>;
  2400. pcie-ctrl-iso-shift = <0xf>;
  2401. status = "disable";
  2402. reset-gpio = <0x1d 0x37 0x0>;
  2403. };
  2404.  
  2405. mmc@fe08c000 {
  2406. compatible = "amlogic,meson-axg-mmc";
  2407. reg = <0x0 0xfe08c000 0x0 0x800 0x0 0xfe000168 0x0 0x4 0x0 0xfe004000 0x0 0x4>;
  2408. interrupts = <0x0 0xb2 0x1>;
  2409. status = "okay";
  2410. clocks = <0xd 0x111 0xd 0xd5 0xd 0xd7 0x1a 0xd 0x29 0xd 0x29>;
  2411. clock-names = "core", "mux0", "mux1", "clkin0", "clkin1", "clkin2";
  2412. card_type = <0x1>;
  2413. ignore_desc_busy;
  2414. mmc_debug_flag;
  2415. src_clk_rate = <0x44aa2000>;
  2416. pinctrl-0 = <0x30 0x31>;
  2417. pinctrl-1 = <0x32>;
  2418. pinctrl-names = "default", "clk-gate";
  2419. bus-width = <0x8>;
  2420. cap-mmc-highspeed;
  2421. mmc-ddr-1_8v;
  2422. mmc-hs200-1_8v;
  2423. max-frequency = <0xbebc200>;
  2424. non-removable;
  2425. disable-wp;
  2426. };
  2427.  
  2428. sd@fe08a000 {
  2429. compatible = "amlogic,meson-axg-mmc";
  2430. reg = <0x0 0xfe08a000 0x0 0x800 0x0 0xfe00016c 0x0 0x4 0x0 0xfe004024 0x0 0x4>;
  2431. interrupts = <0x0 0xb1 0x1>;
  2432. status = "okay";
  2433. clocks = <0xd 0x110 0xd 0xdb 0xd 0xdd 0x1a 0xd 0x5>;
  2434. clock-names = "core", "mux0", "mux1", "clkin0", "clkin1";
  2435. card_type = <0x5>;
  2436. mmc_debug_flag;
  2437. pinctrl-0 = <0x33>;
  2438. pinctrl-1 = <0x34>;
  2439. pinctrl-2 = <0x35>;
  2440. pinctrl-3 = <0x36 0x33 0x37>;
  2441. pinctrl-4 = <0x36 0x35 0x37>;
  2442. pinctrl-5 = <0x33 0x38>;
  2443. pinctrl-6 = <0x36 0x37>;
  2444. pinctrl-7 = <0x33 0x38>;
  2445. pinctrl-8 = <0x36 0x37>;
  2446. pinctrl-names = "sd_default", "clk-gate", "sd_1bit_pins", "sd_clk_cmd_uart_pins", "sd_1bit_uart_pins", "sd_to_ao_uart_pins", "ao_to_sd_uart_pins", "sd_to_ao_jtag_pins", "ao_to_sd_jtag_pins";
  2447. bus-width = <0x4>;
  2448. cap-sd-highspeed;
  2449. max-frequency = <0xbebc200>;
  2450. disable-wp;
  2451. cd-gpios = <0x1d 0x14 0x0>;
  2452. dat1-gpios = <0x1d 0xf 0x0>;
  2453. };
  2454.  
  2455. sdio@fe088000 {
  2456. compatible = "amlogic,meson-axg-mmc";
  2457. reg = <0x0 0xfe088000 0x0 0x800 0x0 0xfe00016c 0x0 0x4 0x0 0xfe00400c 0x0 0x4>;
  2458. interrupts = <0x0 0xb0 0x4>;
  2459. status = "okay";
  2460. clocks = <0xd 0x10f 0xd 0xd8 0xd 0xda 0x1a 0xd 0x5>;
  2461. clock-names = "core", "mux0", "mux1", "clkin0", "clkin1";
  2462. card_type = <0x3>;
  2463. mmc_debug_flag;
  2464. cap-sdio-irq;
  2465. keep-power-in-suspend;
  2466. use_intf3_tuning;
  2467. pinctrl-0 = <0x39>;
  2468. pinctrl-1 = <0x3a>;
  2469. pinctrl-names = "default", "clk-gate";
  2470. #address-cells = <0x1>;
  2471. #size-cells = <0x0>;
  2472. bus-width = <0x4>;
  2473. cap-sd-highspeed;
  2474. sd-uhs-sdr50;
  2475. sd-uhs-sdr104;
  2476. max-frequency = <0xbebc200>;
  2477. non-removable;
  2478. disable-wp;
  2479.  
  2480. wifi@1 {
  2481. reg = <0x1>;
  2482. compatible = "brcm,bcm4329-fmac";
  2483. };
  2484. };
  2485.  
  2486. nfc@fe08c800 {
  2487. compatible = "amlogic,meson-nfc-single-ecc-bl2ex";
  2488. status = "disabled";
  2489. reg = <0x0 0xfe08c800 0x0 0x200>;
  2490. interrupts = <0x0 0xaf 0x1>;
  2491. clocks = <0xd 0x111 0xd 0x5>;
  2492. clock-names = "gate", "fdiv2pll";
  2493. nand_clk_ctrl = <0xfe08c000>;
  2494. #address-cells = <0x1>;
  2495. #size-cells = <0x0>;
  2496. pinctrl-names = "nand_norb_mod", "nand_cs_only";
  2497. pinctrl-0 = <0x3b>;
  2498. pinctrl-1 = <0x3c>;
  2499. bl_mode = <0x1>;
  2500. fip_copies = <0x4>;
  2501. fip_size = <0x200000>;
  2502. ship_bad_block = <0x1>;
  2503. disa_irq_flag = <0x1>;
  2504.  
  2505. nand@bootloader {
  2506. reg = <0x0>;
  2507. #address-cells = <0x1>;
  2508. #size-cells = <0x1>;
  2509. nand-ecc-maximize;
  2510.  
  2511. partition@0 {
  2512. label = "bootloader";
  2513. reg = <0x0 0x0>;
  2514. };
  2515. };
  2516.  
  2517. nand@normal {
  2518. reg = <0x0>;
  2519. #address-cells = <0x1>;
  2520. #size-cells = <0x1>;
  2521. nand-ecc-maximize;
  2522.  
  2523. partition@0 {
  2524. label = "bl2e";
  2525. reg = <0x0 0x0>;
  2526. };
  2527.  
  2528. partition@1 {
  2529. label = "bl2x";
  2530. reg = <0x0 0x0>;
  2531. };
  2532.  
  2533. partition@2 {
  2534. label = "ddrfip";
  2535. reg = <0x0 0x0>;
  2536. };
  2537.  
  2538. partition@3 {
  2539. label = "tpl";
  2540. reg = <0x0 0x0>;
  2541. };
  2542.  
  2543. partition@4 {
  2544. label = "logo";
  2545. reg = <0x0 0x200000>;
  2546. };
  2547.  
  2548. partition@5 {
  2549. label = "recovery";
  2550. reg = <0x0 0x1000000>;
  2551. };
  2552.  
  2553. partition@6 {
  2554. label = "boot";
  2555. reg = <0x0 0xf00000>;
  2556. };
  2557.  
  2558. partition@7 {
  2559. label = "system";
  2560. reg = <0x0 0x11800000>;
  2561. };
  2562.  
  2563. partition@8 {
  2564. label = "data";
  2565. reg = <0x0 0xffffffff>;
  2566. };
  2567. };
  2568. };
  2569.  
  2570. ethernet@fdc00000 {
  2571. compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
  2572. reg = <0x0 0xfdc00000 0x0 0x10000 0x0 0xfe024000 0x0 0x8>;
  2573. interrupts = <0x0 0x4a 0x4>;
  2574. interrupt-names = "macirq";
  2575. power-domains = <0x27 0x5>;
  2576. clocks = <0xd 0x118 0xd 0x5 0xd 0x39>;
  2577. clock-names = "stmmaceth", "clkin0", "clkin1";
  2578. rx-fifo-depth = <0x1000>;
  2579. tx-fifo-depth = <0x800>;
  2580. status = "okay";
  2581. phy-handle = <0x3d>;
  2582. phy-mode = "rmii";
  2583.  
  2584. mdio {
  2585. #address-cells = <0x1>;
  2586. #size-cells = <0x0>;
  2587. compatible = "snps,dwmac-mdio";
  2588. phandle = <0x23>;
  2589. };
  2590. };
  2591.  
  2592. serial@fe078000 {
  2593. compatible = "amlogic,meson-uart";
  2594. reg = <0x0 0xfe078000 0x0 0x18>;
  2595. interrupts = <0x0 0xa8 0x1>;
  2596. status = "okay";
  2597. clocks = <0x1a 0xd 0x119>;
  2598. clock-names = "clk_uart", "clk_gate";
  2599. xtal_tick_en = <0x3>;
  2600. fifosize = <0x40>;
  2601. pinctrl-names = "default";
  2602. pinctrl-0 = <0x3e>;
  2603. uart-has-rtscts;
  2604. };
  2605.  
  2606. serial@fe07c000 {
  2607. compatible = "amlogic,meson-uart";
  2608. reg = <0x0 0xfe07c000 0x0 0x18>;
  2609. interrupts = <0x0 0xaa 0x1>;
  2610. status = "disabled";
  2611. clocks = <0x1a 0xd 0x11b>;
  2612. clock-names = "clk_uart", "clk_gate";
  2613. fifosize = <0x40>;
  2614. pinctrl-names = "default";
  2615. pinctrl-0 = <0x3f>;
  2616. };
  2617.  
  2618. serial@fe07e000 {
  2619. compatible = "amlogic,meson-uart";
  2620. status = "disabled";
  2621. reg = <0x0 0xfe07e000 0x0 0x18>;
  2622. interrupts = <0x0 0xab 0x1>;
  2623. clocks = <0x1a 0xd 0x11c>;
  2624. clock-names = "clk_uart", "clk_gate";
  2625. fifosize = <0x40>;
  2626. pinctrl-names = "default";
  2627. pinctrl-0 = <0x40>;
  2628. };
  2629.  
  2630. serial@fe080000 {
  2631. compatible = "amlogic,meson-uart";
  2632. status = "disabled";
  2633. reg = <0x0 0xfe080000 0x0 0x18>;
  2634. interrupts = <0x0 0xac 0x1>;
  2635. clocks = <0x1a 0xd 0x11d>;
  2636. clock-names = "clk_uart", "clk_gate";
  2637. fifosize = <0x40>;
  2638. pinctrl-names = "default";
  2639. pinctrl-0 = <0x41>;
  2640. };
  2641. };
  2642.  
  2643. mesonstream {
  2644. compatible = "amlogic, codec, streambuf";
  2645. dev_name = "mesonstream";
  2646. status = "okay";
  2647. clocks = <0xd 0x109 0xd 0x98 0xd 0x9f 0xd 0xad 0xd 0xa6>;
  2648. clock-names = "vdec", "clk_vdec_mux", "clk_hcodec_mux", "clk_hevcf_mux", "clk_hevcb_mux";
  2649. };
  2650.  
  2651. vdec {
  2652. compatible = "amlogic, vdec-pm-pd";
  2653. dev_name = "vdec.0";
  2654. status = "okay";
  2655. interrupts = <0x0 0x3 0x1 0x0 0x17 0x1 0x0 0x20 0x1 0x0 0x5b 0x1 0x0 0x5c 0x1 0x0 0x5d 0x1 0x0 0x48 0x1>;
  2656. interrupt-names = "vsync", "demux", "parser", "mailbox_0", "mailbox_1", "mailbox_2", "parser_b";
  2657. power-domains = <0x27 0x1 0x27 0x0>;
  2658. power-domain-names = "pwrc-vdec", "pwrc-hevc";
  2659. };
  2660.  
  2661. cpu_ver_name {
  2662. compatible = "amlogic, cpu-major-id-s4";
  2663. };
  2664.  
  2665. vcodec_dec {
  2666. compatible = "amlogic, vcodec-dec";
  2667. dev_name = "aml-vcodec-dec";
  2668. status = "okay";
  2669. };
  2670.  
  2671. ddr_bandwidth {
  2672. compatible = "amlogic,ddr-bandwidth-s4";
  2673. status = "okay";
  2674. reg = <0x0 0xfe036000 0x0 0x400 0x0 0xfe036c00 0x0 0x100>;
  2675. interrupts = <0x0 0x4e 0x1>;
  2676. interrupt-names = "ddr_bandwidth";
  2677. };
  2678.  
  2679. dmc_monitor {
  2680. compatible = "amlogic,dmc_monitor-s4";
  2681. status = "okay";
  2682. reg = <0x0 0xfe036000 0x0 0x400>;
  2683. reg_base = <0xfe037000>;
  2684. interrupts = <0x0 0x3e 0x1>;
  2685. };
  2686.  
  2687. amhdmitx {
  2688. compatible = "amlogic, amhdmitx-sc2";
  2689. dev_name = "amhdmitx";
  2690. status = "okay";
  2691. power-domains = <0x27 0x2>;
  2692. vend-data = <0x42>;
  2693. pinctrl-names = "default";
  2694. pinctrl-0 = <0x43 0x44>;
  2695. clock-names = "venci_top_gate", "venci_0_gate", "venci_1_gate", "hdmi_vapb_clk", "hdmi_vpu_clk";
  2696. interrupts = <0x0 0xcc 0x1 0x0 0xc5 0x1>;
  2697. interrupt-names = "hdmitx_hpd", "viu1_vsync";
  2698. ic_type = <0xf>;
  2699. hdmi_rext = <0x514>;
  2700. reg = <0x0 0x0 0x0 0x0 0x0 0xff000000 0x0 0x40000 0x0 0x0 0x0 0x0 0x0 0xfe308000 0x0 0x8000 0x0 0xfe300000 0x0 0x8000 0x0 0xfe032000 0x0 0x100 0x0 0xfe008000 0x0 0x400 0x0 0xfe00c000 0x0 0x800 0x0 0xfe002000 0x0 0x400 0x0 0xfe010000 0x0 0x100 0x0 0xfe000000 0x0 0x2000>;
  2701. reg-names = "cbus", "vpu", "hiu", "hdmitxdwc", "hdmitxtop", "esm", "anactrl", "pwrctrl", "resetctrl", "sysctrl", "clkctrl";
  2702.  
  2703. vend_data {
  2704. vendor_name = "Amlogic";
  2705. product_desc = "MBox Meson Ref";
  2706. vendor_id = <0x0>;
  2707. phandle = <0x42>;
  2708. };
  2709. };
  2710.  
  2711. aocec {
  2712. compatible = "amlogic, aocec-s4";
  2713. dev_name = "aocec";
  2714. status = "okay";
  2715. vendor_name = "Amlogic";
  2716. vendor_id = <0xffffff>;
  2717. product_desc = "S4";
  2718. cec_osd_string = "AML_MBOX";
  2719. cec_version = <0x5>;
  2720. port_num = <0x1>;
  2721. output = <0x1>;
  2722. cec_sel = <0x1>;
  2723. ee_cec;
  2724. arc_port_mask = <0x1>;
  2725. interrupts = <0x0 0xb4 0x1 0x0 0xb3 0x1>;
  2726. interrupt-names = "hdmi_aocecb", "hdmi_aocec";
  2727. pinctrl-names = "default", "hdmitx_aocecb", "cec_pin_sleep";
  2728. pinctrl-0 = <0x45>;
  2729. pinctrl-1 = <0x46>;
  2730. pinctrl-2 = <0x46>;
  2731. clocks = <0xd 0x4c 0xd 0x51>;
  2732. clock-names = "ceca_clk", "cecb_clk";
  2733. reg = <0x0 0xfe044000 0x0 0x2ff 0x0 0xfe010000 0x0 0xfff 0x0 0xfe000000 0x0 0xfff>;
  2734. reg-names = "ao", "periphs", "clock";
  2735. };
  2736.  
  2737. aml_dma {
  2738. compatible = "amlogic,aml_txlx_dma";
  2739. reg = <0x0 0xfe440400 0x0 0x48>;
  2740. interrupts = <0x0 0x18 0x1>;
  2741.  
  2742. aml_aes {
  2743. compatible = "amlogic,aes_g12a_dma";
  2744. dev_name = "aml_aes_dma";
  2745. status = "okay";
  2746. iv_swap = [00];
  2747. };
  2748.  
  2749. aml_sha {
  2750. compatible = "amlogic,sha_dma";
  2751. dev_name = "aml_sha_dma";
  2752. status = "okay";
  2753. };
  2754.  
  2755. aml_tdes {
  2756. compatible = "amlogic,des_dma,tdes_dma";
  2757. dev_name = "aml_tdes_dma";
  2758. status = "okay";
  2759. };
  2760. };
  2761.  
  2762. rng {
  2763. compatible = "amlogic,meson-rng";
  2764. status = "okay";
  2765. #address-cells = <0x2>;
  2766. #size-cells = <0x2>;
  2767. reg = <0x0 0xfe440788 0x0 0xc>;
  2768. quality = [03 e8];
  2769. version = <0x2>;
  2770. };
  2771.  
  2772. canvas {
  2773. compatible = "amlogic, meson, canvas";
  2774. status = "okay";
  2775. reg = <0x0 0xfe036048 0x0 0x2000>;
  2776. };
  2777.  
  2778. codec_io {
  2779. compatible = "amlogic, meson-s4, codec-io";
  2780. status = "okay";
  2781. #address-cells = <0x2>;
  2782. #size-cells = <0x2>;
  2783. ranges;
  2784. reg = <0x0 0xfe002000 0x0 0x2000 0x0 0xfe320000 0x0 0x10000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xff000000 0x0 0x40000 0x0 0xfe036000 0x0 0x2000 0x0 0x0 0x0 0x0>;
  2785. reg-names = "cbus", "dosbus", "hiubus", "aobus", "vcbus", "dmcbus", "efusebus";
  2786. };
  2787.  
  2788. amvenc_avc {
  2789. compatible = "amlogic, amvenc_avc";
  2790. dev_name = "amvenc_avc";
  2791. status = "disabled";
  2792. clocks = <0xd 0x9b>;
  2793. clock-names = "cts_hcodec_aclk";
  2794. interrupts = <0x0 0x5d 0x1>;
  2795. interrupt-names = "mailbox_2";
  2796. reset-names = "hcodec_rst";
  2797. resets = <0x26 0xa3>;
  2798. };
  2799.  
  2800. jpegenc {
  2801. compatible = "amlogic, jpegenc";
  2802. dev_name = "jpegenc";
  2803. status = "disabled";
  2804. clocks = <0xd 0x9b>;
  2805. clock-names = "cts_jpegenc_aclk";
  2806. interrupts = <0x0 0x5d 0x1>;
  2807. interrupt-names = "mailbox_2";
  2808. reset-names = "jpegenc_rst";
  2809. resets = <0x26 0xa3>;
  2810. };
  2811.  
  2812. hevc_enc {
  2813. compatible = "cnm, HevcEnc";
  2814. dev_name = "HevcEnc";
  2815. status = "disabled";
  2816. interrupts = <0x0 0x5e 0x1>;
  2817. interrupt-names = "wave420l_irq";
  2818. #address-cells = <0x2>;
  2819. #size-cells = <0x2>;
  2820. clocks = <0xd 0xb0 0xd 0xb3 0xd 0xb6>;
  2821. clock-names = "cts_wave420_aclk", "cts_wave420_bclk", "cts_wave420_cclk";
  2822. ranges;
  2823.  
  2824. io_reg_base {
  2825. reg = <0x0 0xfe310000 0x0 0x4000>;
  2826. };
  2827. };
  2828.  
  2829. vpu {
  2830. compatible = "amlogic, vpu-s4";
  2831. status = "okay";
  2832. reg = <0x0 0xfe000000 0x0 0x100 0x0 0xfe00c000 0x0 0x70 0x0 0xff000000 0x0 0xa000>;
  2833. clocks = <0xd 0xd0 0xd 0x135 0xd 0xb9 0xd 0xbc 0xd 0xbd>;
  2834. clock-names = "vapb_clk", "vpu_intr_gate", "vpu_clk0", "vpu_clk1", "vpu_clk";
  2835. clk_level = <0x7>;
  2836. };
  2837.  
  2838. rdma {
  2839. compatible = "amlogic, meson-sc2, rdma";
  2840. status = "okay";
  2841. interrupts = <0x0 0xd7 0x1>;
  2842. interrupt-names = "rdma";
  2843. reset-names = "rdma";
  2844. resets = <0x26 0x1c>;
  2845. };
  2846.  
  2847. vclk_serve {
  2848. compatible = "amlogic, vclk_serve";
  2849. status = "okay";
  2850. reg = <0x0 0xfe008000 0x0 0x300 0x0 0xfe000000 0x0 0x4a0>;
  2851. };
  2852.  
  2853. vdac {
  2854. compatible = "amlogic, vdac-s4";
  2855. status = "okay";
  2856. };
  2857.  
  2858. vout {
  2859. compatible = "amlogic, vout";
  2860. status = "okay";
  2861. fr_policy = <0x2>;
  2862. };
  2863.  
  2864. dummy_venc {
  2865. compatible = "amlogic, dummy_venc_s4";
  2866. status = "okay";
  2867. };
  2868.  
  2869. adc {
  2870. compatible = "amlogic, adc-s4";
  2871. status = "okay";
  2872. reg = <0x0 0xff654000 0x0 0x2000 0x0 0xfe008000 0x0 0x2000>;
  2873. };
  2874.  
  2875. ir@8000 {
  2876. compatible = "amlogic, meson-ir";
  2877. reg = <0x0 0xfe084040 0x0 0x44 0x0 0xfe084000 0x0 0x20>;
  2878. status = "okay";
  2879. protocol = <0x1>;
  2880. interrupts = <0x0 0x16 0x1>;
  2881. map = <0x47>;
  2882. max_frame_time = <0xc8>;
  2883. pinctrl-0 = <0x48>;
  2884. pinctrl-names = "default";
  2885. };
  2886.  
  2887. p_tsensor@fe020000 {
  2888. compatible = "amlogic, r1p1-tsensor";
  2889. status = "okay";
  2890. reg = <0x0 0xfe020000 0x0 0x50>;
  2891. tsensor_id = <0x1>;
  2892. cal_type = <0x11>;
  2893. cal_coeff = <0x144 0x1a8 0xc57 0x24c3>;
  2894. rtemp = <0x1adb0>;
  2895. interrupts = <0x0 0x1e 0x4>;
  2896. clocks = <0xd 0x8a>;
  2897. clock-names = "ts_comp";
  2898. #thermal-sensor-cells = <0x1>;
  2899. phandle = <0x49>;
  2900. };
  2901.  
  2902. meson-cooldev@0 {
  2903. status = "okay";
  2904. compatible = "amlogic, meson-cooldev";
  2905.  
  2906. cooling_devices {
  2907.  
  2908. cpucore_cool_cluster0 {
  2909. cluster_id = <0x0>;
  2910. node_name = "cpucore_cool0";
  2911. device_type = "cpucore";
  2912. };
  2913.  
  2914. gpufreq_cool {
  2915. dyn_coeff = <0x8c>;
  2916. node_name = "bifrost";
  2917. device_type = "gpufreq";
  2918. };
  2919. };
  2920.  
  2921. cpucore_cool0 {
  2922. #cooling-cells = <0x2>;
  2923. };
  2924. };
  2925.  
  2926. thermal-zones {
  2927.  
  2928. soc_thermal {
  2929. polling-delay = <0x3e8>;
  2930. polling-delay-passive = <0x64>;
  2931. sustainable-power = <0x488>;
  2932. thermal-sensors = <0x49 0x0>;
  2933.  
  2934. trips {
  2935.  
  2936. trip-point@0 {
  2937. temperature = <0x14c08>;
  2938. hysteresis = <0x1388>;
  2939. type = "passive";
  2940. };
  2941.  
  2942. trip-point@1 {
  2943. temperature = <0x17318>;
  2944. hysteresis = <0x1388>;
  2945. type = "passive";
  2946. phandle = <0x4a>;
  2947. };
  2948.  
  2949. trip-point@2 {
  2950. temperature = <0x19a28>;
  2951. hysteresis = <0x3e8>;
  2952. type = "critical";
  2953. };
  2954. };
  2955.  
  2956. cooling-maps {
  2957.  
  2958. cpufreq_cooling_map {
  2959. trip = <0x4a>;
  2960. cooling-device = <0x4b 0x0 0x8>;
  2961. contribution = <0x400>;
  2962. };
  2963.  
  2964. gpufreq_cooling_map {
  2965. trip = <0x4a>;
  2966. cooling-device = <0x4c 0x0 0x3>;
  2967. contribution = <0x400>;
  2968. };
  2969. };
  2970. };
  2971. };
  2972.  
  2973. ion_dev {
  2974. compatible = "amlogic, ion_dev";
  2975. memory-region = <0x4d>;
  2976. };
  2977.  
  2978. meson_uvm {
  2979. compatible = "amlogic, meson_uvm";
  2980. status = "okay";
  2981. };
  2982.  
  2983. meson_videotunnel {
  2984. compatible = "amlogic, meson_videotunnel";
  2985. status = "okay";
  2986. };
  2987.  
  2988. fb {
  2989. compatible = "amlogic, fb-s4";
  2990. memory-region = <0x4e>;
  2991. status = "okay";
  2992. interrupts = <0x0 0xc5 0x1 0x0 0xd7 0x1>;
  2993. interrupt-names = "viu-vsync", "rdma";
  2994. display_mode_default = "1080p60hz";
  2995. scale_mode = <0x1>;
  2996. display_size_default = <0x780 0x438 0x780 0x870 0x20>;
  2997. mem_size = <0x800000 0x1980000 0x100000>;
  2998. logo_addr = "0x3f800000";
  2999. mem_alloc = <0x0>;
  3000. pxp_mode = <0x0>;
  3001. };
  3002.  
  3003. meson-irblaster@fe08410c {
  3004. compatible = "amlogic, meson_irblaster";
  3005. status = "okay";
  3006. reg = <0x0 0xfe08410c 0x0 0x10>;
  3007. #irblaster-cells = <0x2>;
  3008. interrupts = <0x0 0x17 0x1>;
  3009. };
  3010.  
  3011. vdin0 {
  3012. compatible = "amlogic, vdin-s4";
  3013. dev_name = "vdin0";
  3014. status = "okay";
  3015. reserve-iomap = "true";
  3016. flag_cma = <0x0>;
  3017. interrupts = <0x0 0xd2 0x1>;
  3018. rdma-irq = <0x2>;
  3019. clocks = <0xd 0xb 0xd 0xd4>;
  3020. clock-names = "fclk_div5", "cts_vdin_meas_clk";
  3021. vdin_id = <0x0>;
  3022. cma_size = <0x14>;
  3023. tv_bit_mode = <0x1>;
  3024. };
  3025.  
  3026. vdin1 {
  3027. compatible = "amlogic, vdin-s4";
  3028. dev_name = "vdin1";
  3029. status = "okay";
  3030. reserve-iomap = "true";
  3031. flag_cma = <0x0>;
  3032. interrupts = <0x0 0xd4 0x1>;
  3033. rdma-irq = <0x4>;
  3034. vdin_id = <0x1>;
  3035. memory-region = <0x4f>;
  3036. tv_bit_mode = <0x1>;
  3037. };
  3038.  
  3039. meson-amvideom {
  3040. compatible = "amlogic, amvideom-s4";
  3041. dev_name = "amvideom";
  3042. status = "okay";
  3043. interrupts = <0x0 0xc5 0x1>;
  3044. interrupt-names = "vsync";
  3045. };
  3046.  
  3047. video_composer {
  3048. compatible = "amlogic, video_composer";
  3049. dev_name = "video_composer";
  3050. status = "okay";
  3051. };
  3052.  
  3053. vpu_security {
  3054. compatible = "amlogic, meson-s4, vpu_security";
  3055. dev_name = "amlogic-vpu-security";
  3056. status = "okay";
  3057. interrupts = <0x0 0xdc 0x1>;
  3058. interrupt-names = "vpu_security";
  3059. };
  3060.  
  3061. ge2d {
  3062. compatible = "amlogic, ge2d-s4";
  3063. status = "okay";
  3064. interrupts = <0x0 0xd9 0x1>;
  3065. interrupt-names = "ge2d";
  3066. clocks = <0xd 0xd0 0xd 0x121 0xd 0xd1>;
  3067. clock-names = "clk_vapb_0", "clk_ge2d", "clk_ge2d_gate";
  3068. reg = <0x0 0xff040000 0x0 0x100>;
  3069. power-domains = <0x27 0x4>;
  3070. };
  3071.  
  3072. aml_bt {
  3073. compatible = "amlogic, aml-bt";
  3074. status = "okay";
  3075. reset-gpios = <0x1d 0x41 0x0>;
  3076. btwakeup-gpios = <0x1d 0x42 0x0>;
  3077. hostwake-gpios = <0x1d 0x43 0x0>;
  3078. };
  3079.  
  3080. aml_wifi {
  3081. compatible = "amlogic, aml-wifi";
  3082. status = "okay";
  3083. irq_trigger_type = "GPIO_IRQ_LOW";
  3084. pwm_config = <0x50>;
  3085. interrupt-gpios = <0x1d 0x37 0x0>;
  3086. power_on-gpios = <0x1d 0x36 0x0>;
  3087. };
  3088.  
  3089. wifi_pwm_conf {
  3090. phandle = <0x50>;
  3091.  
  3092. pwm_channel1_conf {
  3093. pwms = <0x51 0x0 0x774d 0x0>;
  3094. duty-cycle = <0x3ba6>;
  3095. times = <0x7>;
  3096. };
  3097.  
  3098. pwm_channel2_conf {
  3099. pwms = <0x51 0x2 0x7724 0x0>;
  3100. duty-cycle = <0x3b92>;
  3101. times = <0xa>;
  3102. };
  3103. };
  3104.  
  3105. state_led {
  3106. compatible = "amlogic,state-led-aocpu";
  3107. status = "disabled";
  3108. };
  3109.  
  3110. efuse {
  3111. compatible = "amlogic, efuse";
  3112. reg = <0x0 0xfe440040 0x0 0x4>;
  3113. secureboot_mask = <0xc00>;
  3114. mem_size = <0x100000>;
  3115. read_cmd = <0x82000030>;
  3116. write_cmd = <0x82000031>;
  3117. get_max_cmd = <0x82000033>;
  3118. mem_in_base_cmd = <0x82000020>;
  3119. mem_out_base_cmd = <0x82000021>;
  3120. efuse_pattern_size = <0x600>;
  3121. key = <0x52>;
  3122. clock-names = "efuse_clk";
  3123. status = "okay";
  3124. };
  3125.  
  3126. efusekey {
  3127. keynum = <0x4>;
  3128. key0 = <0x53>;
  3129. key1 = <0x54>;
  3130. key2 = <0x55>;
  3131. key3 = <0x56>;
  3132. phandle = <0x52>;
  3133.  
  3134. key_0 {
  3135. keyname = "mac";
  3136. offset = <0x0>;
  3137. size = <0x6>;
  3138. phandle = <0x53>;
  3139. };
  3140.  
  3141. key_1 {
  3142. keyname = "mac_bt";
  3143. offset = <0x6>;
  3144. size = <0x6>;
  3145. phandle = <0x54>;
  3146. };
  3147.  
  3148. key_2 {
  3149. keyname = "mac_wifi";
  3150. offset = <0xc>;
  3151. size = <0x6>;
  3152. phandle = <0x55>;
  3153. };
  3154.  
  3155. key_3 {
  3156. keyname = "usid";
  3157. offset = <0x12>;
  3158. size = <0x10>;
  3159. phandle = <0x56>;
  3160. };
  3161. };
  3162.  
  3163. drm-amhdmitx {
  3164. status = "okay";
  3165. hdcp = "okay";
  3166. compatible = "amlogic, drm-amhdmitx";
  3167. dev_name = "meson-amhdmitx";
  3168. interrupts = <0x0 0xcc 0x1>;
  3169.  
  3170. ports {
  3171.  
  3172. port {
  3173. #address-cells = <0x1>;
  3174. #size-cells = <0x0>;
  3175.  
  3176. endpoint@0 {
  3177. reg = <0x0>;
  3178. remote-endpoint = <0x57>;
  3179. phandle = <0x5a>;
  3180. };
  3181. };
  3182. };
  3183. };
  3184.  
  3185. drm-amcvbsout {
  3186. status = "okay";
  3187. compatible = "amlogic, drm-cvbsout";
  3188. dev_name = "meson-amcvbsout";
  3189.  
  3190. ports {
  3191.  
  3192. port {
  3193. #address-cells = <0x1>;
  3194. #size-cells = <0x0>;
  3195.  
  3196. endpoint@0 {
  3197. reg = <0x0>;
  3198. remote-endpoint = <0x58>;
  3199. phandle = <0x5b>;
  3200. };
  3201. };
  3202. };
  3203. };
  3204.  
  3205. drm-lcd {
  3206. status = "disabled";
  3207. compatible = "amlogic, drm-lcd";
  3208. dev_name = "meson-lcd";
  3209.  
  3210. ports {
  3211.  
  3212. port {
  3213. #address-cells = <0x1>;
  3214. #size-cells = <0x0>;
  3215.  
  3216. endpoint@0 {
  3217. reg = <0x0>;
  3218. remote-endpoint = <0x59>;
  3219. phandle = <0x5c>;
  3220. };
  3221. };
  3222. };
  3223. };
  3224.  
  3225. drm-vpu@0xff900000 {
  3226. status = "okay";
  3227. compatible = "amlogic, meson-s4-vpu";
  3228. memory-region = <0x4e>;
  3229. osd_ver = [04];
  3230. reg = <0x0 0xff900000 0x0 0x40000 0x0 0xff63c000 0x0 0x2000 0x0 0xff638000 0x0 0x2000>;
  3231. reg-names = "base", "hhi", "dmc";
  3232. interrupts = <0x0 0xc5 0x1>;
  3233. interrupt-names = "viu-vsync";
  3234. clocks = <0xd 0xc9>;
  3235. clock-names = "vpu_clkc";
  3236. dma-coherent;
  3237. logo_addr = "0x3f800000";
  3238.  
  3239. port {
  3240. #address-cells = <0x1>;
  3241. #size-cells = <0x0>;
  3242. phandle = <0x5d>;
  3243.  
  3244. endpoint@0 {
  3245. reg = <0x0>;
  3246. remote-endpoint = <0x5a>;
  3247. phandle = <0x57>;
  3248. };
  3249.  
  3250. endpoint@1 {
  3251. reg = <0x1>;
  3252. remote-endpoint = <0x5b>;
  3253. phandle = <0x58>;
  3254. };
  3255.  
  3256. endpoint@2 {
  3257. reg = <0x2>;
  3258. remote-endpoint = <0x5c>;
  3259. phandle = <0x59>;
  3260. };
  3261. };
  3262. };
  3263.  
  3264. drm-subsystem {
  3265. status = "okay";
  3266. compatible = "amlogic, drm-subsystem";
  3267. ports = <0x5d>;
  3268. fbdev_sizes = <0x780 0x438 0x780 0x870 0x20>;
  3269.  
  3270. vpu_topology {
  3271.  
  3272. vpu_blocks {
  3273.  
  3274. block@0 {
  3275. id = [00];
  3276. index = [00];
  3277. type = [00];
  3278. block_name = "osd1_block";
  3279. num_in_links = [00];
  3280. num_out_links = [01];
  3281. out_links = <0x0 0x5e>;
  3282. phandle = <0x60>;
  3283. };
  3284.  
  3285. block@1 {
  3286. id = [01];
  3287. index = [01];
  3288. type = [00];
  3289. block_name = "osd2_block";
  3290. num_in_links = [00];
  3291. num_out_links = [01];
  3292. out_links = <0x0 0x5f>;
  3293. phandle = <0x62>;
  3294. };
  3295.  
  3296. block@3 {
  3297. id = [03];
  3298. index = [00];
  3299. type = [01];
  3300. block_name = "afbc_osd1_block";
  3301. num_in_links = [01];
  3302. in_links = <0x0 0x60>;
  3303. num_out_links = [01];
  3304. out_links = <0x0 0x61>;
  3305. phandle = <0x5e>;
  3306. };
  3307.  
  3308. block@4 {
  3309. id = [04];
  3310. index = [01];
  3311. type = [01];
  3312. block_name = "afbc_osd2_block";
  3313. num_in_links = [01];
  3314. in_links = <0x0 0x62>;
  3315. num_out_links = [01];
  3316. out_links = <0x0 0x63>;
  3317. phandle = <0x5f>;
  3318. };
  3319.  
  3320. block@6 {
  3321. id = [06];
  3322. index = [00];
  3323. type = [02];
  3324. block_name = "scaler_osd1_block";
  3325. num_in_links = [01];
  3326. in_links = <0x0 0x64>;
  3327. num_out_links = [01];
  3328. out_links = <0x0 0x65>;
  3329. phandle = <0x66>;
  3330. };
  3331.  
  3332. block@7 {
  3333. id = [07];
  3334. index = [01];
  3335. type = [02];
  3336. block_name = "scaler_osd2_block";
  3337. num_in_links = [01];
  3338. in_links = <0x0 0x5f>;
  3339. num_out_links = [01];
  3340. out_links = <0x2 0x61>;
  3341. phandle = <0x63>;
  3342. };
  3343.  
  3344. block@9 {
  3345. id = [09];
  3346. block_name = "osd_blend_block";
  3347. type = [03];
  3348. num_in_links = [02];
  3349. in_links = <0x0 0x5e 0x0 0x63>;
  3350. num_out_links = [02];
  3351. out_links = <0x0 0x64 0x1 0x65>;
  3352. phandle = <0x61>;
  3353. };
  3354.  
  3355. block@10 {
  3356. id = [0a];
  3357. block_name = "osd1_hdr_dolby_block";
  3358. type = [04];
  3359. num_in_links = [01];
  3360. in_links = <0x0 0x61>;
  3361. num_out_links = [01];
  3362. out_links = <0x0 0x66>;
  3363. phandle = <0x64>;
  3364. };
  3365.  
  3366. block@12 {
  3367. id = [0b];
  3368. block_name = "vpp_postblend_block";
  3369. type = [06];
  3370. num_in_links = [02];
  3371. in_links = <0x0 0x66 0x1 0x61>;
  3372. num_out_links = <0x0>;
  3373. phandle = <0x65>;
  3374. };
  3375.  
  3376. block@13 {
  3377. id = [0c];
  3378. index = [00];
  3379. type = [07];
  3380. block_name = "video1_block";
  3381. num_in_links = [00];
  3382. num_out_links = [00];
  3383. };
  3384.  
  3385. block@14 {
  3386. id = [0d];
  3387. index = [01];
  3388. type = [07];
  3389. block_name = "video2_block";
  3390. num_in_links = [00];
  3391. num_out_links = [00];
  3392. };
  3393. };
  3394. };
  3395.  
  3396. vpu_hw_para@0 {
  3397. osd_ver = [02];
  3398. afbc_type = [02];
  3399. has_deband = [01];
  3400. has_lut = [01];
  3401. has_rdma = [01];
  3402. osd_fifo_len = [40];
  3403. vpp_fifo_len = <0xfff>;
  3404. };
  3405. };
  3406.  
  3407. firmware {
  3408.  
  3409. android {
  3410. compatible = "android,firmware";
  3411.  
  3412. vbmeta {
  3413. compatible = "android,vbmeta";
  3414. parts = "vbmeta,boot,oem,vbmeta_system";
  3415. by_name_prefix = "/dev/block";
  3416. };
  3417. };
  3418. };
  3419.  
  3420. partitions {
  3421. parts = <0x19>;
  3422. part-0 = <0x67>;
  3423. part-1 = <0x68>;
  3424. part-2 = <0x69>;
  3425. part-3 = <0x6a>;
  3426. part-4 = <0x6b>;
  3427. part-5 = <0x6c>;
  3428. part-6 = <0x6d>;
  3429. part-7 = <0x6e>;
  3430. part-8 = <0x6f>;
  3431. part-9 = <0x70>;
  3432. part-10 = <0x71>;
  3433. part-11 = <0x72>;
  3434. part-12 = <0x73>;
  3435. part-13 = <0x74>;
  3436. part-14 = <0x75>;
  3437. part-15 = <0x76>;
  3438. part-16 = <0x77>;
  3439. part-17 = <0x78>;
  3440. part-18 = <0x79>;
  3441. part-19 = <0x7a>;
  3442. part-20 = <0x7b>;
  3443. part-21 = <0x7c>;
  3444. part-22 = <0x7d>;
  3445. part-23 = <0x7e>;
  3446. part-24 = <0x7f>;
  3447.  
  3448. frp {
  3449. pname = "frp";
  3450. size = <0x0 0x200000>;
  3451. mask = <0x1>;
  3452. phandle = <0x67>;
  3453. };
  3454.  
  3455. factory {
  3456. pname = "factory";
  3457. size = <0x0 0x800000>;
  3458. mask = <0x11>;
  3459. phandle = <0x68>;
  3460. };
  3461.  
  3462. vendor_boot_a {
  3463. pname = "vendor_boot_a";
  3464. size = <0x0 0x1800000>;
  3465. mask = <0x1>;
  3466. phandle = <0x69>;
  3467. };
  3468.  
  3469. vendor_boot_b {
  3470. pname = "vendor_boot_b";
  3471. size = <0x0 0x1800000>;
  3472. mask = <0x1>;
  3473. phandle = <0x6a>;
  3474. };
  3475.  
  3476. tee {
  3477. pname = "tee";
  3478. size = <0x0 0x2000000>;
  3479. mask = <0x1>;
  3480. phandle = <0x6b>;
  3481. };
  3482.  
  3483. logo {
  3484. pname = "logo";
  3485. size = <0x0 0x800000>;
  3486. mask = <0x1>;
  3487. phandle = <0x6c>;
  3488. };
  3489.  
  3490. misc {
  3491. pname = "misc";
  3492. size = <0x0 0x200000>;
  3493. mask = <0x1>;
  3494. phandle = <0x6d>;
  3495. };
  3496.  
  3497. dtbo_a {
  3498. pname = "dtbo_a";
  3499. size = <0x0 0x200000>;
  3500. mask = <0x1>;
  3501. phandle = <0x6e>;
  3502. };
  3503.  
  3504. dtbo_b {
  3505. pname = "dtbo_b";
  3506. size = <0x0 0x200000>;
  3507. mask = <0x1>;
  3508. phandle = <0x6f>;
  3509. };
  3510.  
  3511. cri_data {
  3512. pname = "cri_data";
  3513. size = <0x0 0x800000>;
  3514. mask = <0x2>;
  3515. phandle = <0x70>;
  3516. };
  3517.  
  3518. rsv {
  3519. pname = "rsv";
  3520. size = <0x0 0x1000000>;
  3521. mask = <0x1>;
  3522. phandle = <0x78>;
  3523. };
  3524.  
  3525. metadata {
  3526. pname = "metadata";
  3527. size = <0x0 0x1000000>;
  3528. mask = <0x1>;
  3529. phandle = <0x79>;
  3530. };
  3531.  
  3532. vbmeta_a {
  3533. pname = "vbmeta_a";
  3534. size = <0x0 0x200000>;
  3535. mask = <0x1>;
  3536. phandle = <0x7a>;
  3537. };
  3538.  
  3539. vbmeta_b {
  3540. pname = "vbmeta_b";
  3541. size = <0x0 0x200000>;
  3542. mask = <0x1>;
  3543. phandle = <0x7b>;
  3544. };
  3545.  
  3546. vbmeta_system_a {
  3547. pname = "vbmeta_system_a";
  3548. size = <0x0 0x200000>;
  3549. mask = <0x1>;
  3550. phandle = <0x7c>;
  3551. };
  3552.  
  3553. vbmeta_system_b {
  3554. pname = "vbmeta_system_b";
  3555. size = <0x0 0x200000>;
  3556. mask = <0x1>;
  3557. phandle = <0x7d>;
  3558. };
  3559.  
  3560. param {
  3561. pname = "param";
  3562. size = <0x0 0x1000000>;
  3563. mask = <0x2>;
  3564. phandle = <0x71>;
  3565. };
  3566.  
  3567. odm_ext_a {
  3568. pname = "odm_ext_a";
  3569. size = <0x0 0x1000000>;
  3570. mask = <0x1>;
  3571. phandle = <0x72>;
  3572. };
  3573.  
  3574. odm_ext_b {
  3575. pname = "odm_ext_b";
  3576. size = <0x0 0x1000000>;
  3577. mask = <0x1>;
  3578. phandle = <0x73>;
  3579. };
  3580.  
  3581. oem_a {
  3582. pname = "oem_a";
  3583. size = <0x0 0x2000000>;
  3584. mask = <0x1>;
  3585. phandle = <0x74>;
  3586. };
  3587.  
  3588. oem_b {
  3589. pname = "oem_b";
  3590. size = <0x0 0x2000000>;
  3591. mask = <0x1>;
  3592. phandle = <0x75>;
  3593. };
  3594.  
  3595. boot_a {
  3596. pname = "boot_a";
  3597. size = <0x0 0x4000000>;
  3598. mask = <0x1>;
  3599. phandle = <0x76>;
  3600. };
  3601.  
  3602. boot_b {
  3603. pname = "boot_b";
  3604. size = <0x0 0x4000000>;
  3605. mask = <0x1>;
  3606. phandle = <0x77>;
  3607. };
  3608.  
  3609. super {
  3610. pname = "super";
  3611. size = <0x0 0x70800000>;
  3612. mask = <0x1>;
  3613. phandle = <0x7e>;
  3614. };
  3615.  
  3616. userdata {
  3617. pname = "userdata";
  3618. size = <0xffffffff 0xffffffff>;
  3619. mask = <0x4>;
  3620. phandle = <0x7f>;
  3621. };
  3622. };
  3623.  
  3624. aliases {
  3625. serial0 = "/soc/apb4@fe000000/serial@7a000";
  3626. serial1 = "/soc/serial@fe078000";
  3627. serial2 = "/soc/serial@fe07c000";
  3628. serial3 = "/soc/serial@fe07e000";
  3629. serial4 = "/soc/serial@fe080000";
  3630. i2c0 = "/soc/apb4@fe000000/i2c@66000";
  3631. i2c1 = "/soc/apb4@fe000000/i2c@68000";
  3632. i2c2 = "/soc/apb4@fe000000/i2c@6a000";
  3633. i2c3 = "/soc/apb4@fe000000/i2c@6c000";
  3634. i2c4 = "/soc/apb4@fe000000/i2c@6e000";
  3635. spi0 = "/soc/apb4@fe000000/spi@56000";
  3636. spi1 = "/soc/apb4@fe000000/spi@50000";
  3637. tsensor0 = "/p_tsensor@fe020000";
  3638. };
  3639.  
  3640. memory@00000000 {
  3641. device_type = "memory";
  3642. linux,usable-memory = <0x0 0x0 0x0 0x80000000>;
  3643. };
  3644.  
  3645. reserved-memory {
  3646. #address-cells = <0x2>;
  3647. #size-cells = <0x2>;
  3648. ranges;
  3649.  
  3650. ramoops@0x07400000 {
  3651. compatible = "ramoops";
  3652. reg = <0x0 0x7400000 0x0 0x100000>;
  3653. record-size = <0x20000>;
  3654. console-size = <0x40000>;
  3655. ftrace-size = <0x80000>;
  3656. pmsg-size = <0x20000>;
  3657. };
  3658.  
  3659. linux,secmon {
  3660. compatible = "shared-dma-pool";
  3661. reusable;
  3662. size = <0x0 0x3400000>;
  3663. alignment = <0x0 0x400000>;
  3664. alloc-ranges = <0x0 0x5000000 0x0 0x3400000>;
  3665. phandle = <0x15>;
  3666. };
  3667.  
  3668. linux,meson-fb {
  3669. compatible = "shared-dma-pool";
  3670. reusable;
  3671. size = <0x0 0x800000>;
  3672. alignment = <0x0 0x400000>;
  3673. alloc-ranges = <0x0 0x3f800000 0x0 0x800000>;
  3674. phandle = <0x4e>;
  3675. };
  3676.  
  3677. linux,ion-dev {
  3678. compatible = "shared-dma-pool";
  3679. reusable;
  3680. size = <0x0 0x2400000>;
  3681. alignment = <0x0 0x400000>;
  3682. phandle = <0x4d>;
  3683. };
  3684.  
  3685. linux,di_cma {
  3686. compatible = "shared-dma-pool";
  3687. reusable;
  3688. alignment = <0x0 0x400000>;
  3689. };
  3690.  
  3691. linux,ppmgr {
  3692. compatible = "shared-dma-pool";
  3693. size = <0x0>;
  3694. phandle = <0x85>;
  3695. };
  3696.  
  3697. linux,codec_mm_cma {
  3698. compatible = "shared-dma-pool";
  3699. reusable;
  3700. size = <0x0 0xd000000>;
  3701. alignment = <0x0 0x400000>;
  3702. linux,contiguous-region;
  3703. phandle = <0x80>;
  3704. };
  3705.  
  3706. linux,codec_mm_reserved {
  3707. compatible = "amlogic, codec-mm-reserved";
  3708. size = <0x0 0x0>;
  3709. alignment = <0x0 0x100000>;
  3710. phandle = <0x81>;
  3711. };
  3712.  
  3713. linux,vdin1_cma {
  3714. compatible = "shared-dma-pool";
  3715. reusable;
  3716. size = <0x0 0x1400000>;
  3717. alignment = <0x0 0x400000>;
  3718. phandle = <0x4f>;
  3719. };
  3720. };
  3721.  
  3722. codec_mm {
  3723. compatible = "amlogic, codec, mm";
  3724. memory-region = <0x80 0x81>;
  3725. dev_name = "codec_mm";
  3726. status = "okay";
  3727. };
  3728.  
  3729. amdolby_vision {
  3730. compatible = "amlogic, dolby_vision_sc2";
  3731. dev_name = "aml_amdolby_vision_driver";
  3732. status = "disabled";
  3733. tv_mode = <0x0>;
  3734. };
  3735.  
  3736. cvbsout {
  3737. compatible = "amlogic, cvbsout-s4";
  3738. status = "disabled";
  3739. clk_path = <0x0>;
  3740. performance = <0x1bf0 0x9 0x1b56 0x333 0x1b12 0x8080 0x1b05 0xfd 0x1c59 0xf850 0xffff 0x0>;
  3741. performance_sarft = <0x1bf0 0x9 0x1b56 0x333 0x1b12 0x0 0x1b05 0x9 0x1c59 0xfc48 0xffff 0x0>;
  3742. performance_revB_telecom = <0x1bf0 0x9 0x1b56 0x546 0x1b12 0x8080 0x1b05 0x9 0x1c59 0xf850 0xffff 0x0>;
  3743. };
  3744.  
  3745. dvb-extern {
  3746. compatible = "amlogic, dvb-extern";
  3747. dev_name = "dvb-extern";
  3748. status = "disabled";
  3749. dvb_power_gpio = <0x1d 0x49 0x0>;
  3750. dvb_power_value = <0x1>;
  3751. dvb_power_dir = <0x0>;
  3752. fe_num = <0x3>;
  3753. fe0_demod = "internal";
  3754. fe0_tuner0 = <0x0>;
  3755. fe1_demod = "internal";
  3756. fe1_tuner0 = <0x1>;
  3757. fe2_demod = "cxd2856";
  3758. fe2_i2c_adap_id = <0x82>;
  3759. fe2_demod_i2c_addr = <0xd8>;
  3760. fe2_reset_value = <0x0>;
  3761. fe2_reset_gpio = <0x1d 0x48 0x0>;
  3762. fe2_reset_dir = <0x0>;
  3763. fe2_ant_poweron_value = <0x0>;
  3764. fe2_ts = <0x0>;
  3765. fe2_tuner1 = <0x3>;
  3766. tuner_num = <0x4>;
  3767. tuner0_name = "r836_tuner";
  3768. tuner0_i2c_adap = <0x83>;
  3769. tuner0_i2c_addr = <0x1a>;
  3770. tuner0_xtal = <0x0>;
  3771. tuner0_xtal_mode = <0x0>;
  3772. tuner0_xtal_cap = <0x10>;
  3773. tuner0_lt_out = <0x1>;
  3774. tuner1_name = "r836_tuner";
  3775. tuner1_i2c_adap = <0x83>;
  3776. tuner1_i2c_addr = <0x3a>;
  3777. tuner1_xtal = <0x0>;
  3778. tuner1_xtal_mode = <0x0>;
  3779. tuner1_xtal_cap = <0x10>;
  3780. tuner1_lt_out = <0x1>;
  3781. tuner2_name = "av2018_tuner";
  3782. tuner2_i2c_adap = <0x83>;
  3783. tuner2_i2c_addr = <0xc4>;
  3784. tuner2_lt_out = <0x1>;
  3785. tuner3_name = "av2018_tuner";
  3786. tuner3_lt_out = <0x1>;
  3787. };
  3788.  
  3789. dvb-demux {
  3790. compatible = "amlogic sc2, dvb-demux";
  3791. dev_name = "dvb-demux";
  3792. status = "disabled";
  3793. reg = <0x0 0xfe000000 0x0 0x480000>;
  3794. dmxdev_num = <0x4>;
  3795. tsn_from = "demod";
  3796. ts0_sid = <0x20>;
  3797. ts0 = "serial-4wire";
  3798. ts0_control = <0x0>;
  3799. ts0_invert = <0x0>;
  3800. ts1_sid = <0x21>;
  3801. ts1 = "parallel";
  3802. ts1_control = <0x0>;
  3803. ts1_invert = <0x0>;
  3804. ts2_sid = <0x22>;
  3805. ts2 = "parallel";
  3806. ts2_control = <0x0>;
  3807. ts2_invert = <0x0>;
  3808. pinctrl-names = "s_ts0";
  3809. pinctrl-0 = <0x84>;
  3810. };
  3811.  
  3812. fd655_dev {
  3813. compatible = "amlogic, fd655_dev";
  3814. dev_name = "fd655_dev";
  3815. status = "okay";
  3816. clk_pin = <0x1d 0x2d 0x1>;
  3817. dat_pin = <0x1d 0x2c 0x1>;
  3818. };
  3819.  
  3820. ionvideo {
  3821. compatible = "amlogic, ionvideo";
  3822. dev_name = "ionvideo";
  3823. status = "okay";
  3824. };
  3825.  
  3826. amlvideo2_0 {
  3827. compatible = "amlogic, amlvideo2";
  3828. dev_name = "amlvideo2";
  3829. status = "okay";
  3830. amlvideo2_id = <0x0>;
  3831. cma_mode = <0x1>;
  3832. };
  3833.  
  3834. amlvideo2_1 {
  3835. compatible = "amlogic, amlvideo2";
  3836. dev_name = "amlvideo2";
  3837. status = "okay";
  3838. amlvideo2_id = <0x1>;
  3839. cma_mode = <0x1>;
  3840. };
  3841.  
  3842. ppmgr {
  3843. compatible = "amlogic, ppmgr";
  3844. memory-region = <0x85>;
  3845. dev_name = "ppmgr";
  3846. status = "okay";
  3847. };
  3848.  
  3849. amlvecm {
  3850. compatible = "amlogic, vecm";
  3851. dev_name = "aml_vecm";
  3852. status = "okay";
  3853. gamma_en = <0x0>;
  3854. wb_en = <0x0>;
  3855. cm_en = <0x0>;
  3856. tx_op_color_primary = <0x0>;
  3857. };
  3858.  
  3859. multi-di {
  3860. compatible = "amlogic, dim-s4";
  3861. status = "okay";
  3862. flag_cma = <0x4>;
  3863. interrupts = <0x0 0xcb 0x1 0x0 0xca 0x1>;
  3864. interrupt-names = "pre_irq", "post_irq";
  3865. clocks = <0xd 0xc2 0xd 0xbd>;
  3866. clock-names = "vpu_clkb", "vpu_mux";
  3867. clock-range = <0x14e 0x29b>;
  3868. buffer-size = <0x3e2c40>;
  3869. post-wr-support = <0x1>;
  3870. nr10bit-support = <0x1>;
  3871. nrds-enable = <0x1>;
  3872. pps-enable = <0x1>;
  3873. };
  3874.  
  3875. provisionkey {
  3876. compatible = "amlogic, provisionkey";
  3877. status = "disabled";
  3878. key-permit-default = "write";
  3879.  
  3880. KEY_PROVISION_XXX {
  3881. };
  3882. };
  3883.  
  3884. unifykey {
  3885. compatible = "amlogic,unifykey";
  3886. status = "ok";
  3887. unifykey-num = <0x13>;
  3888. unifykey-index-0 = <0x86>;
  3889. unifykey-index-1 = <0x87>;
  3890. unifykey-index-2 = <0x88>;
  3891. unifykey-index-3 = <0x89>;
  3892. unifykey-index-4 = <0x8a>;
  3893. unifykey-index-5 = <0x8b>;
  3894. unifykey-index-6 = <0x8c>;
  3895. unifykey-index-7 = <0x8d>;
  3896. unifykey-index-8 = <0x8e>;
  3897. unifykey-index-9 = <0x8f>;
  3898. unifykey-index-10 = <0x90>;
  3899. unifykey-index-11 = <0x91>;
  3900. unifykey-index-12 = <0x92>;
  3901. unifykey-index-13 = <0x93>;
  3902. unifykey-index-14 = <0x94>;
  3903. unifykey-index-15 = <0x95>;
  3904. unifykey-index-16 = <0x96>;
  3905. unifykey-index-17 = <0x97>;
  3906. unifykey-index-18 = <0x98>;
  3907.  
  3908. key_0 {
  3909. key-name = "usid";
  3910. key-device = "normal";
  3911. key-permit = "read", "write", "del";
  3912. phandle = <0x86>;
  3913. };
  3914.  
  3915. key_1 {
  3916. key-name = "mac";
  3917. key-device = "normal";
  3918. key-permit = "read", "write", "del";
  3919. phandle = <0x87>;
  3920. };
  3921.  
  3922. key_2 {
  3923. key-name = "hdcp";
  3924. key-device = "secure";
  3925. key-type = "sha1";
  3926. key-permit = "read", "write", "del";
  3927. phandle = <0x88>;
  3928. };
  3929.  
  3930. key_3 {
  3931. key-name = "secure_boot_set";
  3932. key-device = "efuse";
  3933. key-permit = "write";
  3934. phandle = <0x89>;
  3935. };
  3936.  
  3937. key_4 {
  3938. key-name = "mac_bt";
  3939. key-device = "normal";
  3940. key-permit = "read", "write", "del";
  3941. key-type = "mac";
  3942. phandle = <0x8a>;
  3943. };
  3944.  
  3945. key_5 {
  3946. key-name = "mac_wifi";
  3947. key-device = "normal";
  3948. key-permit = "read", "write", "del";
  3949. key-type = "mac";
  3950. phandle = <0x8b>;
  3951. };
  3952.  
  3953. key_6 {
  3954. key-name = "hdcp2_tx";
  3955. key-device = "normal";
  3956. key-permit = "read", "write", "del";
  3957. phandle = <0x8c>;
  3958. };
  3959.  
  3960. key_7 {
  3961. key-name = "hdcp2_rx";
  3962. key-device = "normal";
  3963. key-permit = "read", "write", "del";
  3964. phandle = <0x8d>;
  3965. };
  3966.  
  3967. key_8 {
  3968. key-name = "widevinekeybox";
  3969. key-device = "secure";
  3970. key-permit = "read", "write", "del";
  3971. phandle = <0x8e>;
  3972. };
  3973.  
  3974. key_9 {
  3975. key-name = "deviceid";
  3976. key-device = "normal";
  3977. key-permit = "read", "write", "del";
  3978. phandle = <0x8f>;
  3979. };
  3980.  
  3981. key_10 {
  3982. key-name = "hdcp22_fw_private";
  3983. key-device = "secure";
  3984. key-permit = "read", "write", "del";
  3985. phandle = <0x90>;
  3986. };
  3987.  
  3988. key_11 {
  3989. key-name = "PlayReadykeybox25";
  3990. key-device = "secure";
  3991. key-permit = "read", "write", "del";
  3992. phandle = <0x91>;
  3993. };
  3994.  
  3995. key_12 {
  3996. key-name = "prpubkeybox";
  3997. key-device = "secure";
  3998. key-permit = "read", "write", "del";
  3999. phandle = <0x92>;
  4000. };
  4001.  
  4002. key_13 {
  4003. key-name = "prprivkeybox";
  4004. key-device = "secure";
  4005. key-permit = "read", "write", "del";
  4006. phandle = <0x93>;
  4007. };
  4008.  
  4009. key_14 {
  4010. key-name = "attestationkeybox";
  4011. key-device = "secure";
  4012. key-permit = "read", "write", "del";
  4013. phandle = <0x94>;
  4014. };
  4015.  
  4016. key_15 {
  4017. key-name = "region_code";
  4018. key-device = "normal";
  4019. key-permit = "read", "write", "del";
  4020. phandle = <0x95>;
  4021. };
  4022.  
  4023. key_16 {
  4024. key-name = "netflix_mgkid";
  4025. key-device = "secure";
  4026. key-permit = "read", "write", "del";
  4027. phandle = <0x96>;
  4028. };
  4029.  
  4030. key_17 {
  4031. key-name = "attestationdevidbox";
  4032. key-device = "secure";
  4033. key-permit = "read", "write", "del";
  4034. phandle = <0x97>;
  4035. };
  4036.  
  4037. key_18 {
  4038. key-name = "oemkey";
  4039. key-device = "normal";
  4040. key-permit = "read", "write", "del";
  4041. phandle = <0x98>;
  4042. };
  4043. };
  4044.  
  4045. auge_sound {
  4046. compatible = "amlogic, auge-sound-card";
  4047. aml-audio-card,name = "AML-AUGESOUND";
  4048. avout_mute-gpios = <0x1d 0x29 0x0>;
  4049.  
  4050. aml-audio-card,dai-link@0 {
  4051. format = "dsp_a";
  4052. mclk-fs = <0x200>;
  4053. bitclock-master = <0x99>;
  4054. frame-master = <0x99>;
  4055. suffix-name = "alsaPORT-pcm";
  4056.  
  4057. cpu {
  4058. sound-dai = <0x99>;
  4059. dai-tdm-slot-tx-mask = <0x1>;
  4060. dai-tdm-slot-rx-mask = <0x1>;
  4061. dai-tdm-slot-num = <0x2>;
  4062. dai-tdm-slot-width = <0x10>;
  4063. system-clock-frequency = <0x3e800>;
  4064. };
  4065.  
  4066. codec {
  4067. sound-dai = <0x9a>;
  4068. };
  4069. };
  4070.  
  4071. aml-audio-card,dai-link@1 {
  4072. format = "i2s";
  4073. mclk-fs = <0x100>;
  4074. bitclock-master = <0x9b>;
  4075. frame-master = <0x9b>;
  4076. suffix-name = "alsaPORT-i2s2hdmi";
  4077.  
  4078. cpu {
  4079. sound-dai = <0x9b>;
  4080. dai-tdm-slot-tx-mask = <0x1 0x1>;
  4081. dai-tdm-slot-rx-mask = <0x1 0x1>;
  4082. dai-tdm-slot-num = <0x2>;
  4083. dai-tdm-slot-width = <0x20>;
  4084. system-clock-frequency = <0xbb8000>;
  4085. };
  4086.  
  4087. codec {
  4088. sound-dai = <0x9a>;
  4089. };
  4090. };
  4091.  
  4092. aml-audio-card,dai-link@2 {
  4093. format = "i2s";
  4094. mclk-fs = <0x100>;
  4095. bitclock-master = <0x9c>;
  4096. frame-master = <0x9c>;
  4097. suffix-name = "alsaPORT-i2s";
  4098.  
  4099. cpu {
  4100. sound-dai = <0x9c>;
  4101. dai-tdm-slot-tx-mask = <0x1 0x1>;
  4102. dai-tdm-slot-rx-mask = <0x1 0x1>;
  4103. dai-tdm-slot-num = <0x2>;
  4104. dai-tdm-slot-width = <0x20>;
  4105. system-clock-frequency = <0xbb8000>;
  4106. };
  4107.  
  4108. codec {
  4109. sound-dai = <0x9d>;
  4110. };
  4111. };
  4112.  
  4113. aml-audio-card,dai-link@3 {
  4114. mclk-fs = <0x40>;
  4115. suffix-name = "alsaPORT-pdm-builtinmic";
  4116.  
  4117. cpu {
  4118. sound-dai = <0x9e>;
  4119. };
  4120.  
  4121. codec {
  4122. sound-dai = <0x9a>;
  4123. };
  4124. };
  4125.  
  4126. aml-audio-card,dai-link@4 {
  4127. mclk-fs = <0x80>;
  4128. suffix-name = "alsaPORT-spdif";
  4129.  
  4130. cpu {
  4131. sound-dai = <0x9f>;
  4132. system-clock-frequency = <0x5dc000>;
  4133. };
  4134.  
  4135. codec {
  4136. sound-dai = <0x9a>;
  4137. };
  4138. };
  4139.  
  4140. aml-audio-card,dai-link@5 {
  4141. mclk-fs = <0x80>;
  4142. continuous-clock;
  4143. suffix-name = "alsaPORT-spdifb";
  4144.  
  4145. cpu {
  4146. sound-dai = <0xa0>;
  4147. system-clock-frequency = <0x5dc000>;
  4148. };
  4149.  
  4150. codec {
  4151. sound-dai = <0x9a>;
  4152. };
  4153. };
  4154.  
  4155. aml-audio-card,dai-link@6 {
  4156. mclk-fs = <0x100>;
  4157. continuous-clock;
  4158. suffix-name = "alsaPORT-loopback";
  4159.  
  4160. cpu {
  4161. sound-dai = <0xa1>;
  4162. system-clock-frequency = <0xbb8000>;
  4163. };
  4164.  
  4165. codec {
  4166. sound-dai = <0x9a>;
  4167. };
  4168. };
  4169. };
  4170.  
  4171. picdec {
  4172. compatible = "amlogic, picdec";
  4173. status = "okay";
  4174. };
  4175.  
  4176. locker {
  4177. compatible = "amlogic, audiolocker";
  4178. clock-names = "lock_out", "lock_in", "out_src", "in_src", "out_calc", "in_ref";
  4179. interrupts = <0x0 0x1 0x1>;
  4180. interrupt-names = "irq";
  4181. frequency = <0x2ebae40>;
  4182. dividor = <0x31>;
  4183. status = "disabled";
  4184. };
  4185.  
  4186. adc_keypad {
  4187. compatible = "amlogic, adc_keypad";
  4188. status = "okay";
  4189. key_name = "standby", "vol+", "vol-";
  4190. key_num = <0x3>;
  4191. io-channels = <0xa2 0x0>;
  4192. io-channel-names = "key-chan-0";
  4193. key_chan = <0x0 0x0 0x0>;
  4194. key_code = <0x74 0x73 0x72>;
  4195. key_val = <0x14 0x38e 0x276>;
  4196. key_tolerance = <0x28 0x28 0x28>;
  4197. };
  4198.  
  4199. gpio_keypad {
  4200. compatible = "amlogic, gpio_keypad";
  4201. status = "okay";
  4202. scan_period = <0x14>;
  4203. key_num = <0x1>;
  4204. key_name = "bluetooth";
  4205. key_code = <0x258>;
  4206. key-gpios = <0x1d 0x1a 0x0>;
  4207. detect_mode = <0x0>;
  4208. };
  4209. };
  4210.  
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