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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Dept. of Computer Science, National Chiao Tung University
  4. // Engineer: Chun-Jen Tsai
  5. //
  6. // Create Date: 2017/05/08 15:29:41
  7. // Design Name:
  8. // Module Name: lab6
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description: The sample top module of lab 6: sd card reader. The behavior of
  13. // this module is as follows
  14. // 1. When the SD card is initialized, display a message on the LCD.
  15. // If the initialization fails, an error message will be shown.
  16. // 2. The user can then press usr_btn[2] to trigger the sd card
  17. // controller to read the super block of the sd card (located at
  18. // block # 8192) into the SRAM memory.
  19. // 3. During SD card reading time, the four LED lights will be turned on.
  20. // They will be turned off when the reading is done.
  21. // 4. The LCD will then displayer the sector just been read, and the
  22. // first byte of the sector.
  23. // 5. Everytime you press usr_btn[2], the next byte will be displayed.
  24. //
  25. // Dependencies: clk_divider, LCD_module, debounce, sd_card
  26. //
  27. // Revision:
  28. // Revision 0.01 - File Created
  29. // Additional Comments:
  30. //
  31. //////////////////////////////////////////////////////////////////////////////////
  32.  
  33. module lab7(
  34. // General system I/O ports
  35. input clk,
  36. input reset_n,
  37. input [3:0] usr_btn,
  38. output [3:0] usr_led,
  39.  
  40. // SD card specific I/O ports
  41. output spi_ss,
  42. output spi_sck,
  43. output spi_mosi,
  44. input spi_miso,
  45.  
  46. // 1602 LCD Module Interface
  47. output LCD_RS,
  48. output LCD_RW,
  49. output LCD_E,
  50. output [3:0] LCD_D
  51. );
  52.  
  53. localparam [3:0] S_MAIN_INIT = 4'b0000, S_MAIN_IDLE = 4'b0001,
  54. S_MAIN_WAIT = 4'b0010, S_MAIN_READ = 4'b0011,
  55. S_MAIN_DONE = 4'b0100, S_MAIN_FIND = 4'b0101,
  56. S_MAIN_CAL = 4'b0110, S_MAIN_SHOW = 4'b0111;
  57.  
  58. // Declare system variables
  59. wire btn_level, btn_pressed;
  60. reg prev_btn_level;
  61. reg [5:0] send_counter;
  62. reg [2:0] P, P_next;
  63. reg [9:0] sd_counter;
  64. reg [9:0] counter=0;
  65. reg [9:0] start_counter;
  66. reg [7:0] data_byte;
  67. reg [31:0] blk_addr;
  68. reg [31:0] start_blk_addr;
  69. reg [3:0] dlab_tag_match=0;
  70. reg start_flag=0;
  71. reg not_this_block;
  72. reg [127:0] row_A = "SD card cannot ";
  73. reg [127:0] row_B = "be initialized! ";
  74. reg [0:63] dlab_tag = "MATX_TAG";
  75. reg [0:56] print_out = " ";
  76. reg done_flag; // Signals the completion of reading one SD sector.
  77. reg [0:7] word="@", word_1="@", word_2='h1 ,word_3 = "!",word_4='h2, word_5, word_6, word_7;
  78. reg [0:31] p_addr, p_addr_1;
  79. reg flag=0;
  80. // Declare SD card interface signals
  81. wire clk_sel;
  82. wire clk_500k;
  83. reg rd_req;
  84. reg [31:0] rd_addr;
  85. wire init_finished;
  86. wire [7:0] sd_dout;
  87. wire sd_valid;
  88. reg read_fin=0, cal_fin=0;
  89. // Declare the control/data signals of an SRAM memory block
  90. wire [7:0] data_in;
  91. wire [7:0] data_out;
  92. wire [8:0] sram_addr;
  93. wire sram_we, sram_en;
  94.  
  95. assign clk_sel = (init_finished)? clk : clk_500k; // clock for the SD controller
  96. assign usr_led = P;
  97.  
  98. // for matrix
  99. reg [0:255] A_mat, B_mat;
  100. reg [7:0] A_save_count, B_save_count;
  101. clk_divider#(200) clk_divider0(
  102. .clk(clk),
  103. .reset(~reset_n),
  104. .clk_out(clk_500k)
  105. );
  106.  
  107. debounce btn_db0(
  108. .clk(clk),
  109. .btn_input(usr_btn[2]),
  110. .btn_output(btn_level)
  111. );
  112.  
  113. LCD_module lcd0(
  114. .clk(clk),
  115. .reset(~reset_n),
  116. .row_A(row_A),
  117. .row_B(row_B),
  118. .LCD_E(LCD_E),
  119. .LCD_RS(LCD_RS),
  120. .LCD_RW(LCD_RW),
  121. .LCD_D(LCD_D)
  122. );
  123.  
  124. sd_card sd_card0(
  125. .cs(spi_ss),
  126. .sclk(spi_sck),
  127. .mosi(spi_mosi),
  128. .miso(spi_miso),
  129.  
  130. .clk(clk_sel),
  131. .rst(~reset_n),
  132. .rd_req(rd_req),
  133. .block_addr(rd_addr),
  134. .init_finished(init_finished),
  135. .dout(sd_dout),
  136. .sd_valid(sd_valid)
  137. );
  138.  
  139. sram ram0(
  140. .clk(clk),
  141. .we(sram_we),
  142. .en(sram_en),
  143. .addr(sram_addr),
  144. .data_i(data_in),
  145. .data_o(data_out)
  146. );
  147.  
  148.  
  149. //
  150. // Enable one cycle of btn_pressed per each button hit
  151. //
  152. always @(posedge clk) begin
  153. if (~reset_n)
  154. prev_btn_level <= 0;
  155. else
  156. prev_btn_level <= btn_level;
  157. end
  158.  
  159. assign btn_pressed = (btn_level == 1 && prev_btn_level == 0)? 1 : 0;
  160.  
  161. // ------------------------------------------------------------------------
  162. // The following code sets the control signals of an SRAM memory block
  163. // that is connected to the data output port of the SD controller.
  164. // Once the read request is made to the SD controller, 512 bytes of data
  165. // will be sequentially read into the SRAM memory block, one byte per
  166. // clock cycle (as long as the sd_valid signal is high).
  167. assign sram_we = sd_valid; // Write data into SRAM when sd_valid is high.
  168. assign sram_en = 1; // Always enable the SRAM block.
  169. assign data_in = sd_dout; // Input data always comes from the SD controller.
  170. assign sram_addr = sd_counter[8:0]; // Set the driver of the SRAM address signal.
  171. // End of the SRAM memory block
  172. // ------------------------------------------------------------------------
  173.  
  174. // ------------------------------------------------------------------------
  175. // FSM of the SD card reader that reads the super block (512 bytes)
  176. always @(posedge clk) begin
  177. if (~reset_n) begin
  178. P <= S_MAIN_INIT;
  179. done_flag <= 0;
  180. end
  181. else begin
  182. P <= P_next;
  183. if (P == S_MAIN_DONE)
  184. done_flag <= 1;
  185. else if (P == S_MAIN_SHOW && P_next == S_MAIN_IDLE)
  186. done_flag <= 0;
  187. else
  188. done_flag <= done_flag;
  189. end
  190. end
  191.  
  192.  
  193.  
  194. always @(*) begin // FSM next-state logic
  195. case (P)
  196. S_MAIN_INIT: // wait for SD card initialization
  197. if (init_finished == 1) P_next = S_MAIN_IDLE;
  198. else P_next = S_MAIN_INIT;
  199. S_MAIN_IDLE: // wait for button click
  200. if (btn_pressed == 1) P_next = S_MAIN_WAIT;
  201. else P_next = S_MAIN_IDLE;
  202. S_MAIN_WAIT: // issue a rd_req to the SD controller until it's ready
  203. P_next = S_MAIN_READ;
  204. S_MAIN_READ: // wait for the input data to enter the SRAM buffer
  205. if (sd_counter == 512) P_next = S_MAIN_DONE;
  206. else P_next = S_MAIN_READ;
  207. S_MAIN_DONE: // read byte 0 of the superblock from sram[]
  208. P_next = S_MAIN_FIND;
  209. S_MAIN_FIND:
  210. if (read_fin == 1) P_next = S_MAIN_CAL;
  211. else if (sd_counter =='d512) P_next = S_MAIN_WAIT;
  212. else P_next = S_MAIN_FIND;
  213. S_MAIN_CAL:
  214. if (cal_fin == 1) P_next = S_MAIN_SHOW;
  215. else P_next = S_MAIN_CAL;
  216. S_MAIN_SHOW:
  217. if (~reset_n) P_next = S_MAIN_INIT;
  218. else P_next = S_MAIN_SHOW;
  219. default:
  220. P_next = S_MAIN_IDLE;
  221. endcase
  222. end
  223.  
  224. // FSM output logic: controls the 'rd_req' and 'rd_addr' signals.
  225. always @(*) begin
  226. rd_req = (P == S_MAIN_WAIT);
  227. rd_addr = blk_addr;
  228. end
  229.  
  230. always @(posedge clk) begin
  231. if (~reset_n) begin
  232. counter <= 0;
  233. blk_addr <= 32'h2000;
  234. dlab_tag_match <=0;
  235. start_flag <= 0;
  236. flag <= 0;
  237. A_save_count <= 0;
  238. B_save_count <= 0;
  239. read_fin <= 0;
  240. end
  241. if (P==S_MAIN_WAIT) begin
  242. not_this_block <= 0;
  243. end
  244.  
  245. if (P==S_MAIN_FIND) begin
  246. if(data_byte==dlab_tag[counter+:8]) begin
  247. dlab_tag_match = dlab_tag_match + 1;
  248. counter <= counter + 8;
  249. not_this_block <= 0;
  250. // if (dlab_tag_match == 'd1) word <= data_byte;
  251. // if (dlab_tag_match == 'd2) word_1 <= data_byte;
  252. // if (dlab_tag_match == 'd3) word_2 <= data_byte;
  253. // if (dlab_tag_match == 'd4) word_3 <= data_byte;
  254. // if (dlab_tag_match == 'd5) word_4 <= data_byte;
  255. // if (dlab_tag_match == 'd6) word_5 <= data_byte;
  256. // if (dlab_tag_match == 'd7) word_6 <= data_byte;
  257. if (dlab_tag_match == 'd8) begin
  258. start_flag <= 1;
  259. dlab_tag_match = dlab_tag_match+1;
  260. //word_7 <= data_byte;
  261. p_addr_1[0+:8]<=blk_addr[15:12];
  262. p_addr_1[8+:8]<=blk_addr[11:8];
  263. p_addr_1[16+:8]<=blk_addr[7:4];
  264. p_addr_1[24+:8]<=blk_addr[3:0];
  265. end
  266.  
  267. end
  268. else begin
  269. dlab_tag_match <= 0;
  270. counter <= 0;
  271. end
  272. if (start_flag == 1) begin
  273. if ((A_save_count < 'd255) && (((data_byte >= "0") && (data_byte <= "9")) || ((data_byte >= "A") && (data_byte <= "E")))) begin
  274. A_mat[A_save_count+:8] <= data_byte;
  275. if (A_save_count==0) word <= "*";
  276. if (A_save_count==8) word_1 <= "!";
  277. if (A_save_count==16) word_2 <= "@";
  278. if (A_save_count==24) word_3 <= "&";
  279. A_save_count <= A_save_count + 'd8;
  280. end
  281. else if (B_save_count < 'd255 && ((data_byte >= "0" && data_byte <= "9") || (data_byte >= "A" && data_byte <= "E"))) begin
  282. B_mat[B_save_count+:8] <= data_byte;
  283. if (B_save_count==0) word_4 <= "o";
  284. if (B_save_count==8) word_5 <= "y";
  285. if (B_save_count==16) word_6 <= "t";
  286. if (B_save_count==24) word_7 <= "r";
  287. B_save_count <= B_save_count + 'd8;
  288.  
  289. end
  290. if(B_save_count >='d255) read_fin <= 1;
  291. end
  292.  
  293. end
  294. if (P == S_MAIN_FIND && sd_counter == 'd512) blk_addr <= blk_addr+1;
  295. end
  296.  
  297.  
  298. always @(posedge clk) begin
  299. if (~reset_n || (P == S_MAIN_READ && P_next == S_MAIN_DONE) || ((P == S_MAIN_DONE) && (P_next == S_MAIN_WAIT)) || ((P == S_MAIN_FIND) && (P_next == S_MAIN_WAIT)) || ((P == S_MAIN_DONE) && (P_next == S_MAIN_FIND)))
  300. sd_counter <= 0;
  301. else if ((P == S_MAIN_READ && sd_valid) ||(P == S_MAIN_DONE && P_next==S_MAIN_FIND) || (P==S_MAIN_DONE && sd_counter<512) || (P==S_MAIN_FIND && sd_counter<512) ||((P == S_MAIN_CAL) && (P_next==S_MAIN_SHOW)))
  302. sd_counter <= sd_counter + 1;
  303.  
  304. end
  305.  
  306.  
  307.  
  308. // FSM ouput logic: Retrieves the content of sram[] for display
  309. always @(posedge clk) begin
  310. if (~reset_n) data_byte <= 8'b0;
  311. else if (sram_en && (P == S_MAIN_DONE || P == S_MAIN_FIND )) data_byte <= data_out;
  312. //else data_byte <= data_out;
  313. end
  314. // End of the FSM of the SD card reader
  315. // ------------------------------------------------------------------------
  316.  
  317. // ------------------------------------------------------------------------
  318. // LCD Display function.
  319. always @(posedge clk) begin
  320. if (~reset_n) begin
  321. row_A = "SD card cannot ";
  322. row_B = "be initialized! ";
  323. end
  324. else if (done_flag) begin
  325. row_A <= {word, word_1, word_2, word_3, word_4, word_5, word_6, word_7, ((p_addr_1[0:7] > 9)? "7" : "0") + p_addr_1[0:7], ((p_addr_1[8:15] > 9)? "7" : "0") + p_addr_1[8:15], ((p_addr_1[16:23] > 9)? "7" : "0") + p_addr_1[16:23], ((p_addr_1[24:31] > 9)? "7" : "0") + p_addr_1[24:31]};
  326. //row_A <= {word, word_1};
  327. // row_B <= { "Byte ",
  328. // sd_counter[9:8] + "0",
  329. // ((sd_counter[7:4] > 9)? "7" : "0") + sd_counter[7:4],
  330. // ((sd_counter[3:0] > 9)? "7" : "0") + sd_counter[3:0],
  331. // "h = ",
  332. // ((data_byte[7:4] > 9)? "7" : "0") + data_byte[7:4],
  333. // ((data_byte[3:0] > 9)? "7" : "0") + data_byte[3:0], "h." };
  334. //row_A <= A_mat[0:127];
  335. row_B <= B_mat[0:127];
  336. end
  337. else if (P == S_MAIN_IDLE) begin
  338. row_A <= "Hit BTN2 to read";
  339. row_B <= "the SD card ... ";
  340. end
  341.  
  342. end
  343. // End of the LCD display function
  344. // ------------------------------------------------------------------------
  345.  
  346.  
  347.  
  348.  
  349. endmodule
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