entity reg8b is
port ( 	LD,CLK,CLR : in std_logic;
			  D_IN : in std_logic_vector (7 downto 0);
			 D_OUT : out std_logic_vector (7 downto 0));
end reg8b;


architecture Behavioral of reg8b is
begin
	process (CLK,LD)
		begin
			if (LD = '1' and rising_edge(CLK)) then
				D_OUT <= D_IN;
			end if;
	end process;
end Behavioral;