config PLLDIV = 1 ; (4 MHz crystal )
config CPUDIV = OSC1_PLL2 ; No dividim. Treballem a 4MHz
config USBDIV = 2 ; Clock source from 96MHz PLL/2
config FOSC = HS ;sense PLL


ADCON1 EQU 0xFC1
PORTA EQU 0xF80
PORTB EQU 0xF81
PORTC EQU 0xF82
TRISA EQU 0xF92
TRISB EQU 0xF93
TRISC EQU 0xF94

org 0

MOVLW 0x0F
MOVWF ADCON1,0 ;I/O digitals
MOVLW 0xFF
MOVWF TRISA,0 ;PORTA IN
MOVLW 0x00
MOVWF TRISB,0 ;PORTB OUT

CLRF PORTB,0 ;PORTB = 0


loop	MOVLW 0x00
		CPFSEQ PORTA,0
		GOTO canviB
		GOTO loop

canviB	CPFSGT PORTB,0
		GOTO ledon
		GOTO ledoff

canviA	CPFSGT PORTA,0
		GOTO	loop
		GOTO 	canviA


ledon	SETF PORTB,0
		GOTO canviA


ledoff	CLRF PORTB,0
		GOTO canviA

END