UINT_MIN

ROSE-8 v0.2

Jan 13th, 2020
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  1. v0.2
  2.  
  3. Eight completely symmetric general-purpose registers (r0-7)
  4. Special registers: pc (16-bit address), it (accumulator), data1 (segment), data2 (segment), code (segment)
  5.  
  6. 7654_3210
  7.  
  8. 0000_0000 TRAP (invalid)
  9. 0001 NOPE "no operation" (with a more fun mnemonic)
  10. 0010 PRNT print it (for debugging or toy programs)
  11. 0011
  12. 010x
  13. 0110 CABA call absolute code[it], it <- return addr, code <- return segment
  14. 0111 COFA call offset pc ± it, it <- return offset (-it + 1)
  15.  
  16. 0000_1ooo ALU1 it <- {zero, lsl1, lsr1, asr1, incr, decr, comp, negt} it
  17.  
  18. 0001_0000 GET1 it <- data1
  19. 0001 GET2 it <- data2
  20. 0010 GETC it <- code
  21. 0011 (reserved for another special register)
  22. 01xx
  23. 1000 SET1 data1 <- it
  24. 1001 SET2 data2 <- it
  25. 1010 SETC code <- it
  26. 1011 (reserved for another special register)
  27. 11xx
  28.  
  29. 0010_0aaa GETR it <- it
  30. 0_1aaa SETR ra <- it
  31. 1_0aaa SWAP ra <- it, it <- ra
  32. 1_1aaa ISLT "is less than", for testing overflow / carries: it <- (it < ra) ? 1 : 0
  33.  
  34. 01oo_oaaa ALUR it <- it {addr, subr, andr, iorr, xorr, lslr, lsrr, asrr} ra
  35.  
  36. 100i_0aaa LD1U it <- data1[ra], then ra += i
  37. 0i_1aaa ST1U data1[ra] <- it, then ra += i
  38. 1i_0aaa LD2U it <- data2[ra], then ra += i
  39. 1i_1aaa ST2U data2[ra] <- it, then ra += i
  40.  
  41. 110x_xaaa (reserved w/ register)
  42. 1110_xaaa (reserved w/ register)
  43.  
  44. 1111_00oo iiiiiiii ALUI it <- it {andi, iori, xori, (see below)} i
  45. 0011 0iiiiiii ADDI it <- it + i
  46. 0011 10oooiii BITI it <- it {roli, lsli, lsri, asri, clri, insi, togi, exti} i
  47. 0011 11iiiiii ADDI it <- it + (whole field, thus allowing many negative numbers)
  48. 0100 iiiiiiii BEZI branch pc ± i if it == 0
  49. 0101 iiiiiiii JOFI jump offset to pc ± i
  50. 0110 iiiiiiii CABI call absolute code[i], it <- return addr, code <- return segment
  51. 0111 iiiiiiii COFI call offset pc ± i, it <- return offset (-i + 2)
  52. 10xx iiiiiiii (reserved w/ immediate)
  53. 110x iiiiiiii (reserved w/ immediate)
  54. 1110 iiiiiiii GETI it <- i
  55. 1111 xxxxxxxx EXT1 extended encoding for "future-proofing"
  56.  
  57. 11 free no-argument encodings
  58. 6 free register encodings - possibly load-then-decrement? possibly 16-bit ADD and SUB with register pairs?
  59. 6 free immediate encodings
  60.  
  61. Some dubiously "nice" properties:
  62. - 0 is invalid
  63. - 1111_xxxx takes immediate
  64. - Register instructions are all consecutive (0010_0aaa through 1110_1aaa)
  65. - No reg/imm ops, so data line can be the immediate
  66. - Two data segments, because I'm generous like that
  67. - get/set pairs consistently differentiated by bit 3
  68. - Future-proofing! Because that's definitely a thing that this set needs
  69. - The nicest instruction is "ADDR r5"
  70. - Near and far calls (okay, this is not nice)
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