ROSE-8 v0.2

v0.2

Eight completely symmetric general-purpose registers (r0-7)
Special registers: pc (16-bit address), it (accumulator), data1 (segment), data2 (segment), code (segment)

7654_3210

0000_0000          TRAP (invalid)
     0001          NOPE "no operation" (with a more fun mnemonic)
     0010          PRNT print it (for debugging or toy programs)
     0011
     010x
     0110          CABA call absolute code[it], it <- return addr, code <- return segment
     0111          COFA call offset pc ± it, it <- return offset (-it + 1)

0000_1ooo          ALU1 it <- {zero, lsl1, lsr1, asr1, incr, decr, comp, negt} it

0001_0000          GET1 it <- data1
     0001          GET2 it <- data2
     0010          GETC it <- code
     0011               (reserved for another special register)
     01xx
     1000          SET1 data1 <- it
     1001          SET2 data2 <- it
     1010          SETC code  <- it
     1011               (reserved for another special register)
     11xx

0010_0aaa          GETR it <- it
   0_1aaa          SETR ra <- it
   1_0aaa          SWAP ra <- it, it <- ra
   1_1aaa          ISLT "is less than", for testing overflow / carries: it <- (it < ra) ? 1 : 0

01oo_oaaa          ALUR it <- it {addr, subr, andr, iorr, xorr, lslr, lsrr, asrr} ra

100i_0aaa          LD1U it <- data1[ra], then ra += i
  0i_1aaa          ST1U data1[ra] <- it, then ra += i
  1i_0aaa          LD2U it <- data2[ra], then ra += i
  1i_1aaa          ST2U data2[ra] <- it, then ra += i

110x_xaaa               (reserved w/ register)
1110_xaaa               (reserved w/ register)

1111_00oo iiiiiiii ALUI it <- it {andi, iori, xori, (see below)} i
     0011 0iiiiiii ADDI it <- it + i
     0011 10oooiii BITI it <- it {roli, lsli, lsri, asri, clri, insi, togi, exti} i
     0011 11iiiiii ADDI it <- it + (whole field, thus allowing many negative numbers)
     0100 iiiiiiii BEZI branch pc ± i if it == 0
     0101 iiiiiiii JOFI jump offset to pc ± i
     0110 iiiiiiii CABI call absolute code[i], it <- return addr, code <- return segment
     0111 iiiiiiii COFI call offset pc ± i, it <- return offset (-i + 2)
     10xx iiiiiiii      (reserved w/ immediate)
     110x iiiiiiii      (reserved w/ immediate)
     1110 iiiiiiii GETI it <- i
     1111 xxxxxxxx EXT1 extended encoding for "future-proofing"

11 free no-argument encodings
6 free register encodings - possibly load-then-decrement? possibly 16-bit ADD and SUB with register pairs?
6 free immediate encodings

Some dubiously "nice" properties:
- 0 is invalid
- 1111_xxxx takes immediate
- Register instructions are all consecutive (0010_0aaa through 1110_1aaa)
- No reg/imm ops, so data line can be the immediate
- Two data segments, because I'm generous like that
- get/set pairs consistently differentiated by bit 3
- Future-proofing! Because that's definitely a thing that this set needs
- The nicest instruction is "ADDR r5"
- Near and far calls (okay, this is not nice)