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patch-sun50i-a64.dtsi

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Oct 25th, 2018
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  1. diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  2. index 5202b76e9684..9024b6f23200 100644
  3. --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  4. +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  5. @@ -43,9 +43,11 @@
  6. */
  7.  
  8. #include <dt-bindings/clock/sun50i-a64-ccu.h>
  9. +#include <dt-bindings/clock/sun8i-de2.h>
  10. #include <dt-bindings/clock/sun8i-r-ccu.h>
  11. #include <dt-bindings/interrupt-controller/arm-gic.h>
  12. #include <dt-bindings/reset/sun50i-a64-ccu.h>
  13. +#include <dt-bindings/reset/sun8i-de2.h>
  14.  
  15. / {
  16. interrupt-parent = <&gic>;
  17. @@ -169,6 +171,41 @@
  18. #size-cells = <1>;
  19. ranges;
  20.  
  21. + display_clocks: clock@1000000 {
  22. + /* compatible is in per SoC .dtsi file */
  23. + reg = <0x01000000 0x100000>;
  24. + clocks = <&ccu CLK_DE>,
  25. + <&ccu CLK_BUS_DE>;
  26. + clock-names = "mod",
  27. + "bus";
  28. + resets = <&ccu RST_BUS_DE>;
  29. + #clock-cells = <1>;
  30. + #reset-cells = <1>;
  31. + };
  32. +
  33. + mixer0: mixer@1100000 {
  34. + compatible = "allwinner,sun8i-h3-de2-mixer-0";
  35. + reg = <0x01100000 0x100000>;
  36. + clocks = <&display_clocks CLK_BUS_MIXER0>,
  37. + <&display_clocks CLK_MIXER0>;
  38. + clock-names = "bus",
  39. + "mod";
  40. + resets = <&display_clocks RST_MIXER0>;
  41. +
  42. + ports {
  43. + #address-cells = <1>;
  44. + #size-cells = <0>;
  45. +
  46. + mixer0_out: port@1 {
  47. + reg = <1>;
  48. +
  49. + mixer0_out_tcon0: endpoint {
  50. + remote-endpoint = <&tcon0_in_mixer0>;
  51. + };
  52. + };
  53. + };
  54. + };
  55. +
  56. syscon: syscon@1c00000 {
  57. compatible = "allwinner,sun50i-a64-system-controller",
  58. "syscon";
  59. @@ -186,6 +223,41 @@
  60. #dma-cells = <1>;
  61. };
  62.  
  63. + tcon0: lcd-controller@1c0c000 {
  64. + compatible = "allwinner,sun8i-h3-tcon-tv",
  65. + "allwinner,sun8i-a83t-tcon-tv";
  66. + reg = <0x01c0c000 0x1000>;
  67. + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  68. + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
  69. + clock-names = "ahb", "tcon-ch1";
  70. + resets = <&ccu RST_BUS_TCON0>;
  71. + reset-names = "lcd";
  72. +
  73. + ports {
  74. + #address-cells = <1>;
  75. + #size-cells = <0>;
  76. +
  77. + tcon0_in: port@0 {
  78. + reg = <0>;
  79. +
  80. + tcon0_in_mixer0: endpoint {
  81. + remote-endpoint = <&mixer0_out_tcon0>;
  82. + };
  83. + };
  84. +
  85. + tcon0_out: port@1 {
  86. + #address-cells = <1>;
  87. + #size-cells = <0>;
  88. + reg = <1>;
  89. +
  90. + tcon0_out_hdmi: endpoint@1 {
  91. + reg = <1>;
  92. + remote-endpoint = <&hdmi_in_tcon0>;
  93. + };
  94. + };
  95. + };
  96. + };
  97. +
  98. mmc0: mmc@1c0f000 {
  99. compatible = "allwinner,sun50i-a64-mmc";
  100. reg = <0x01c0f000 0x1000>;
  101. @@ -630,6 +702,50 @@
  102. #interrupt-cells = <3>;
  103. };
  104.  
  105. + hdmi: hdmi@1ee0000 {
  106. + compatible = "allwinner,sun8i-h3-dw-hdmi",
  107. + "allwinner,sun8i-a83t-dw-hdmi";
  108. + reg = <0x01ee0000 0x10000>;
  109. + reg-io-width = <1>;
  110. + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  111. + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
  112. + <&ccu CLK_HDMI>;
  113. + clock-names = "iahb", "isfr", "tmds";
  114. + resets = <&ccu RST_BUS_HDMI1>;
  115. + reset-names = "ctrl";
  116. + phys = <&hdmi_phy>;
  117. + phy-names = "hdmi-phy";
  118. + status = "disabled";
  119. +
  120. + ports {
  121. + #address-cells = <1>;
  122. + #size-cells = <0>;
  123. +
  124. + hdmi_in: port@0 {
  125. + reg = <0>;
  126. +
  127. + hdmi_in_tcon0: endpoint {
  128. + remote-endpoint = <&tcon0_out_hdmi>;
  129. + };
  130. + };
  131. +
  132. + hdmi_out: port@1 {
  133. + reg = <1>;
  134. + };
  135. + };
  136. + };
  137. +
  138. + hdmi_phy: hdmi-phy@1ef0000 {
  139. + compatible = "allwinner,sun8i-h3-hdmi-phy";
  140. + reg = <0x01ef0000 0x10000>;
  141. + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
  142. + <&ccu 6>;
  143. + clock-names = "bus", "mod", "pll-0";
  144. + resets = <&ccu RST_BUS_HDMI0>;
  145. + reset-names = "phy";
  146. + #phy-cells = <0>;
  147. + };
  148. +
  149. rtc: rtc@1f00000 {
  150. compatible = "allwinner,sun6i-a31-rtc";
  151. reg = <0x01f00000 0x54>;
  152. @@ -693,5 +809,36 @@
  153. reg = <0x01c20ca0 0x20>;
  154. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  155. };
  156. +
  157. + mali: gpu@1c40000 {
  158. + compatible = "allwinner,sun50i-h5-mali", "arm,mali-400";
  159. + reg = <0x01c40000 0x10000>;
  160. + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
  161. + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
  162. + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
  163. + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  164. + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  165. + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
  166. + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
  167. + interrupt-names = "gp",
  168. + "gpmmu",
  169. + "pp0",
  170. + "ppmmu0",
  171. + "pp1",
  172. + "ppmmu1",
  173. + "pmu";
  174. + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
  175. + clock-names = "bus", "core";
  176. + resets = <&ccu RST_BUS_GPU>;
  177. +
  178. + assigned-clocks = <&ccu CLK_GPU>;
  179. + assigned-clock-rates = <576000000>;
  180. + };
  181. + };
  182. +
  183. + de: display-engine {
  184. + compatible = "allwinner,sun8i-h3-display-engine";
  185. + allwinner,pipelines = <&mixer0>;
  186. + status = "enabled";
  187. };
  188. };
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