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andyp73
Nov 18th, 2021
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  1. FMAP: Found "FLASH" version 1.1 at 0x3f1040.
  2. FMAP: base = 0x0 size = 0x800000 #areas = 7
  3. FMAP: area COREBOOT found @ 3f1240 (4255168 bytes)
  4. ERROR: CBFS @ 3f1240 size 40edc0 exceeds mem-mapped area @ 1000 size 6be000
  5. FMAP: area COREBOOT found @ 3f1240 (4255168 bytes)
  6. CBFS: Found 'fallback/romstage' @0x80 size 0xc878
  7. BS: bootblock times (exec / console): total (unknown) / 42 ms
  8.  
  9.  
  10. coreboot-4.13-6490-g2194221849-dirty Thu Nov 18 11:46:03 UTC 2021 romstage starting (log level: 7)...
  11. CPU: Intel(R) Pentium(R) Silver N5030 CPU @ 1.10GHz
  12. CPU: ID 706a8, Geminilake R0, ucode: 00000019
  13. CPU: AES Supported, TXT Not Supported, VT Supported
  14. MCH: device id 31f0 (rev 06) is Geminilake
  15. PCH: device id 31e8 (rev 06) is Geminilake
  16. IGD: device id 3184 (rev 06) is Geminilake
  17. pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000
  18. gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
  19. gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
  20. gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
  21. gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
  22. prsts: 00000000
  23. tco_sts: 0000 0000
  24. gen_pmcon1: 08004004 gen_pmcon2: 00003a00 gen_pmcon3: 00000000
  25. prev_sleep_state 5
  26. CBFS: Found 'fspm.bin' @0x52d80 size 0x66000
  27. FMAP: area RW_MRC_CACHE found @ 381040 (65536 bytes)
  28. MRC: no data in 'RW_MRC_CACHE'
  29.  
  30. ============= FSP Spec v2.0 Header Revision v3 ($GLKFSP$ v2.2.0.0) =============
  31. Fsp BootFirmwareVolumeBase - 0xFEF40000
  32. Fsp BootFirmwareVolumeSize - 0x66000
  33. Fsp TemporaryRamBase - 0xFEFD6000
  34. Fsp TemporaryRamSize - 0x2A000
  35. Fsp PeiTemporaryRamBase - 0xFEFD6000
  36. Fsp PeiTemporaryRamSize - 0x1B4CC
  37. Fsp StackBase - 0xFEFF14CC
  38. Fsp StackSize - 0xEB34
  39. GPIO pad is not owned by host! skip it. Ownership: 03
  40. GPIO pad is not owned by host! skip it. Ownership: 03
  41. Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
  42. Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
  43. The 0th FV start address is 0x000FEF40000, size is 0x00066000, handle is 0x0
  44. Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
  45. Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389
  46. Loading PEIM at 0x000FEF4EC90 EntryPoint=0x000FEF4EFE5 PcdPeim.efi
  47. Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480
  48. Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1
  49. Loading PEIM at 0x000FEF503E4 EntryPoint=0x000FEF50C9C FspInitPreMem.efi
  50. Install PPI: 820695B0-C2F2-4EC7-A252-DB0DBEE838A3
  51. Install PPI: CFE5EC91-31ED-47E9-BE7D-9CCB59134B71
  52. Install PPI: F8D5438E-26E1-481D-B63C-30D6EFF4A420
  53. Install PPI: CBD86677-362F-4C04-9459-A741326E05CF
  54. Install PPI: 563F8EDE-1FA5-45A2-BE23-B0B6A07DE239
  55. Loading PEIM at 0x000FEF54274 EntryPoint=0x000FEF56A22 SiInitPreMem.efi
  56. GPIO pad is not owned by host! skip it. Ownership: 03
  57. GPIO pad is not owned by host! skip it. Ownership: 03
  58. SiInitPrePolicy() Start
  59. ScInitPrePolicy() - Start
  60. POSTCODE=<0000DB00>
  61. ScInitPreMem() - Start
  62. POSTCODE=<0000DB02>
  63. ScEarlyInit() - Start
  64. ScSmbusInit() Start
  65. ScSmbusInit() End
  66. ConfigureLpcOnEarlyPei()
  67. ScEarlyInit() - End
  68. POSTCODE=<0000DB7F>
  69. ScInitPreMem() - End
  70. ScInitPrePolicy() - End
  71. POSTCODE=<0000DB10>
  72. ScConfigurePciePowerSequence ()
  73. Clearing BLKDQDA and BLKPLLEN
  74. Clearing BLKDQDA and BLKPLLEN
  75. Clearing BLKDQDA and BLKPLLEN
  76. Clearing BLKDQDA and BLKPLLEN
  77. Clearing BLKDQDA and BLKPLLEN
  78. Clearing BLKDQDA and BLKPLLEN
  79. Pre-Mem North Cluster Entry
  80. POSTCODE=<0000DA00>
  81. PeiNpkInit() - Start
  82. NpkReserveHob->NpkPreMemConfig.TraceHubEn = 0x0
  83. NpkReserveHob->NpkPreMemConfig.TraceHubVrcTapEn = 0x0
  84. NpkReserveHob->NpkPreMemConfig.FwTraceEn = 0x1
  85. NpkReserveHob->NpkPreMemConfig.RecoverDump = 0x0
  86. NpkReserveHob->NpkPreMemConfig.FwTraceDestination = 0x4
  87. NpkReserveHob->NpkPreMemConfig.Msc0Size = 0x0
  88. NpkReserveHob->NpkPreMemConfig.Msc0Wrap = 0x1
  89. NpkReserveHob->NpkPreMemConfig.Msc1Size = 0x0
  90. NpkReserveHob->NpkPreMemConfig.Msc1Wrap = 0x1
  91. NpkReserveHob->NpkPreMemConfig.PtiMode = 0x1
  92. NpkReserveHob->NpkPreMemConfig.PtiTraining = 0x0
  93. NpkReserveHob->NpkPreMemConfig.PtiSpeed = 0x2
  94. NpkReserveHob->NpkPreMemConfig.PunitMlvl = 0x1
  95. NpkReserveHob->NpkPreMemConfig.PmcMlvl = 0x1
  96. NpkReserveHob->NpkPreMemConfig.SwTraceEn = 0x0
  97. CSE Host_Secboot_0 value 0xE
  98. Skipping: PO Workaround Disable NPK by sending IPC1 message.
  99. BaseAddress: 0xFE042000
  100. tempCommand: 0xED
  101. CmdType:0x0
  102. ReturnDataSize:0x0
  103. BufferSize:0
  104. Disable NPK by sending IPC1 message.
  105. Initializing Pre-Mem Graphics
  106. POSTCODE=<0000DA50>
  107. iGFX initialization Start
  108. IGD enabled.
  109. GMSData: 0x2
  110. IGD VGA Decode is disabled because it's not a primary display.
  111. iGFX initialization End
  112. Pre-Mem North Cluster Exit
  113. POSTCODE=<0000DA7F>
  114. SiInitPrePolicy() - End
  115. Loading PEIM at 0x000FEF5D344 EntryPoint=0x000FEF717CD MemoryInit.efi
  116. GPIO pad is not owned by host! skip it. Ownership: 03
  117. GPIO pad is not owned by host! skip it. Ownership: 03
  118. Profile is now set to: 6
  119. MRC SeCUmaSize memory size from SeC ... 0
  120. PeimMemoryInit - current boot mode: 00
  121. GLK R0 Detected.
  122. CPU stepping = 192.
  123. BXT Series = 3.
  124. SKPD: 0x00000000 DEBUP: 0x00000000
  125. MRC Parameters not valid. Status is Success
  126. MRC: DRAM in SR: 0
  127. Cold boot detected.
  128. CurrentBootMode -> 8 ValidFlag -> 0
  129. NOT Restore Path
  130. Ch[0] 2 ranks
  131. Ch[1] 2 ranks
  132. DIMM0 Memory Size: 2048, System Mem 2048 in MB
  133. DIMM1 Memory Size: 2048, System Mem 4096 in MB
  134. Ch0 SLICE_0_MASTER: 1 SLICE_1_MASTER: 0
  135. Overall ChEnMask: 0x3
  136. LP3/LP4 ChEnMask PHY0: 0x3 PHY1: 0x0
  137. FREQ_HIGH: 18
  138. Current Profile:6
  139. BootMode set to: 8 (FB=0x10; S5=8; S0=1,2,4; S3=0x20)
  140. CurrentFreq = 5 (1333 = 2, 1600 = 3, 1866 =4, 2133 = 5, 2400 = 6, 2666 = 7, 3200 = 8)
  141. SystemMemSize = 1000
  142. CH 0 Enabled LPDDR4
  143. CH 1 Enabled LPDDR4
  144. CP 00
  145. DISPLAYMMRCVERSION
  146. MRC REVISION ID 1.37.00
  147. + MMRC REVISION ID 1.37
  148. DRAM Policy:
  149. ChannelHashMask :0x36
  150. SliceHashMask :0x9
  151. ChannelsSlicesEnabled :0x0
  152. ScramblerSupport :0x1
  153. InterleavedMode :0x2
  154. MinRefRate2xEnabled :0x0
  155. DualRankSupportEnabled :0x3
  156. Profile :0x6
  157. SpdAddress[0] :0x0
  158. SpdAddress[1] :0x0
  159. SystemMemorySizeLimit :0x0
  160. LowMemMaxVal :0x0
  161. HighMemMaxVal :0x0
  162. DisableFastBoot :0x0
  163. RmtMode :0x0
  164. RmtCheckRun :0x0
  165. RmtMarginCheckScaleHighThreshold:0x0
  166. MsgLevelMask :0x0
  167. MemoryDown :0x1
  168. Channel0:
  169. RankEnable :0x3
  170. DeviceWidth :0x1
  171. DramDensity :0x2
  172. Option :0x3
  173. OdtConfig :0x2
  174. TristateClk1 :0x0
  175. Mode2N :0x0
  176. OdtLevels :0x0
  177. Swizzling:
  178. F B D E 9 C A 8 6 4 5 7 3 2 1 0 1E 19 18 1C 1D 1B 1F 1A 14 15 17 10 16 12 11 13
  179. Channel1:
  180. RankEnable :0x3
  181. DeviceWidth :0x1
  182. DramDensity :0x2
  183. Option :0x3
  184. OdtConfig :0x2
  185. TristateClk1 :0x0
  186. Mode2N :0x0
  187. OdtLevels :0x0
  188. Swizzling:
  189. 3 5 6 7 1 4 2 0 C D E B A 8 9 F 10 16 15 13 14 17 12 11 1F 1E 1B 19 18 1D 1C 1A
  190. CP 01
  191. MmrcCheckFreqConfig
  192. FREQ_HIGH: 18
  193. FreqHi 6
  194. CP 02
  195. Won't run on disabled channels
  196. MmrcConvertParams
  197. B0 Stepping detected, Dynamic Diffamp Enabled.
  198. MrcData::DVFSFreqIndex set to 0
  199. ChEnMask: 0x1
  200. MrcData::AddrMirror: 0 CASWIZZLE 1
  201. C=0 TCWL: 0x12
  202. CustomTSV Enabled
  203. SABy2Clk: 333; SpidClk: 267
  204. CustomTSV: 23
  205. CMD_RDPTROFFSET_ADUST = 1
  206. CA OdtConfig:High_High
  207. Won't run on disabled channels
  208. MmrcConvertParams
  209. B0 Stepping detected, Dynamic Diffamp Enabled.
  210. MrcData::DVFSFreqIndex set to 0
  211. ChEnMask: 0x3
  212. MrcData::AddrMirror: 0 CASWIZZLE 1
  213. C=1 TCWL: 0x12
  214. CustomTSV Enabled
  215. SABy2Clk: 333; SpidClk: 267
  216. CustomTSV: 23
  217. CMD_RDPTROFFSET_ADUST = 1
  218. CA OdtConfig:High_High
  219. CP F1
  220. Won't run on disabled channels
  221. SWSetHiFrequency
  222. Speed set to:5
  223. Won't run on disabled channels
  224. SWSetHiFrequency
  225. Speed set to:5
  226. CP 03
  227. CP 04
  228. CP 05
  229. CP 07
  230. Forcing run on disabled channels
  231. Forcing run on disabled channels
  232. CP 08
  233. Forcing run on disabled channels
  234. Forcing run on disabled channels
  235. Forcing run on disabled channels
  236. Forcing run on disabled channels
  237. CP 09
  238. Forcing run on disabled channels
  239. Forcing run on disabled channels
  240. Forcing run on disabled channels
  241. Forcing run on disabled channels
  242. CP 10
  243. Forcing run on disabled channels
  244. Forcing run on disabled channels
  245. Forcing run on disabled channels
  246. Forcing run on disabled channels
  247. CP 11
  248. Forcing run on disabled channels
  249. Forcing run on disabled channels
  250. Forcing run on disabled channels
  251. Forcing run on disabled channels
  252. CP 12
  253. Forcing run on disabled channels
  254. Forcing run on disabled channels
  255. Forcing run on disabled channels
  256. Forcing run on disabled channels
  257. CP 14
  258. Forcing run on disabled channels
  259. Forcing run on disabled channels
  260. Forcing run on disabled channels
  261. Forcing run on disabled channels
  262. CP 16
  263. Forcing run on disabled channels
  264. Forcing run on disabled channels
  265. Forcing run on disabled channels
  266. Forcing run on disabled channels
  267. CP 17
  268. Forcing run on disabled channels
  269. Forcing run on disabled channels
  270. Forcing run on disabled channels
  271. Forcing run on disabled channels
  272. CP 18
  273. Forcing run on disabled channels
  274. Forcing run on disabled channels
  275. Forcing run on disabled channels
  276. Forcing run on disabled channels
  277. CP 19
  278. Forcing run on disabled channels
  279. Forcing run on disabled channels
  280. Forcing run on disabled channels
  281. Forcing run on disabled channels
  282. CP 20
  283. Forcing run on disabled channels
  284. Forcing run on disabled channels
  285. Forcing run on disabled channels
  286. Forcing run on disabled channels
  287. CP 21
  288. Forcing run on disabled channels
  289. Forcing run on disabled channels
  290. Forcing run on disabled channels
  291. Forcing run on disabled channels
  292. CP 22
  293. CP 23
  294. CP 24
  295. CP 26
  296. Forcing run on disabled channels
  297. Forcing run on disabled channels
  298. Forcing run on disabled channels
  299. Forcing run on disabled channels
  300. CP 27
  301. Forcing run on disabled channels
  302. Forcing run on disabled channels
  303. Forcing run on disabled channels
  304. Forcing run on disabled channels
  305. CP 28
  306. Forcing run on disabled channels
  307. Forcing run on disabled channels
  308. Forcing run on disabled channels
  309. Forcing run on disabled channels
  310. CP 30
  311. Forcing run on disabled channels
  312. Forcing run on disabled channels
  313. Forcing run on disabled channels
  314. Forcing run on disabled channels
  315. CP 31
  316. Forcing run on disabled channels
  317. Forcing run on disabled channels
  318. Forcing run on disabled channels
  319. Forcing run on disabled channels
  320. CP 36
  321. Forcing run on disabled channels
  322. Forcing run on disabled channels
  323. Forcing run on disabled channels
  324. Forcing run on disabled channels
  325. CP 36
  326. Forcing run on disabled channels
  327. Forcing run on disabled channels
  328. CP F1
  329. HWSetBootFrequency
  330. Set Boot Freq:3 Speed set to:3
  331. MAXPI State = MAXPI_INIT
  332. Ecc Disabled
  333. setting dq_finec=0
  334. setting ccc_finec=0
  335. A0 Offset 0
  336. CH0 Limits
  337. Fine Hard: 0x2A - 0xB0
  338. Mux : 0xD - 0x1A
  339. Coarse : 0x6 - 0xE
  340. Fine Soft: 0x30 - 0xA0
  341. MAXPI State = MAXPI_DLLINIT
  342. CH0 Limits
  343. Fine Hard: 0x2A - 0xB0
  344. Mux : 0xD - 0x1A
  345. Coarse : 0x6 - 0xE
  346. Fine Soft: 0x30 - 0xA0
  347. DQ_CH_ERR_STAT 0x00000001
  348. DQ_CODE_STAT 0x00156669
  349. CH 0:DQ 0:RK 0:Val 0x00000015:Max 0x00000015 Err:0 Coarse:6 Coarsei:6 Fine:105 ctlebias=4
  350. CCC0_CH_ERR_STAT 0x00000001
  351. CCC0_CODE_STAT 0x00156669
  352. CCC0_CH 0:DQ 0:RK 0:Val 0x00000015:Max 0x00000015 Err:0 Coarse:6 Coarsei:6 Fine:105
  353. DQ_CH_ERR_STAT 0x00000001
  354. DQ_CODE_STAT 0x00156669
  355. CH 0:DQ 1:RK 0:Val 0x00000015:Max 0x00000015 Err:0 Coarse:6 Coarsei:6 Fine:105 ctlebias=4
  356. CH1 Limits
  357. Fine Hard: 0x2A - 0xB0
  358. Mux : 0xD - 0x1A
  359. Coarse : 0x6 - 0xE
  360. Fine Soft: 0x0 - 0x0
  361. DQ_CH_ERR_STAT 0x00000001
  362. DQ_CODE_STAT 0x00166688
  363. CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:136 ctlebias=4
  364. CCC1_CH_ERR_STAT 0x00000001
  365. CCC1_CODE_STAT 0x00166684
  366. CCC1_CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:132
  367. DQ_CH_ERR_STAT 0x00000001
  368. DQ_CODE_STAT 0x00166681
  369. CH 1:DQ 1:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:129 ctlebias=4
  370. MAXPI State = MAXPI_CHECK_ACROSS_FAMILY
  371. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch0 Coarse Range from 00000004 to 0000000F
  372. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch0 Muxcode Range from 00000016 to 00000016
  373. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch1 Coarse Range from 00000004 to 0000000F
  374. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch1 Muxcode Range from 00000016 to 00000016
  375. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch2 Coarse Range from 00000004 to 0000000F
  376. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch2 Muxcode Range from 00000016 to 00000016
  377. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch3 Coarse Range from 00000004 to 0000000F
  378. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch3 Muxcode Range from 00000016 to 00000016
  379. MAXPI State = MAXPI_SETUP_WIDER_RANGE
  380. MAXPI State = MAXPI_DLLINIT
  381. CH0 Limits
  382. Fine Hard: 0x2A - 0xB0
  383. Mux : 0x16 - 0x16
  384. Coarse : 0x4 - 0xF
  385. Fine Soft: 0x30 - 0xA0
  386. DQ_CH_ERR_STAT 0x00000001
  387. DQ_CODE_STAT 0x00167769
  388. CH 0:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:105 ctlebias=5
  389. CCC0_CH_ERR_STAT 0x00000001
  390. CCC0_CODE_STAT 0x00167769
  391. CCC0_CH 0:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:105
  392. DQ_CH_ERR_STAT 0x00000001
  393. DQ_CODE_STAT 0x0016776B
  394. CH 0:DQ 1:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:107 ctlebias=5
  395. CH1 Limits
  396. Fine Hard: 0x2A - 0xB0
  397. Mux : 0x16 - 0x16
  398. Coarse : 0x4 - 0xF
  399. Fine Soft: 0x0 - 0x0
  400. DQ_CH_ERR_STAT 0x00000001
  401. DQ_CODE_STAT 0x00166686
  402. CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:134 ctlebias=4
  403. CCC1_CH_ERR_STAT 0x00000001
  404. CCC1_CODE_STAT 0x00166681
  405. CCC1_CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:129
  406. DQ_CH_ERR_STAT 0x00000001
  407. DQ_CODE_STAT 0x0016667F
  408. CH 1:DQ 1:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:127 ctlebias=4
  409. MAXPI State = MAXPI_CHECK_ACROSS_FAMILY
  410. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch0 Coarse Range from 00000004 to 0000000F
  411. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch0 Muxcode Range from 00000016 to 00000016
  412. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch1 Coarse Range from 00000004 to 0000000F
  413. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch1 Muxcode Range from 00000016 to 00000016
  414. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch2 Coarse Range from 00000004 to 0000000F
  415. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch2 Muxcode Range from 00000016 to 00000016
  416. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch3 Coarse Range from 00000004 to 0000000F
  417. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch3 Muxcode Range from 00000016 to 00000016
  418. MAXPI State = MAXPI_FINAL_VALUES
  419. MAXPI_FINAL_VALUES: MrcData->HalfClkPi = 0xB8(725 ps Estimate) FullRangePi = 0xB8(725 ps Estimate)
  420. MAXPI_FINAL_VALUES: Muxcode = 0x16
  421. dq_90:0x2D 180:0x5B 270:0x89 ccc_90:0x2D 180:0x5B 270:0x89 dq_rxdll_rxmuxsel:0x1C
  422. ccc_rxdll_rxmuxsel:0x1C
  423. db1:0x16, db2:0x2D, db3:0x44 db4:0x5B, db5:0x72, db6:0x89, db7:0xA0
  424. setting dq_finec=1
  425. setting ccc_finec=1
  426. CH0 Limits
  427. Fine Hard: 0x2A - 0xB0
  428. Mux : 0x16 - 0x16
  429. Coarse : 0x4 - 0xF
  430. Fine Soft: 0x30 - 0xA0
  431. DQ_CH_ERR_STAT 0x00000001
  432. DQ_CODE_STAT 0x0016776A
  433. CH 0:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:106 ctlebias=5
  434. CCC0_CH_ERR_STAT 0x00000001
  435. CCC0_CODE_STAT 0x00166694
  436. CCC0_CH 0:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:148
  437. DQ_CH_ERR_STAT 0x00000001
  438. DQ_CODE_STAT 0x0016776A
  439. CH 0:DQ 1:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:106 ctlebias=5
  440. CH1 Limits
  441. Fine Hard: 0x2A - 0xB0
  442. Mux : 0x16 - 0x16
  443. Coarse : 0x4 - 0xF
  444. Fine Soft: 0x0 - 0x0
  445. DQ_CH_ERR_STAT 0x00000001
  446. DQ_CODE_STAT 0x0016668B
  447. CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:139 ctlebias=4
  448. CCC1_CH_ERR_STAT 0x00000001
  449. CCC1_CODE_STAT 0x00166682
  450. CCC1_CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:130
  451. DQ_CH_ERR_STAT 0x00000001
  452. DQ_CODE_STAT 0x00166680
  453. CH 1:DQ 1:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:128 ctlebias=4
  454. 0:374->378
  455. 1:374->378
  456. 2:372->375
  457. Ch 0:fbclktrim:0xF
  458. 0:374->378
  459. 1:374->378
  460. 2:372->375
  461. Ch 1:fbclktrim:0x1F
  462. DefaultCmdClkCtl=1
  463. DefaultCmdClkCtl=1
  464. DefaultCmdClkCtl=1
  465. DefaultCmdClkCtl=1
  466. CP 39
  467. SetupMaxPI
  468. MAXPI State = MAXPI_INIT
  469. Ecc Disabled
  470. setting dq_finec=0
  471. setting ccc_finec=0
  472. A0 Offset 0
  473. CH0 Limits
  474. Fine Hard: 0x2A - 0xB0
  475. Mux : 0xD - 0x1A
  476. Coarse : 0x4 - 0xF
  477. Fine Soft: 0x30 - 0xA0
  478. WarmBoot: Muxcode=22
  479. MAXPI State = MAXPI_FINAL_VALUES
  480. MAXPI_FINAL_VALUES: MrcData->HalfClkPi = 0xB8(725 ps Estimate) FullRangePi = 0xB8(725 ps Estimate)
  481. MAXPI_FINAL_VALUES: Muxcode = 0x16
  482. dq_90:0x2D 180:0x5B 270:0x89 ccc_90:0x2D 180:0x5B 270:0x89 dq_rxdll_rxmuxsel:0x1C
  483. ccc_rxdll_rxmuxsel:0x1C
  484. db1:0x16, db2:0x2D, db3:0x44 db4:0x5B, db5:0x72, db6:0x89, db7:0xA0
  485. setting dq_finec=1
  486. setting ccc_finec=1
  487. CH0 Limits
  488. Fine Hard: 0x2A - 0xB0
  489. Mux : 0x16 - 0x16
  490. Coarse : 0x4 - 0xF
  491. Fine Soft: 0x30 - 0xA0
  492. DQ_CH_ERR_STAT 0x00000001
  493. DQ_CODE_STAT 0x00167776
  494. CH 0:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:118 ctlebias=5
  495. CCC0_CH_ERR_STAT 0x00000001
  496. CCC0_CODE_STAT 0x00167776
  497. CCC0_CH 0:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:118
  498. DQ_CH_ERR_STAT 0x00000001
  499. DQ_CODE_STAT 0x00167773
  500. CH 0:DQ 1:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:115 ctlebias=5
  501. CH1 Limits
  502. Fine Hard: 0x2A - 0xB0
  503. Mux : 0x16 - 0x16
  504. Coarse : 0x4 - 0xF
  505. Fine Soft: 0x0 - 0x0
  506. DQ_CH_ERR_STAT 0x00000001
  507. DQ_CODE_STAT 0x00166698
  508. CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:152 ctlebias=4
  509. CCC1_CH_ERR_STAT 0x00000001
  510. CCC1_CODE_STAT 0x0016668F
  511. CCC1_CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:143
  512. DQ_CH_ERR_STAT 0x00000001
  513. DQ_CODE_STAT 0x0016668B
  514. CH 1:DQ 1:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:139 ctlebias=4
  515. Ch 0:fbclktrim:0xF
  516. Ch 1:fbclktrim:0x1F
  517. CP 35
  518. CalculateAndSetCtleBias
  519. CP 3C
  520. Forcing run on disabled channels
  521. Forcing run on disabled channels
  522. Forcing run on disabled channels
  523. Forcing run on disabled channels
  524. CP 3D
  525. Forcing run on disabled channels
  526. Forcing run on disabled channels
  527. Forcing run on disabled channels
  528. Forcing run on disabled channels
  529. CP 3F
  530. ClkGatePhy
  531. ClkGatePhy
  532. Ch2 disable
  533. Ch3 disable
  534. CP 40
  535. Forcing run on disabled channels
  536. Forcing run on disabled channels
  537. Forcing run on disabled channels
  538. Forcing run on disabled channels
  539. CP 41
  540. Won't run on disabled channels
  541. Channel0Only
  542. Won't run on disabled channels
  543. Channel0Only
  544. CP F1
  545. SWSetHiFrequency
  546. Speed set to:5
  547. CP 43
  548. CP 47
  549. Won't run on disabled channels
  550. Won't run on disabled channels
  551. CP 44
  552. CP 49
  553. DramPhysicalReset
  554. DRAM Resetting
  555. CP 4A
  556. Won't run on disabled channels
  557. Won't run on disabled channels
  558. CP F1
  559. Won't run on disabled channels
  560. SWSetBootFrequency
  561. Set Software Init Freq:3 Speed set to:3
  562. Won't run on disabled channels
  563. SWSetBootFrequency
  564. CP 4B
  565. Won't run on disabled channels
  566. R2RDynamicSetup
  567. Won't run on disabled channels
  568. R2RDynamicSetup
  569. CP 4C
  570. Won't run on disabled channels
  571. Won't run on disabled channels
  572. CP C0
  573. CP 4E
  574. Won't run on disabled channels
  575. LP4MRProgramming_ODTVREF
  576. Won't run on disabled channels
  577. LP4MRProgramming_ODTVREF
  578. CP 4F
  579. Won't run on disabled channels
  580. DiffAmpOverride_PostAstep
  581. Won't run on disabled channels
  582. DiffAmpOverride_PostAstep
  583. CP 4F
  584. Won't run on disabled channels
  585. DiffAmpOverride_AstepOnly
  586. Won't run on disabled channels
  587. DiffAmpOverride_AstepOnly
  588. CP A0
  589. Won't run on disabled channels
  590. VOCTraining
  591. Comp Vref Code = 4
  592. Pull Up Ron = 140
  593. Pull Up COMP Vref Code = 4
  594. Pull Up RComp = 9
  595. Pull Dn Ron = 40
  596. Pull Dn COMP Vref Code = 41
  597. Pull Dn RComp = 39, 39, 39
  598. Sweeping Vref for 1->0 transition on VOCSampler holding VOC=0
  599. VOC SL0:00:00:00:00:00:00:00:00 SL1:00:00:00:00:00:00:00:00 SL2:00:00:00:00:00:00:00:00 SL3:00:00:00:00:00:00:00:00
  600. VREF SL0:21:19:21:23:18:21:21:22[20] SL1:22:15:21:18:23:20:21:23[19] SL2:20:19:23:20:20:19:20:18[20] SL3:21:18:21:20:22:20:19:18[20]
  601. 00 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  602. 01 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  603. 02 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  604. 03 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  605. 04 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  606. 05 1:1:1:1:1:1:1:1: 1:0:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  607. 06 1:0:1:1:0:1:1:1: 1:0:1:1:1:1:1:1: 1:0:1:1:1:1:1:0: 1:0:1:1:1:1:1:0:
  608. 07 1:0:1:1:0:1:1:1: 1:0:1:0:1:1:1:1: 0:0:1:0:0:0:0:0: 1:0:0:0:1:0:0:0:
  609. 08 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:1: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  610. 09 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  611. 10 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  612. 11 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  613. 12 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  614. 13 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  615. 14 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  616. 15 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  617. Resetting Voc to 0
  618. Resetting Voc to 0
  619. Resetting Voc to 0
  620. Resetting Voc to 0
  621.  
  622. Sweeping Vref for 1->0 transition on VOCSampler with VOC Normalized.
  623. VOC SL0:08:06:08:08:06:08:08:08 SL1:08:05:08:07:08:08:08:09 SL2:07:07:08:07:07:07:07:06 SL3:08:06:08:07:08:07:07:06
  624. VREF SL0:18:20:18:19:20:17:18:19[18] SL1:19:18:18:18:19:16:18:18[17] SL2:20:19:21:20:20:19:20:20[20] SL3:17:20:17:20:19:20:19:20[18]
  625. Won't run on disabled channels
  626. VOCTraining
  627. Comp Vref Code = 4
  628. Pull Up Ron = 140
  629. Pull Up COMP Vref Code = 4
  630. Pull Up RComp = 9
  631. Pull Dn Ron = 40
  632. Pull Dn COMP Vref Code = 41
  633. Pull Dn RComp = 39, 39, 39
  634. Sweeping Vref for 1->0 transition on VOCSampler holding VOC=0
  635. VOC SL0:00:00:00:00:00:00:00:00 SL1:00:00:00:00:00:00:00:00 SL2:00:00:00:00:00:00:00:00 SL3:00:00:00:00:00:00:00:00
  636. VREF SL0:21:21:18:21:24:20:22:24[21] SL1:18:22:20:21:19:21:21:22[20] SL2:22:19:21:22:20:22:21:26[22] SL3:20:21:24:22:20:20:19:21[21]
  637. 00 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  638. 01 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  639. 02 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  640. 03 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  641. 04 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  642. 05 1:1:0:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:0:1:1:1:1:1:1: 1:1:1:1:1:1:1:1:
  643. 06 1:1:0:1:1:0:1:1: 0:1:1:1:0:1:1:1: 1:0:0:1:0:1:0:1: 0:1:1:1:0:1:0:1:
  644. 07 0:0:0:0:1:0:1:1: 0:1:0:1:0:1:1:1: 0:0:0:0:0:0:0:1: 0:0:1:1:0:0:0:0:
  645. 08 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:1: 0:0:0:0:0:0:0:0:
  646. 09 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  647. 10 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  648. 11 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  649. 12 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  650. 13 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  651. 14 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  652. 15 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0:
  653. Resetting Voc to 0
  654. Resetting Voc to 0
  655. Resetting Voc to 0
  656. Resetting Voc to 0
  657.  
  658. Sweeping Vref for 1->0 transition on VOCSampler with VOC Normalized.
  659. VOC SL0:08:07:05:07:08:06:08:08 SL1:05:08:07:08:06:08:08:08 SL2:07:05:07:07:06:07:06:08 SL3:06:07:08:08:06:07:06:07
  660. VREF SL0:19:21:21:21:21:21:19:21[20] SL1:21:19:20:18:20:18:18:18[19] SL2:22:22:21:22:22:22:22:22[21] SL3:21:21:20:19:21:20:21:21[20]
  661. CP 50
  662. Won't run on disabled channels
  663. Won't run on disabled channels
  664. CP 51
  665. Won't run on disabled channels
  666. Lp4CBTEntryAllRanks
  667. Won't run on disabled channels
  668. Lp4CBTEntryAllRanks
  669. CP F1
  670. HWSetHiFrequency
  671. Speed set to:5
  672. MAXPI State = MAXPI_INIT
  673. Ecc Disabled
  674. setting dq_finec=0
  675. setting ccc_finec=0
  676. A0 Offset 0
  677. CH0 Limits
  678. Fine Hard: 0x2A - 0xB0
  679. Mux : 0xA - 0x14
  680. Coarse : 0x6 - 0xE
  681. Fine Soft: 0x30 - 0xA0
  682. MAXPI State = MAXPI_DLLINIT
  683. CH0 Limits
  684. Fine Hard: 0x2A - 0xB0
  685. Mux : 0xA - 0x14
  686. Coarse : 0x6 - 0xE
  687. Fine Soft: 0x30 - 0xA0
  688. DQ_CH_ERR_STAT 0x00000001
  689. DQ_CODE_STAT 0x00107769
  690. CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:105 ctlebias=5
  691. CCC0_CH_ERR_STAT 0x00000001
  692. CCC0_CODE_STAT 0x0010776D
  693. CCC0_CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:109
  694. DQ_CH_ERR_STAT 0x00000001
  695. DQ_CODE_STAT 0x0010668F
  696. CH 0:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:143 ctlebias=4
  697. CH1 Limits
  698. Fine Hard: 0x2A - 0xB0
  699. Mux : 0xA - 0x14
  700. Coarse : 0x6 - 0xE
  701. Fine Soft: 0x0 - 0x0
  702. DQ_CH_ERR_STAT 0x00000001
  703. DQ_CODE_STAT 0x00106684
  704. CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:132 ctlebias=4
  705. CCC1_CH_ERR_STAT 0x00000001
  706. CCC1_CODE_STAT 0x00106681
  707. CCC1_CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:129
  708. DQ_CH_ERR_STAT 0x00000001
  709. DQ_CODE_STAT 0x0010667B
  710. CH 1:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:123 ctlebias=4
  711. MAXPI State = MAXPI_CHECK_ACROSS_FAMILY
  712. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch0 Coarse Range from 00000004 to 0000000F
  713. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch0 Muxcode Range from 00000010 to 00000010
  714. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch1 Coarse Range from 00000004 to 0000000F
  715. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch1 Muxcode Range from 00000010 to 00000010
  716. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch2 Coarse Range from 00000004 to 0000000F
  717. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch2 Muxcode Range from 00000010 to 00000010
  718. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch3 Coarse Range from 00000004 to 0000000F
  719. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch3 Muxcode Range from 00000010 to 00000010
  720. MAXPI State = MAXPI_SETUP_WIDER_RANGE
  721. MAXPI State = MAXPI_DLLINIT
  722. CH0 Limits
  723. Fine Hard: 0x2A - 0xB0
  724. Mux : 0x10 - 0x10
  725. Coarse : 0x4 - 0xF
  726. Fine Soft: 0x30 - 0xA0
  727. DQ_CH_ERR_STAT 0x00000001
  728. DQ_CODE_STAT 0x00107769
  729. CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:105 ctlebias=5
  730. CCC0_CH_ERR_STAT 0x00000001
  731. CCC0_CODE_STAT 0x0010776B
  732. CCC0_CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:107
  733. DQ_CH_ERR_STAT 0x00000001
  734. DQ_CODE_STAT 0x00106691
  735. CH 0:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:145 ctlebias=4
  736. CH1 Limits
  737. Fine Hard: 0x2A - 0xB0
  738. Mux : 0x10 - 0x10
  739. Coarse : 0x4 - 0xF
  740. Fine Soft: 0x0 - 0x0
  741. DQ_CH_ERR_STAT 0x00000001
  742. DQ_CODE_STAT 0x00106681
  743. CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:129 ctlebias=4
  744. CCC1_CH_ERR_STAT 0x00000001
  745. CCC1_CODE_STAT 0x00106681
  746. CCC1_CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:129
  747. DQ_CH_ERR_STAT 0x00000001
  748. DQ_CODE_STAT 0x00106678
  749. CH 1:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:120 ctlebias=4
  750. MAXPI State = MAXPI_CHECK_ACROSS_FAMILY
  751. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch0 Coarse Range from 00000004 to 0000000F
  752. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch0 Muxcode Range from 00000010 to 00000010
  753. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch1 Coarse Range from 00000004 to 0000000F
  754. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch1 Muxcode Range from 00000010 to 00000010
  755. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch2 Coarse Range from 00000004 to 0000000F
  756. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch2 Muxcode Range from 00000010 to 00000010
  757. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch3 Coarse Range from 00000004 to 0000000F
  758. MAXPI_CHECK_ACROSS_FAMILY: Setting Ch3 Muxcode Range from 00000010 to 00000010
  759. MAXPI State = MAXPI_FINAL_VALUES
  760. MAXPI_FINAL_VALUES: MrcData->HalfClkPi = 0x88(725 ps Estimate) FullRangePi = 0x88(725 ps Estimate)
  761. MAXPI_FINAL_VALUES: Muxcode = 0x10
  762. dq_90:0x21 180:0x43 270:0x65 ccc_90:0x21 180:0x43 270:0x65 dq_rxdll_rxmuxsel:0x15
  763. ccc_rxdll_rxmuxsel:0x15
  764. db1:0x10, db2:0x21, db3:0x32 db4:0x43, db5:0x54, db6:0x65, db7:0x76
  765. setting dq_finec=1
  766. setting ccc_finec=1
  767. CH0 Limits
  768. Fine Hard: 0x2A - 0xB0
  769. Mux : 0x10 - 0x10
  770. Coarse : 0x4 - 0xF
  771. Fine Soft: 0x30 - 0xA0
  772. DQ_CH_ERR_STAT 0x00000001
  773. DQ_CODE_STAT 0x00106696
  774. CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:150 ctlebias=4
  775. CCC0_CH_ERR_STAT 0x00000001
  776. CCC0_CODE_STAT 0x00107771
  777. CCC0_CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:113
  778. DQ_CH_ERR_STAT 0x00000001
  779. DQ_CODE_STAT 0x00106690
  780. CH 0:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:144 ctlebias=4
  781. CH1 Limits
  782. Fine Hard: 0x2A - 0xB0
  783. Mux : 0x10 - 0x10
  784. Coarse : 0x4 - 0xF
  785. Fine Soft: 0x0 - 0x0
  786. DQ_CH_ERR_STAT 0x00000001
  787. DQ_CODE_STAT 0x00106685
  788. CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:133 ctlebias=4
  789. CCC1_CH_ERR_STAT 0x00000001
  790. CCC1_CODE_STAT 0x00106680
  791. CCC1_CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:128
  792. DQ_CH_ERR_STAT 0x00000001
  793. DQ_CODE_STAT 0x00106677
  794. CH 1:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:119 ctlebias=4
  795. 0:281->289
  796. 1:281->289
  797. 2:279->285
  798. Ch 0:fbclktrim:0xF
  799. 0:281->289
  800. 1:281->289
  801. 2:279->285
  802. Ch 1:fbclktrim:0x1F
  803. DefaultCmdClkCtl=1
  804. DefaultCmdClkCtl=1
  805. DefaultCmdClkCtl=1
  806. DefaultCmdClkCtl=1
  807. CP A2
  808. Won't run on disabled channels
  809. EarlyCommandTraining
  810. Xls OffsetPushout: 2
  811. SMIP OffsetPushout: 0
  812. No additional Pushouts requested.
  813. Channel 0, Rank 0
  814. Control value 140
  815. S00K0
  816. ECT: S39000000, E33003300
  817. CH00 0142:-
  818. ECT: S06003A00, E33003300
  819. CH00 0176:-
  820. ECT: S06003A00, E33003300
  821. CH00 0210:-
  822. ECT: S06003A00, E33003300
  823. CH00 0244:-
  824. ECT: S06003A00, E33003300
  825. CH00 0278:-
  826. ECT: S06003A00, E33003300
  827. CH00 0312:-
  828. ECT: S06003A00, E33003300
  829. CH00 0346:-
  830. ECT: S06003A00, E33003300
  831. CH00 0380:-
  832. ECT: S06003A00, E33003300
  833. CH00 0414:-
  834. ECT: S06003A00, E33003300
  835. CH00 0414:-
  836. ECT: S06003A00, E33003300
  837. CH00 0380:-
  838. ECT: S06003A00, E33003300
  839. CH00 0346:-
  840. ECT: S06003A00, E33003300
  841. CH00 0312:-
  842. ECT: S06003A00, E33003300
  843. CH00 0278:-
  844. ECT: S06003A00, E33003300
  845. CH00 0244:-
  846. ECT: S06003A00, E33003300
  847. CH00 0210:-
  848. ECT: S06003A00, E33003300
  849. CH00 0176:-
  850. ECT: S06003A00, E33003300
  851. CH00 0142:-
  852. Control value 174
  853. S00K0
  854. ECT: S06003200, E33003300
  855. CH00 0142:-
  856. ECT: S39003A00, E33003300
  857. CH00 0176:-
  858. ECT: S39003A00, E33003300
  859. CH00 0210:-
  860. ECT: S39003A00, E33003300
  861. CH00 0244:-
  862. ECT: S39003A00, E33003300
  863. CH00 0278:-
  864. ECT: S39003A00, E33003300
  865. CH00 0312:-
  866. ECT: S39003A00, E33003300
  867. CH00 0346:-
  868. ECT: S39003A00, E33003300
  869. CH00 0380:-
  870. ECT: S39003A00, E33003300
  871. CH00 0414:-
  872. ECT: S39003A00, E33003300
  873. CH00 0414:-
  874. ECT: S39003A00, E33003300
  875. CH00 0380:-
  876. ECT: S39003A00, E33003300
  877. CH00 0346:-
  878. ECT: S39003A00, E33003300
  879. CH00 0312:-
  880. ECT: S39003A00, E33003300
  881. CH00 0278:-
  882. ECT: S39003A00, E33003300
  883. CH00 0244:-
  884. ECT: S39003A00, E33003300
  885. CH00 0210:-
  886. ECT: S39003A00, E33003300
  887. CH00 0176:-
  888. ECT: S06003200, E33003300
  889. CH00 0142:-
  890. Control value 208
  891. S00K0
  892. ECT: S06003200, E33003300
  893. CH00 0142:-
  894. ECT: S39003A00, E33003300
  895. CH00 0176:-
  896. ECT: S39003A00, E33003300
  897. CH00 0210:-
  898. ECT: S39003A00, E33003300
  899. CH00 0244:-
  900. ECT: S39003A00, E33003300
  901. CH00 0278:-
  902. ECT: S39003A00, E33003300
  903. CH00 0312:-
  904. ECT: S39003A00, E33003300
  905. CH00 0346:-
  906. ECT: S39003A00, E33003300
  907. CH00 0380:-
  908. ECT: S39003A00, E33003300
  909. CH00 0414:-
  910. ECT: S39003A00, E33003300
  911. CH00 0414:-
  912. ECT: S39003A00, E33003300
  913. CH00 0380:-
  914. ECT: S39003A00, E33003300
  915. CH00 0346:-
  916. ECT: S39003A00, E33003300
  917. CH00 0312:-
  918. ECT: S39003A00, E33003300
  919. CH00 0278:-
  920. ECT: S39003A00, E33003300
  921. CH00 0244:-
  922. ECT: S39003A00, E33003300
  923. CH00 0210:-
  924. ECT: S39003A00, E33003300
  925. CH00 0176:-
  926. ECT: S06003200, E33003300
  927. CH00 0142:-
  928. Control value 242
  929. S00K0
  930. ECT: S06003200, E33003300
  931. CH00 0142:-
  932. ECT: S39003A00, E33003300
  933. CH00 0176:-
  934. ECT: S39003A00, E33003300
  935. CH00 0210:-
  936. ECT: S39003A00, E33003300
  937. CH00 0244:-
  938. ECT: S39003A00, E33003300
  939. CH00 0278:-
  940. ECT: S39003A00, E33003300
  941. CH00 0312:-
  942. ECT: S39003A00, E33003300
  943. CH00 0346:-
  944. ECT: S39003A00, E33003300
  945. CH00 0380:-
  946. ECT: S39003A00, E33003300
  947. CH00 0414:-
  948. ECT: S39003A00, E33003300
  949. CH00 0414:-
  950. ECT: S39003A00, E33003300
  951. CH00 0380:-
  952. ECT: S39003A00, E33003300
  953. CH00 0346:-
  954. ECT: S39003A00, E33003300
  955. CH00 0312:-
  956. ECT: S39003A00, E33003300
  957. CH00 0278:-
  958. ECT: S39003A00, E33003300
  959. CH00 0244:-
  960. ECT: S39003A00, E33003300
  961. CH00 0210:-
  962. ECT: S39003A00, E33003300
  963. CH00 0176:-
  964. ECT: S39003A00, E33003300
  965. CH00 0142:-
  966. Control value 276
  967. S00K0
  968. ECT: S06003A00, E33003300
  969. CH00 0142:-
  970. ECT: S39003A00, E33003300
  971. CH00 0176:-
  972. ECT: S39003A00, E33003300
  973. CH00 0210:-
  974. ECT: S39003A00, E33003300
  975. CH00 0244:-
  976. ECT: S39003A00, E33003300
  977. CH00 0278:-
  978. ECT: S39003A00, E33003300
  979. CH00 0312:-
  980. ECT: S39003A00, E33003300
  981. CH00 0346:-
  982. ECT: S39003A00, E33003300
  983. CH00 0380:-
  984. ECT: S39003A00, E33003300
  985. CH00 0414:-
  986. ECT: S39003A00, E33003300
  987. CH00 0414:-
  988. ECT: S39003A00, E33003300
  989. CH00 0380:-
  990. ECT: S39003A00, E33003300
  991. CH00 0346:-
  992. ECT: S39003A00, E33003300
  993. CH00 0312:-
  994. ECT: S39003A00, E33003300
  995. CH00 0278:-
  996. ECT: S39003A00, E33003300
  997. CH00 0244:-
  998. ECT: S39003A00, E33003300
  999. CH00 0210:-
  1000. ECT: S39003A00, E33003300
  1001. CH00 0176:-
  1002. ECT: S06003200, E33003300
  1003. CH00 0142:-
  1004. Control value 310
  1005. S00K0
  1006. ECT: S06003A00, E33003300
  1007. CH00 0142:-
  1008. ECT: S39003A00, E33003300
  1009. CH00 0176:-
  1010. ECT: S39003A00, E33003300
  1011. CH00 0210:-
  1012. ECT: S39003A00, E33003300
  1013. CH00 0244:-
  1014. ECT: S39003A00, E33003300
  1015. CH00 0278:-
  1016. ECT: S39003A00, E33003300
  1017. CH00 0312:-
  1018. ECT: S39003A00, E33003300
  1019. CH00 0346:-
  1020. ECT: S39003A00, E33003300
  1021. CH00 0380:-
  1022. ECT: S39003A00, E33003300
  1023. CH00 0414:-
  1024. ECT: S39003A00, E33003300
  1025. CH00 0414:-
  1026. ECT: S39003A00, E33003300
  1027. CH00 0380:-
  1028. ECT: S39003A00, E33003300
  1029. CH00 0346:-
  1030. ECT: S39003A00, E33003300
  1031. CH00 0312:-
  1032. ECT: S39003A00, E33003300
  1033. CH00 0278:-
  1034. ECT: S39003A00, E33003300
  1035. CH00 0244:-
  1036. ECT: S39003A00, E33003300
  1037. CH00 0210:-
  1038. ECT: S39003A00, E33003300
  1039. CH00 0176:-
  1040. ECT: S06003A00, E33003300
  1041. CH00 0142:-
  1042. Control value 344
  1043. S00K0
  1044. ECT: S06003A00, E33003300
  1045. CH00 0142:-
  1046. ECT: S39003A00, E33003300
  1047. CH00 0176:-
  1048. ECT: S39003A00, E33003300
  1049. CH00 0210:-
  1050. ECT: S39003A00, E33003300
  1051. CH00 0244:-
  1052. ECT: S39003A00, E33003300
  1053. CH00 0278:-
  1054. ECT: S39003A00, E33003300
  1055. CH00 0312:-
  1056. ECT: S39003A00, E33003300
  1057. CH00 0346:-
  1058. ECT: S39003A00, E33003300
  1059. CH00 0380:-
  1060. ECT: S39003A00, E33003300
  1061. CH00 0414:-
  1062. ECT: S39003A00, E33003300
  1063. CH00 0414:-
  1064. ECT: S39003A00, E33003300
  1065. CH00 0380:-
  1066. ECT: S39003A00, E33003300
  1067. CH00 0346:-
  1068. ECT: S39003A00, E33003300
  1069. CH00 0312:-
  1070. ECT: S39003A00, E33003300
  1071. CH00 0278:-
  1072. ECT: S39003A00, E33003300
  1073. CH00 0244:-
  1074. ECT: S39003A00, E33003300
  1075. CH00 0210:-
  1076. ECT: S39003A00, E33003300
  1077. CH00 0176:-
  1078. ECT: S06003A00, E33003300
  1079. CH00 0142:-
  1080. Control value 378
  1081. S00K0
  1082. ECT: S06003A00, E33003300
  1083. CH00 0142:-
  1084. ECT: S39003A00, E33003300
  1085. CH00 0176:-
  1086. ECT: S39003A00, E33003300
  1087. CH00 0210:-
  1088. ECT: S39003A00, E33003300
  1089. CH00 0244:-
  1090. ECT: S39003A00, E33003300
  1091. CH00 0278:-
  1092. ECT: S39003A00, E33003300
  1093. CH00 0312:-
  1094. ECT: S39003A00, E33003300
  1095. CH00 0346:-
  1096. ECT: S39003A00, E33003300
  1097. CH00 0380:-
  1098. ECT: S39003A00, E33003300
  1099. CH00 0414:-
  1100. ECT: S39003A00, E33003300
  1101. CH00 0414:-
  1102. ECT: S39003A00, E33003300
  1103. CH00 0380:-
  1104. ECT: S39003A00, E33003300
  1105. CH00 0346:-
  1106. ECT: S39003A00, E33003300
  1107. CH00 0312:-
  1108. ECT: S39003A00, E33003300
  1109. CH00 0278:-
  1110. ECT: S39003A00, E33003300
  1111. CH00 0244:-
  1112. ECT: S39003A00, E33003300
  1113. CH00 0210:-
  1114. ECT: S39003A00, E33003300
  1115. CH00 0176:-
  1116. ECT: S06003A00, E33003300
  1117. CH00 0142:-
  1118. Control value 412
  1119. S00K0
  1120. ECT: S06000000, E33003300
  1121. CH00 0142:-
  1122. ECT: S39000000, E33003300
  1123. CH00 0176:-
  1124. ECT: S39000000, E33003300
  1125. CH00 0210:-
  1126. ECT: S39000000, E33003300
  1127. CH00 0244:-
  1128. ECT: S39000000, E33003300
  1129. CH00 0278:-
  1130. ECT: S39000000, E33003300
  1131. CH00 0312:-
  1132. ECT: S39000000, E33003300
  1133. CH00 0346:-
  1134. ECT: S39000000, E33003300
  1135. CH00 0380:-
  1136. ECT: S39000000, E33003300
  1137. CH00 0414:-
  1138. ECT: S39000000, E33003300
  1139. CH00 0414:-
  1140. ECT: S39000000, E33003300
  1141. CH00 0380:-
  1142. ECT: S39000000, E33003300
  1143. CH00 0346:-
  1144. ECT: S39000000, E33003300
  1145. CH00 0312:-
  1146. ECT: S39000000, E33003300
  1147. CH00 0278:-
  1148. ECT: S39000000, E33003300
  1149. CH00 0244:-
  1150. ECT: S39000000, E33003300
  1151. CH00 0210:-
  1152. ECT: S39000000, E33003300
  1153. CH00 0176:-
  1154. ECT: S06000000, E33003300
  1155. CH00 0142:-
  1156. ERROR: Highest Value found is a 0
  1157. Final solution Rank 0 = 0, 0, Channel 0, Rank 1
  1158. Control value 140
  1159. S00K0
  1160. ECT: S00000000, E33003300
  1161. CH00 0142:-
  1162. ECT: S00000000, E33003300
  1163. CH00 0176:-
  1164. ECT: S00000000, E33003300
  1165. CH00 0210:-
  1166. ECT: S00000000, E33003300
  1167. CH00 0244:-
  1168. ECT: S00000000, E33003300
  1169. CH00 0278:-
  1170. ECT: S00000000, E33003300
  1171. CH00 0312:-
  1172. ECT: S00000000, E33003300
  1173. CH00 0346:-
  1174. ECT: S00000000, E33003300
  1175. CH00 0380:-
  1176. ECT: S00000000, E33003300
  1177. CH00 0414:-
  1178. ECT: S00000000, E33003300
  1179. CH00 0414:-
  1180. ECT: S00000000, E33003300
  1181. CH00 0380:-
  1182. ECT: S00000000, E33003300
  1183. CH00 0346:-
  1184. ECT: S00000000, E33003300
  1185. CH00 0312:-
  1186. ECT: S00000000, E33003300
  1187. CH00 0278:-
  1188. ECT: S00000000, E33003300
  1189. CH00 0244:-
  1190. ECT: S00000000, E33003300
  1191. CH00 0210:-
  1192. ECT: S00000000, E33003300
  1193. CH00 0176:-
  1194. ECT: S00000000, E33003300
  1195. CH00 0142:-
  1196. Control value 174
  1197. S00K0
  1198. ECT: S00000000, E33003300
  1199. CH00 0142:-
  1200. ECT: S00000000, E33003300
  1201. CH00 0176:-
  1202. ECT: S00000000, E33003300
  1203. CH00 0210:-
  1204. ECT: S00000000, E33003300
  1205. CH00 0244:-
  1206. ECT: S00000000, E33003300
  1207. CH00 0278:-
  1208. ECT: S00000000, E33003300
  1209. CH00 0312:-
  1210. ECT: S00000000, E33003300
  1211. CH00 0346:-
  1212. ECT: S00000000, E33003300
  1213. CH00 0380:-
  1214. ECT: S00000000, E33003300
  1215. CH00 0414:-
  1216. ECT: S00000000, E33003300
  1217. CH00 0414:-
  1218. ECT: S00000000, E33003300
  1219. CH00 0380:-
  1220. ECT: S00000000, E33003300
  1221. CH00 0346:-
  1222. ECT: S00000000, E33003300
  1223. CH00 0312:-
  1224. ECT: S00000000, E33003300
  1225. CH00 0278:-
  1226. ECT: S00000000, E33003300
  1227. CH00 0244:-
  1228. ECT: S00000000, E33003300
  1229. CH00 0210:-
  1230. ECT: S00000000, E33003300
  1231. CH00 0176:-
  1232. ECT: S00000000, E33003300
  1233. CH00 0142:-
  1234. Control value 208
  1235. S00K0
  1236. ECT: S00000000, E33003300
  1237. CH00 0142:-
  1238. ECT: S00000000, E33003300
  1239. CH00 0176:-
  1240. ECT: S00000000, E33003300
  1241. CH00 0210:-
  1242. ECT: S00000000, E33003300
  1243. CH00 0244:-
  1244. ECT: S00000000, E33003300
  1245. CH00 0278:-
  1246. ECT: S00000000, E33003300
  1247. CH00 0312:-
  1248. ECT: S00000000, E33003300
  1249. CH00 0346:-
  1250. ECT: S00000000, E33003300
  1251. CH00 0380:-
  1252. ECT: S00000000, E33003300
  1253. CH00 0414:-
  1254. ECT: S00000000, E33003300
  1255. CH00 0414:-
  1256. ECT: S00000000, E33003300
  1257. CH00 0380:-
  1258. ECT: S00000000, E33003300
  1259. CH00 0346:-
  1260. ECT: S00000000, E33003300
  1261. CH00 0312:-
  1262. ECT: S00000000, E33003300
  1263. CH00 0278:-
  1264. ECT: S00000000, E33003300
  1265. CH00 0244:-
  1266. ECT: S00000000, E33003300
  1267. CH00 0210:-
  1268. ECT: S00000000, E33003300
  1269. CH00 0176:-
  1270. ECT: S00000000, E33003300
  1271. CH00 0142:-
  1272. Control value 242
  1273. S00K0
  1274. ECT: S00000000, E33003300
  1275. CH00 0142:-
  1276. ECT: S00000000, E33003300
  1277. CH00 0176:-
  1278. ECT: S00000000, E33003300
  1279. CH00 0210:-
  1280. ECT: S00000000, E33003300
  1281. CH00 0244:-
  1282. ECT: S00000000, E33003300
  1283. CH00 0278:-
  1284. ECT: S00000000, E33003300
  1285. CH00 0312:-
  1286. ECT: S00000000, E33003300
  1287. CH00 0346:-
  1288. ECT: S00000000, E33003300
  1289. CH00 0380:-
  1290. ECT: S00000000, E33003300
  1291. CH00 0414:-
  1292. ECT: S00000000, E33003300
  1293. CH00 0414:-
  1294. ECT: S00000000, E33003300
  1295. CH00 0380:-
  1296. ECT: S00000000, E33003300
  1297. CH00 0346:-
  1298. ECT: S00000000, E33003300
  1299. CH00 0312:-
  1300. ECT: S00000000, E33003300
  1301. CH00 0278:-
  1302. ECT: S00000000, E33003300
  1303. CH00 0244:-
  1304. ECT: S00000000, E33003300
  1305. CH00 0210:-
  1306. ECT: S00000000, E33003300
  1307. CH00 0176:-
  1308. ECT: S00000000, E33003300
  1309. CH00 0142:-
  1310. Control value 276
  1311. S00K0
  1312. ECT: S00000000, E33003300
  1313. CH00 0142:-
  1314. ECT: S00000000, E33003300
  1315. CH00 0176:-
  1316. ECT: S00000000, E33003300
  1317. CH00 0210:-
  1318. ECT: S00000000, E33003300
  1319. CH00 0244:-
  1320. ECT: S00000000, E33003300
  1321. CH00 0278:-
  1322. ECT: S00000000, E33003300
  1323. CH00 0312:-
  1324. ECT: S00000000, E33003300
  1325. CH00 0346:-
  1326. ECT: S00000000, E33003300
  1327. CH00 0380:-
  1328. ECT: S00000000, E33003300
  1329. CH00 0414:-
  1330. ECT: S00000000, E33003300
  1331. CH00 0414:-
  1332. ECT: S00000000, E33003300
  1333. CH00 0380:-
  1334. ECT: S00000000, E33003300
  1335. CH00 0346:-
  1336. ECT: S00000000, E33003300
  1337. CH00 0312:-
  1338. ECT: S00000000, E33003300
  1339. CH00 0278:-
  1340. ECT: S00000000, E33003300
  1341. CH00 0244:-
  1342. ECT: S00000000, E33003300
  1343. CH00 0210:-
  1344. ECT: S00000000, E33003300
  1345. CH00 0176:-
  1346. ECT: S00000000, E33003300
  1347. CH00 0142:-
  1348. Control value 310
  1349. S00K0
  1350. ECT: S00000000, E33003300
  1351. CH00 0142:-
  1352. ECT: S00000000, E33003300
  1353. CH00 0176:-
  1354. ECT: S00000000, E33003300
  1355. CH00 0210:-
  1356. ECT: S00000000, E33003300
  1357. CH00 0244:-
  1358. ECT: S00000000, E33003300
  1359. CH00 0278:-
  1360. ECT: S00000000, E33003300
  1361. CH00 0312:-
  1362. ECT: S00000000, E33003300
  1363. CH00 0346:-
  1364. ECT: S00000000, E33003300
  1365. CH00 0380:-
  1366. ECT: S00000000, E33003300
  1367. CH00 0414:-
  1368. ECT: S00000000, E33003300
  1369. CH00 0414:-
  1370. ECT: S00000000, E33003300
  1371. CH00 0380:-
  1372. ECT: S00000000, E33003300
  1373. CH00 0346:-
  1374. ECT: S00000000, E33003300
  1375. CH00 0312:-
  1376. ECT: S00000000, E33003300
  1377. CH00 0278:-
  1378. ECT: S00000000, E33003300
  1379. CH00 0244:-
  1380. ECT: S00000000, E33003300
  1381. CH00 0210:-
  1382. ECT: S00000000, E33003300
  1383. CH00 0176:-
  1384. ECT: S00000000, E33003300
  1385. CH00 0142:-
  1386. Control value 344
  1387. S00K0
  1388. ECT: S00000000, E33003300
  1389. CH00 0142:-
  1390. ECT: S00000000, E33003300
  1391. CH00 0176:-
  1392. ECT: S00000000, E33003300
  1393. CH00 0210:-
  1394. ECT: S00000000, E33003300
  1395. CH00 0244:-
  1396. ECT: S00000000, E33003300
  1397. CH00 0278:-
  1398. ECT: S00000000, E33003300
  1399. CH00 0312:-
  1400. ECT: S00000000, E33003300
  1401. CH00 0346:-
  1402. ECT: S00000000, E33003300
  1403. CH00 0380:-
  1404. ECT: S00000000, E33003300
  1405. CH00 0414:-
  1406. ECT: S00000000, E33003300
  1407. CH00 0414:-
  1408. ECT: S00000000, E33003300
  1409. CH00 0380:-
  1410. ECT: S00000000, E33003300
  1411. CH00 0346:-
  1412. ECT: S00000000, E33003300
  1413. CH00 0312:-
  1414. ECT: S00000000, E33003300
  1415. CH00 0278:-
  1416. ECT: S00000000, E33003300
  1417. CH00 0244:-
  1418. ECT: S00000000, E33003300
  1419. CH00 0210:-
  1420. ECT: S00000000, E33003300
  1421. CH00 0176:-
  1422. ECT: S00000000, E33003300
  1423. CH00 0142:-
  1424. Control value 378
  1425. S00K0
  1426. ECT: S00000000, E33003300
  1427. CH00 0142:-
  1428. ECT: S00000000, E33003300
  1429. CH00 0176:-
  1430. ECT: S00000000, E33003300
  1431. CH00 0210:-
  1432. ECT: S00000000, E33003300
  1433. CH00 0244:-
  1434. ECT: S00000000, E33003300
  1435. CH00 0278:-
  1436. ECT: S00000000, E33003300
  1437. CH00 0312:-
  1438. ECT: S00000000, E33003300
  1439. CH00 0346:-
  1440. ECT: S00000000, E33003300
  1441. CH00 0380:-
  1442. ECT: S00000000, E33003300
  1443. CH00 0414:-
  1444. ECT: S00000000, E33003300
  1445. CH00 0414:-
  1446. ECT: S00000000, E33003300
  1447. CH00 0380:-
  1448. ECT: S00000000, E33003300
  1449. CH00 0346:-
  1450. ECT: S00000000, E33003300
  1451. CH00 0312:-
  1452. ECT: S00000000, E33003300
  1453. CH00 0278:-
  1454. ECT: S00000000, E33003300
  1455. CH00 0244:-
  1456. ECT: S00000000, E33003300
  1457. CH00 0210:-
  1458. ECT: S00000000, E33003300
  1459. CH00 0176:-
  1460. ECT: S00000000, E33003300
  1461. CH00 0142:-
  1462. Control value 412
  1463. S00K0
  1464. ECT: S00000000, E33003300
  1465. CH00 0142:-
  1466. ECT: S00000000, E33003300
  1467. CH00 0176:-
  1468. ECT: S00000000, E33003300
  1469. CH00 0210:-
  1470. ECT: S00000000, E33003300
  1471. CH00 0244:-
  1472. ECT: S00000000, E33003300
  1473. CH00 0278:-
  1474. ECT: S00000000, E33003300
  1475. CH00 0312:-
  1476. ECT: S00000000, E33003300
  1477. CH00 0346:-
  1478. ECT: S00000000, E33003300
  1479. CH00 0380:-
  1480. ECT: S00000000, E33003300
  1481. CH00 0414:-
  1482. ECT: S00000000, E33003300
  1483. CH00 0414:-
  1484. ECT: S00000000, E33003300
  1485. CH00 0380:-
  1486. ECT: S00000000, E33003300
  1487. CH00 0346:-
  1488. ECT: S00000000, E33003300
  1489. CH00 0312:-
  1490. ECT: S00000000, E33003300
  1491. CH00 0278:-
  1492. ECT: S00000000, E33003300
  1493. CH00 0244:-
  1494. ECT: S00000000, E33003300
  1495. CH00 0210:-
  1496. ECT: S00000000, E33003300
  1497. CH00 0176:-
  1498. ECT: S00000000, E33003300
  1499. CH00 0142:-
  1500. ERROR: Highest Value found is a 0
  1501. Final solution Rank 1 = 0, 0, Final control is 140, Final command is 142
  1502. Won't run on disabled channels
  1503. EarlyCommandTraining
  1504. Xls OffsetPushout: 2
  1505. SMIP OffsetPushout: 0
  1506. No additional Pushouts requested.
  1507. Channel 1, Rank 0
  1508. Control value 140
  1509. S00K0
  1510. ECT: S3F000300, E33003300
  1511. CH01 0142:-
  1512. ECT: S3C000300, E33003300
  1513. CH01 0176:-
  1514. ECT: S3C000300, E33003300
  1515. CH01 0210:-
  1516. ECT: S3C001C00, E33003300
  1517. CH01 0244:-
  1518. ECT: S3C001C00, E33003300
  1519. CH01 0278:-
  1520. ECT: S3C001C00, E33003300
  1521. CH01 0312:-
  1522. ECT: S3C001C00, E33003300
  1523. CH01 0346:-
  1524. ECT: S3C000300, E33003300
  1525. CH01 0380:-
  1526. ECT: S3F001C00, E33003300
  1527. CH01 0414:-
  1528. ECT: S3F001300, E33003300
  1529. CH01 0414:-
  1530. ECT: S3C001C00, E33003300
  1531. CH01 0380:-
  1532. ECT: S3C001C00, E33003300
  1533. CH01 0346:-
  1534. ECT: S3C000300, E33003300
  1535. CH01 0312:-
  1536. ECT: S3C001C00, E33003300
  1537. CH01 0278:-
  1538. ECT: S3C001C00, E33003300
  1539. CH01 0244:-
  1540. ECT: S3C000300, E33003300
  1541. CH01 0210:-
  1542. ECT: S3C000300, E33003300
  1543. CH01 0176:-
  1544. ECT: S3F000300, E33003300
  1545. CH01 0142:-
  1546. Control value 174
  1547. S00K0
  1548. ECT: S3F001F00, E33003300
  1549. CH01 0142:-
  1550. ECT: S3C001C00, E33003300
  1551. CH01 0176:-
  1552. ECT: S3C001C00, E33003300
  1553. CH01 0210:-
  1554. ECT: S3C001C00, E33003300
  1555. CH01 0244:-
  1556. ECT: S3C001C00, E33003300
  1557. CH01 0278:-
  1558. ECT: S3C001C00, E33003300
  1559. CH01 0312:-
  1560. ECT: S3C001C00, E33003300
  1561. CH01 0346:-
  1562. ECT: S3C001C00, E33003300
  1563. CH01 0380:-
  1564. ECT: S3F000E00, E33003300
  1565. CH01 0414:-
  1566. ECT: S3F000E00, E33003300
  1567. CH01 0414:-
  1568. ECT: S3C001C00, E33003300
  1569. CH01 0380:-
  1570. ECT: S3C001C00, E33003300
  1571. CH01 0346:-
  1572. ECT: S3C001C00, E33003300
  1573. CH01 0312:-
  1574. ECT: S3C001C00, E33003300
  1575. CH01 0278:-
  1576. ECT: S3C001C00, E33003300
  1577. CH01 0244:-
  1578. ECT: S3C001C00, E33003300
  1579. CH01 0210:-
  1580. ECT: S3C001C00, E33003300
  1581. CH01 0176:-
  1582. ECT: S3F001F00, E33003300
  1583. CH01 0142:-
  1584. Control value 208
  1585. S00K0
  1586. ECT: S3F001F00, E33003300
  1587. CH01 0142:-
  1588. ECT: S3C001C00, E33003300
  1589. CH01 0176:-
  1590. ECT: S3C001C00, E33003300
  1591. CH01 0210:-
  1592. ECT: S3C001C00, E33003300
  1593. CH01 0244:-
  1594. ECT: S3C001C00, E33003300
  1595. CH01 0278:-
  1596. ECT: S3C001C00, E33003300
  1597. CH01 0312:-
  1598. ECT: S3C001C00, E33003300
  1599. CH01 0346:-
  1600. ECT: S3C001C00, E33003300
  1601. CH01 0380:-
  1602. ECT: S03000300, E33003300
  1603. CH01 0414:-
  1604. ECT: S3F000E00, E33003300
  1605. CH01 0414:-
  1606. ECT: S3C001C00, E33003300
  1607. CH01 0380:-
  1608. ECT: S3C001C00, E33003300
  1609. CH01 0346:-
  1610. ECT: S3C001C00, E33003300
  1611. CH01 0312:-
  1612. ECT: S3C001C00, E33003300
  1613. CH01 0278:-
  1614. ECT: S3C001C00, E33003300
  1615. CH01 0244:-
  1616. ECT: S3C001C00, E33003300
  1617. CH01 0210:-
  1618. ECT: S3C001C00, E33003300
  1619. CH01 0176:-
  1620. ECT: S3F001F00, E33003300
  1621. CH01 0142:-
  1622. Control value 242
  1623. S00K0
  1624. ECT: S3F001F00, E33003300
  1625. CH01 0142:-
  1626. ECT: S3C001C00, E33003300
  1627. CH01 0176:-
  1628. ECT: S3C001C00, E33003300
  1629. CH01 0210:-
  1630. ECT: S3C001C00, E33003300
  1631. CH01 0244:-
  1632. ECT: S3C001C00, E33003300
  1633. CH01 0278:-
  1634. ECT: S3C001C00, E33003300
  1635. CH01 0312:-
  1636. ECT: S3C001C00, E33003300
  1637. CH01 0346:-
  1638. ECT: S3C001C00, E33003300
  1639. CH01 0380:-
  1640. ECT: S3F000E00, E33003300
  1641. CH01 0414:-
  1642. ECT: S3F000C00, E33003300
  1643. CH01 0414:-
  1644. ECT: S3C001C00, E33003300
  1645. CH01 0380:-
  1646. ECT: S3C001C00, E33003300
  1647. CH01 0346:-
  1648. ECT: S3C001C00, E33003300
  1649. CH01 0312:-
  1650. ECT: S3C001C00, E33003300
  1651. CH01 0278:-
  1652. ECT: S3C001C00, E33003300
  1653. CH01 0244:-
  1654. ECT: S3C001C00, E33003300
  1655. CH01 0210:-
  1656. ECT: S3C001C00, E33003300
  1657. CH01 0176:-
  1658. ECT: S3F001F00, E33003300
  1659. CH01 0142:-
  1660. Control value 276
  1661. S00K0
  1662. ECT: S3F001F00, E33003300
  1663. CH01 0142:-
  1664. ECT: S3C001C00, E33003300
  1665. CH01 0176:-
  1666. ECT: S3C001C00, E33003300
  1667. CH01 0210:-
  1668. ECT: S3C001C00, E33003300
  1669. CH01 0244:-
  1670. ECT: S3C001C00, E33003300
  1671. CH01 0278:-
  1672. ECT: S3C001C00, E33003300
  1673. CH01 0312:-
  1674. ECT: S3C001C00, E33003300
  1675. CH01 0346:-
  1676. ECT: S3C001C00, E33003300
  1677. CH01 0380:-
  1678. ECT: S3F000E00, E33003300
  1679. CH01 0414:-
  1680. ECT: S3F000E00, E33003300
  1681. CH01 0414:-
  1682. ECT: S3C001C00, E33003300
  1683. CH01 0380:-
  1684. ECT: S3C001C00, E33003300
  1685. CH01 0346:-
  1686. ECT: S3C001C00, E33003300
  1687. CH01 0312:-
  1688. ECT: S3C001C00, E33003300
  1689. CH01 0278:-
  1690. ECT: S3C001C00, E33003300
  1691. CH01 0244:-
  1692. ECT: S3C001C00, E33003300
  1693. CH01 0210:-
  1694. ECT: S3C001C00, E33003300
  1695. CH01 0176:-
  1696. ECT: S3F001F00, E33003300
  1697. CH01 0142:-
  1698. Control value 310
  1699. S00K0
  1700. ECT: S3F001F00, E33003300
  1701. CH01 0142:-
  1702. ECT: S3C001C00, E33003300
  1703. CH01 0176:-
  1704. ECT: S3C001C00, E33003300
  1705. CH01 0210:-
  1706. ECT: S3C001C00, E33003300
  1707. CH01 0244:-
  1708. ECT: S3C001C00, E33003300
  1709. CH01 0278:-
  1710. ECT: S3C001C00, E33003300
  1711. CH01 0312:-
  1712. ECT: S3C001C00, E33003300
  1713. CH01 0346:-
  1714. ECT: S3C001C00, E33003300
  1715. CH01 0380:-
  1716. ECT: S3F000E00, E33003300
  1717. CH01 0414:-
  1718. ECT: S3F000E00, E33003300
  1719. CH01 0414:-
  1720. ECT: S3C001C00, E33003300
  1721. CH01 0380:-
  1722. ECT: S3C001C00, E33003300
  1723. CH01 0346:-
  1724. ECT: S3C001C00, E33003300
  1725. CH01 0312:-
  1726. ECT: S3C001C00, E33003300
  1727. CH01 0278:-
  1728. ECT: S3C001C00, E33003300
  1729. CH01 0244:-
  1730. ECT: S3C001C00, E33003300
  1731. CH01 0210:-
  1732. ECT: S3C001C00, E33003300
  1733. CH01 0176:-
  1734. ECT: S3F001F00, E33003300
  1735. CH01 0142:-
  1736. Control value 344
  1737. S00K0
  1738. ECT: S3F001F00, E33003300
  1739. CH01 0142:-
  1740. ECT: S3C001C00, E33003300
  1741. CH01 0176:-
  1742. ECT: S3C001C00, E33003300
  1743. CH01 0210:-
  1744. ECT: S3C001C00, E33003300
  1745. CH01 0244:-
  1746. ECT: S3C001C00, E33003300
  1747. CH01 0278:-
  1748. ECT: S3C001C00, E33003300
  1749. CH01 0312:-
  1750. ECT: S3C001C00, E33003300
  1751. CH01 0346:-
  1752. ECT: S3C001C00, E33003300
  1753. CH01 0380:-
  1754. ECT: S3F000E00, E33003300
  1755. CH01 0414:-
  1756. ECT: S3F000E00, E33003300
  1757. CH01 0414:-
  1758. ECT: S3C001C00, E33003300
  1759. CH01 0380:-
  1760. ECT: S3C001C00, E33003300
  1761. CH01 0346:-
  1762. ECT: S3C001C00, E33003300
  1763. CH01 0312:-
  1764. ECT: S3C001C00, E33003300
  1765. CH01 0278:-
  1766. ECT: S3C001C00, E33003300
  1767. CH01 0244:-
  1768. ECT: S3C001C00, E33003300
  1769. CH01 0210:-
  1770. ECT: S3C001C00, E33003300
  1771. CH01 0176:-
  1772. ECT: S3F001F00, E33003300
  1773. CH01 0142:-
  1774. Control value 378
  1775. S00K0
  1776. ECT: S3F001F00, E33003300
  1777. CH01 0142:-
  1778. ECT: S3C001C00, E33003300
  1779. CH01 0176:-
  1780. ECT: S3C001C00, E33003300
  1781. CH01 0210:-
  1782. ECT: S3C001C00, E33003300
  1783. CH01 0244:-
  1784. ECT: S3C001C00, E33003300
  1785. CH01 0278:-
  1786. ECT: S3C001C00, E33003300
  1787. CH01 0312:-
  1788. ECT: S3C001C00, E33003300
  1789. CH01 0346:-
  1790. ECT: S3C001C00, E33003300
  1791. CH01 0380:-
  1792. ECT: S3F000E00, E33003300
  1793. CH01 0414:-
  1794. ECT: S3F000E00, E33003300
  1795. CH01 0414:-
  1796. ECT: S3C001C00, E33003300
  1797. CH01 0380:-
  1798. ECT: S3C001C00, E33003300
  1799. CH01 0346:-
  1800. ECT: S3C001C00, E33003300
  1801. CH01 0312:-
  1802. ECT: S3C001C00, E33003300
  1803. CH01 0278:-
  1804. ECT: S3C001C00, E33003300
  1805. CH01 0244:-
  1806. ECT: S3C001C00, E33003300
  1807. CH01 0210:-
  1808. ECT: S3C001C00, E33003300
  1809. CH01 0176:-
  1810. ECT: S3F001B00, E33003300
  1811. CH01 0142:-
  1812. Control value 412
  1813. S00K0
  1814. ECT: S03000000, E33003300
  1815. CH01 0142:-
  1816. ECT: S03000300, E33003300
  1817. CH01 0176:-
  1818. ECT: S03000300, E33003300
  1819. CH01 0210:-
  1820. ECT: S03000300, E33003300
  1821. CH01 0244:-
  1822. ECT: S03000300, E33003300
  1823. CH01 0278:-
  1824. ECT: S03000300, E33003300
  1825. CH01 0312:-
  1826. ECT: S03000300, E33003300
  1827. CH01 0346:-
  1828. ECT: S03000300, E33003300
  1829. CH01 0380:-
  1830. ECT: S3F000300, E33003300
  1831. CH01 0414:-
  1832. ECT: S3F000300, E33003300
  1833. CH01 0414:-
  1834. ECT: S03000300, E33003300
  1835. CH01 0380:-
  1836. ECT: S03000300, E33003300
  1837. CH01 0346:-
  1838. ECT: S03000300, E33003300
  1839. CH01 0312:-
  1840. ECT: S3F000300, E33003300
  1841. CH01 0278:-
  1842. ECT: S03000300, E33003300
  1843. CH01 0244:-
  1844. ECT: S03000300, E33003300
  1845. CH01 0210:-
  1846. ECT: S03000300, E33003300
  1847. CH01 0176:-
  1848. ECT: S03000000, E33003300
  1849. CH01 0142:-
  1850. ERROR: Highest Value found is a 0
  1851. Final solution Rank 0 = 0, 0, Channel 1, Rank 1
  1852. Control value 140
  1853. S00K0
  1854. ECT: S00000000, E33003300
  1855. CH01 0142:-
  1856. ECT: S00000000, E33003300
  1857. CH01 0176:-
  1858. ECT: S00000000, E33003300
  1859. CH01 0210:-
  1860. ECT: S00000000, E33003300
  1861. CH01 0244:-
  1862. ECT: S00000000, E33003300
  1863. CH01 0278:-
  1864. ECT: S00000000, E33003300
  1865. CH01 0312:-
  1866. ECT: S00000000, E33003300
  1867. CH01 0346:-
  1868. ECT: S00000000, E33003300
  1869. CH01 0380:-
  1870. ECT: S00000000, E33003300
  1871. CH01 0414:-
  1872. ECT: S00000000, E33003300
  1873. CH01 0414:-
  1874. ECT: S00000000, E33003300
  1875. CH01 0380:-
  1876. ECT: S00000000, E33003300
  1877. CH01 0346:-
  1878. ECT: S00000000, E33003300
  1879. CH01 0312:-
  1880. ECT: S00000000, E33003300
  1881. CH01 0278:-
  1882. ECT: S00000000, E33003300
  1883. CH01 0244:-
  1884. ECT: S00000000, E33003300
  1885. CH01 0210:-
  1886. ECT: S00000000, E33003300
  1887. CH01 0176:-
  1888. ECT: S00000000, E33003300
  1889. CH01 0142:-
  1890. Control value 174
  1891. S00K0
  1892. ECT: S00000000, E33003300
  1893. CH01 0142:-
  1894. ECT: S00000000, E33003300
  1895. CH01 0176:-
  1896. ECT: S00000000, E33003300
  1897. CH01 0210:-
  1898. ECT: S00000000, E33003300
  1899. CH01 0244:-
  1900. ECT: S00000000, E33003300
  1901. CH01 0278:-
  1902. ECT: S00000000, E33003300
  1903. CH01 0312:-
  1904. ECT: S00000000, E33003300
  1905. CH01 0346:-
  1906. ECT: S00000000, E33003300
  1907. CH01 0380:-
  1908. ECT: S00000000, E33003300
  1909. CH01 0414:-
  1910. ECT: S00000000, E33003300
  1911. CH01 0414:-
  1912. ECT: S00000000, E33003300
  1913. CH01 0380:-
  1914. ECT: S00000000, E33003300
  1915. CH01 0346:-
  1916. ECT: S00000000, E33003300
  1917. CH01 0312:-
  1918. ECT: S00000000, E33003300
  1919. CH01 0278:-
  1920. ECT: S00000000, E33003300
  1921. CH01 0244:-
  1922. ECT: S00000000, E33003300
  1923. CH01 0210:-
  1924. ECT: S00000000, E33003300
  1925. CH01 0176:-
  1926. ECT: S00000000, E33003300
  1927. CH01 0142:-
  1928. Control value 208
  1929. S00K0
  1930. ECT: S00000000, E33003300
  1931. CH01 0142:-
  1932. ECT: S00000000, E33003300
  1933. CH01 0176:-
  1934. ECT: S00000000, E33003300
  1935. CH01 0210:-
  1936. ECT: S00000000, E33003300
  1937. CH01 0244:-
  1938. ECT: S00000000, E33003300
  1939. CH01 0278:-
  1940. ECT: S00000000, E33003300
  1941. CH01 0312:-
  1942. ECT: S00000000, E33003300
  1943. CH01 0346:-
  1944. ECT: S00000000, E33003300
  1945. CH01 0380:-
  1946. ECT: S00000000, E33003300
  1947. CH01 0414:-
  1948. ECT: S00000000, E33003300
  1949. CH01 0414:-
  1950. ECT: S00000000, E33003300
  1951. CH01 0380:-
  1952. ECT: S00000000, E33003300
  1953. CH01 0346:-
  1954. ECT: S00000000, E33003300
  1955. CH01 0312:-
  1956. ECT: S00000000, E33003300
  1957. CH01 0278:-
  1958. ECT: S00000000, E33003300
  1959. CH01 0244:-
  1960. ECT: S00000000, E33003300
  1961. CH01 0210:-
  1962. ECT: S00000000, E33003300
  1963. CH01 0176:-
  1964. ECT: S00000000, E33003300
  1965. CH01 0142:-
  1966. Control value 242
  1967. S00K0
  1968. ECT: S00000000, E33003300
  1969. CH01 0142:-
  1970. ECT: S00000000, E33003300
  1971. CH01 0176:-
  1972. ECT: S00000000, E33003300
  1973. CH01 0210:-
  1974. ECT: S00000000, E33003300
  1975. CH01 0244:-
  1976. ECT: S00000000, E33003300
  1977. CH01 0278:-
  1978. ECT: S00000000, E33003300
  1979. CH01 0312:-
  1980. ECT: S00000000, E33003300
  1981. CH01 0346:-
  1982. ECT: S00000000, E33003300
  1983. CH01 0380:-
  1984. ECT: S00000000, E33003300
  1985. CH01 0414:-
  1986. ECT: S00000000, E33003300
  1987. CH01 0414:-
  1988. ECT: S00000000, E33003300
  1989. CH01 0380:-
  1990. ECT: S00000000, E33003300
  1991. CH01 0346:-
  1992. ECT: S00000000, E33003300
  1993. CH01 0312:-
  1994. ECT: S00000000, E33003300
  1995. CH01 0278:-
  1996. ECT: S00000000, E33003300
  1997. CH01 0244:-
  1998. ECT: S00000000, E33003300
  1999. CH01 0210:-
  2000. ECT: S00000000, E33003300
  2001. CH01 0176:-
  2002. ECT: S00000000, E33003300
  2003. CH01 0142:-
  2004. Control value 276
  2005. S00K0
  2006. ECT: S00000000, E33003300
  2007. CH01 0142:-
  2008. ECT: S00000000, E33003300
  2009. CH01 0176:-
  2010. ECT: S00000000, E33003300
  2011. CH01 0210:-
  2012. ECT: S00000000, E33003300
  2013. CH01 0244:-
  2014. ECT: S00000000, E33003300
  2015. CH01 0278:-
  2016. ECT: S00000000, E33003300
  2017. CH01 0312:-
  2018. ECT: S00000000, E33003300
  2019. CH01 0346:-
  2020. ECT: S00000000, E33003300
  2021. CH01 0380:-
  2022. ECT: S00000000, E33003300
  2023. CH01 0414:-
  2024. ECT: S00000000, E33003300
  2025. CH01 0414:-
  2026. ECT: S00000000, E33003300
  2027. CH01 0380:-
  2028. ECT: S00000000, E33003300
  2029. CH01 0346:-
  2030. ECT: S00000000, E33003300
  2031. CH01 0312:-
  2032. ECT: S00000000, E33003300
  2033. CH01 0278:-
  2034. ECT: S00000000, E33003300
  2035. CH01 0244:-
  2036. ECT: S00000000, E33003300
  2037. CH01 0210:-
  2038. ECT: S00000000, E33003300
  2039. CH01 0176:-
  2040. ECT: S00000000, E33003300
  2041. CH01 0142:-
  2042. Control value 310
  2043. S00K0
  2044. ECT: S00000000, E33003300
  2045. CH01 0142:-
  2046. ECT: S00000000, E33003300
  2047. CH01 0176:-
  2048. ECT: S00000000, E33003300
  2049. CH01 0210:-
  2050. ECT: S00000000, E33003300
  2051. CH01 0244:-
  2052. ECT: S00000000, E33003300
  2053. CH01 0278:-
  2054. ECT: S00000000, E33003300
  2055. CH01 0312:-
  2056. ECT: S00000000, E33003300
  2057. CH01 0346:-
  2058. ECT: S00000000, E33003300
  2059. CH01 0380:-
  2060. ECT: S00000000, E33003300
  2061. CH01 0414:-
  2062. ECT: S00000000, E33003300
  2063. CH01 0414:-
  2064. ECT: S00000000, E33003300
  2065. CH01 0380:-
  2066. ECT: S00000000, E33003300
  2067. CH01 0346:-
  2068. ECT: S00000000, E33003300
  2069. CH01 0312:-
  2070. ECT: S00000000, E33003300
  2071. CH01 0278:-
  2072. ECT: S00000000, E33003300
  2073. CH01 0244:-
  2074. ECT: S00000000, E33003300
  2075. CH01 0210:-
  2076. ECT: S00000000, E33003300
  2077. CH01 0176:-
  2078. ECT: S00000000, E33003300
  2079. CH01 0142:-
  2080. Control value 344
  2081. S00K0
  2082. ECT: S00000000, E33003300
  2083. CH01 0142:-
  2084. ECT: S00000000, E33003300
  2085. CH01 0176:-
  2086. ECT: S00000000, E33003300
  2087. CH01 0210:-
  2088. ECT: S00000000, E33003300
  2089. CH01 0244:-
  2090. ECT: S00000000, E33003300
  2091. CH01 0278:-
  2092. ECT: S00000000, E33003300
  2093. CH01 0312:-
  2094. ECT: S00000000, E33003300
  2095. CH01 0346:-
  2096. ECT: S00000000, E33003300
  2097. CH01 0380:-
  2098. ECT: S00000000, E33003300
  2099. CH01 0414:-
  2100. ECT: S00000000, E33003300
  2101. CH01 0414:-
  2102. ECT: S00000000, E33003300
  2103. CH01 0380:-
  2104. ECT: S00000000, E33003300
  2105. CH01 0346:-
  2106. ECT: S00000000, E33003300
  2107. CH01 0312:-
  2108. ECT: S00000000, E33003300
  2109. CH01 0278:-
  2110. ECT: S00000000, E33003300
  2111. CH01 0244:-
  2112. ECT: S00000000, E33003300
  2113. CH01 0210:-
  2114. ECT: S00000000, E33003300
  2115. CH01 0176:-
  2116. ECT: S00000000, E33003300
  2117. CH01 0142:-
  2118. Control value 378
  2119. S00K0
  2120. ECT: S00000000, E33003300
  2121. CH01 0142:-
  2122. ECT: S00000000, E33003300
  2123. CH01 0176:-
  2124. ECT: S00000000, E33003300
  2125. CH01 0210:-
  2126. ECT: S00000000, E33003300
  2127. CH01 0244:-
  2128. ECT: S00000000, E33003300
  2129. CH01 0278:-
  2130. ECT: S00000000, E33003300
  2131. CH01 0312:-
  2132. ECT: S00000000, E33003300
  2133. CH01 0346:-
  2134. ECT: S00000000, E33003300
  2135. CH01 0380:-
  2136. ECT: S00000000, E33003300
  2137. CH01 0414:-
  2138. ECT: S00000000, E33003300
  2139. CH01 0414:-
  2140. ECT: S00000000, E33003300
  2141. CH01 0380:-
  2142. ECT: S00000000, E33003300
  2143. CH01 0346:-
  2144. ECT: S00000000, E33003300
  2145. CH01 0312:-
  2146. ECT: S00000000, E33003300
  2147. CH01 0278:-
  2148. ECT: S00000000, E33003300
  2149. CH01 0244:-
  2150. ECT: S00000000, E33003300
  2151. CH01 0210:-
  2152. ECT: S00000000, E33003300
  2153. CH01 0176:-
  2154. ECT: S00000000, E33003300
  2155. CH01 0142:-
  2156. Control value 412
  2157. S00K0
  2158. ECT: S00000000, E33003300
  2159. CH01 0142:-
  2160. ECT: S00000000, E33003300
  2161. CH01 0176:-
  2162. ECT: S00000000, E33003300
  2163. CH01 0210:-
  2164. ECT: S00000000, E33003300
  2165. CH01 0244:-
  2166. ECT: S00000000, E33003300
  2167. CH01 0278:-
  2168. ECT: S00000000, E33003300
  2169. CH01 0312:-
  2170. ECT: S00000000, E33003300
  2171. CH01 0346:-
  2172. ECT: S00000000, E33003300
  2173. CH01 0380:-
  2174. ECT: S00000000, E33003300
  2175. CH01 0414:-
  2176. ECT: S00000000, E33003300
  2177. CH01 0414:-
  2178. ECT: S00000000, E33003300
  2179. CH01 0380:-
  2180. ECT: S00000000, E33003300
  2181. CH01 0346:-
  2182. ECT: S00000000, E33003300
  2183. CH01 0312:-
  2184. ECT: S00000000, E33003300
  2185. CH01 0278:-
  2186. ECT: S00000000, E33003300
  2187. CH01 0244:-
  2188. ECT: S00000000, E33003300
  2189. CH01 0210:-
  2190. ECT: S00000000, E33003300
  2191. CH01 0176:-
  2192. ECT: S00000000, E33003300
  2193. CH01 0142:-
  2194. ERROR: Highest Value found is a 0
  2195. Final solution Rank 1 = 0, 0, Final control is 140, Final command is 142
  2196. CP 56
  2197. Won't run on disabled channels
  2198. Lp4CBTExitAllRanks
  2199. Won't run on disabled channels
  2200. Lp4CBTExitAllRanks
  2201. CP B2
  2202. CompleteJedecInit
  2203. DRAM Resetting
  2204. Set Boot Freq:3 Speed set to:3
  2205. MAXPI State = MAXPI_INIT
  2206. Ecc Disabled
  2207. setting dq_finec=0
  2208. setting ccc_finec=0
  2209. A0 Offset 0
  2210. CH0 Limits
  2211. Fine Hard: 0x2A - 0xB0
  2212. Mux : 0xD - 0x1A
  2213. Coarse : 0x4 - 0xF
  2214. Fine Soft: 0x30 - 0xA0
  2215. WarmBoot: Muxcode=22
  2216. MAXPI State = MAXPI_FINAL_VALUES
  2217. MAXPI_FINAL_VALUES: MrcData->HalfClkPi = 0xB8(725 ps Estimate) FullRangePi = 0xB8(725 ps Estimate)
  2218. MAXPI_FINAL_VALUES: Muxcode = 0x16
  2219. dq_90:0x2D 180:0x5B 270:0x89 ccc_90:0x2D 180:0x5B 270:0x89 dq_rxdll_rxmuxsel:0x1C
  2220. ccc_rxdll_rxmuxsel:0x1C
  2221. db1:0x16, db2:0x2D, db3:0x44 db4:0x5B, db5:0x72, db6:0x89, db7:0xA0
  2222. setting dq_finec=1
  2223. setting ccc_finec=1
  2224. CH0 Limits
  2225. Fine Hard: 0x2A - 0xB0
  2226. Mux : 0x16 - 0x16
  2227. Coarse : 0x4 - 0xF
  2228. Fine Soft: 0x30 - 0xA0
  2229. DQ_CH_ERR_STAT 0x00000001
  2230. DQ_CODE_STAT 0x00167764
  2231. CH 0:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:100 ctlebias=5
  2232. CCC0_CH_ERR_STAT 0x00000001
  2233. CCC0_CODE_STAT 0x00167769
  2234. CCC0_CH 0:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:105
  2235. DQ_CH_ERR_STAT 0x00000001
  2236. DQ_CODE_STAT 0x00167769
  2237. CH 0:DQ 1:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:7 Coarsei:7 Fine:105 ctlebias=5
  2238. CH1 Limits
  2239. Fine Hard: 0x2A - 0xB0
  2240. Mux : 0x16 - 0x16
  2241. Coarse : 0x4 - 0xF
  2242. Fine Soft: 0x0 - 0x0
  2243. DQ_CH_ERR_STAT 0x00000001
  2244. DQ_CODE_STAT 0x00166685
  2245. CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:133 ctlebias=4
  2246. CCC1_CH_ERR_STAT 0x00000001
  2247. CCC1_CODE_STAT 0x00166687
  2248. CCC1_CH 1:DQ 0:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:135
  2249. DQ_CH_ERR_STAT 0x00000001
  2250. DQ_CODE_STAT 0x00166681
  2251. CH 1:DQ 1:RK 0:Val 0x00000016:Max 0x00000016 Err:0 Coarse:6 Coarsei:6 Fine:129 ctlebias=4
  2252. Ch 0:fbclktrim:0xF
  2253. Ch 1:fbclktrim:0x1F
  2254. DefaultCmdClkCtl=1
  2255. DefaultCmdClkCtl=1
  2256. DefaultCmdClkCtl=1
  2257. DefaultCmdClkCtl=1
  2258. Speed set to:5
  2259. TimingParam nWR = 24, MR1 = 36046
  2260. FBPath - Ch0 Rk0 TxVref: 00000000
  2261. FBPath - Ch0 Rk1 TxVref: 00000000
  2262. Speed set to:5
  2263. MAXPI State = MAXPI_INIT
  2264. Ecc Disabled
  2265. setting dq_finec=0
  2266. setting ccc_finec=0
  2267. A0 Offset 0
  2268. CH0 Limits
  2269. Fine Hard: 0x2A - 0xB0
  2270. Mux : 0xA - 0x14
  2271. Coarse : 0x4 - 0xF
  2272. Fine Soft: 0x30 - 0xA0
  2273. WarmBoot: Muxcode=16
  2274. MAXPI State = MAXPI_FINAL_VALUES
  2275. MAXPI_FINAL_VALUES: MrcData->HalfClkPi = 0x88(725 ps Estimate) FullRangePi = 0x88(725 ps Estimate)
  2276. MAXPI_FINAL_VALUES: Muxcode = 0x10
  2277. dq_90:0x21 180:0x43 270:0x65 ccc_90:0x21 180:0x43 270:0x65 dq_rxdll_rxmuxsel:0x15
  2278. ccc_rxdll_rxmuxsel:0x15
  2279. db1:0x10, db2:0x21, db3:0x32 db4:0x43, db5:0x54, db6:0x65, db7:0x76
  2280. setting dq_finec=1
  2281. setting ccc_finec=1
  2282. CH0 Limits
  2283. Fine Hard: 0x2A - 0xB0
  2284. Mux : 0x10 - 0x10
  2285. Coarse : 0x4 - 0xF
  2286. Fine Soft: 0x30 - 0xA0
  2287. DQ_CH_ERR_STAT 0x00000001
  2288. DQ_CODE_STAT 0x00106698
  2289. CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:152 ctlebias=4
  2290. CCC0_CH_ERR_STAT 0x00000001
  2291. CCC0_CODE_STAT 0x00107769
  2292. CCC0_CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:105
  2293. DQ_CH_ERR_STAT 0x00000001
  2294. DQ_CODE_STAT 0x0010668B
  2295. CH 0:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:139 ctlebias=4
  2296. CH1 Limits
  2297. Fine Hard: 0x2A - 0xB0
  2298. Mux : 0x10 - 0x10
  2299. Coarse : 0x4 - 0xF
  2300. Fine Soft: 0x0 - 0x0
  2301. DQ_CH_ERR_STAT 0x00000001
  2302. DQ_CODE_STAT 0x00106685
  2303. CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:133 ctlebias=4
  2304. CCC1_CH_ERR_STAT 0x00000001
  2305. CCC1_CODE_STAT 0x00106686
  2306. CCC1_CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:134
  2307. DQ_CH_ERR_STAT 0x00000001
  2308. DQ_CODE_STAT 0x0010667B
  2309. CH 1:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:123 ctlebias=4
  2310. Ch 0:fbclktrim:0xF
  2311. Ch 1:fbclktrim:0x1F
  2312. DefaultCmdClkCtl=0
  2313. DefaultCmdClkCtl=0
  2314. DefaultCmdClkCtl=0
  2315. DefaultCmdClkCtl=0
  2316. Speed set to:5
  2317. TimingParam nWR = 24, MR1 = 36046
  2318. FBPath - Ch1 Rk0 TxVref: 00000000
  2319. FBPath - Ch1 Rk1 TxVref: 00000000
  2320. Speed set to:5
  2321. MAXPI State = MAXPI_INIT
  2322. Ecc Disabled
  2323. setting dq_finec=0
  2324. setting ccc_finec=0
  2325. A0 Offset 0
  2326. CH0 Limits
  2327. Fine Hard: 0x2A - 0xB0
  2328. Mux : 0xA - 0x14
  2329. Coarse : 0x4 - 0xF
  2330. Fine Soft: 0x30 - 0xA0
  2331. WarmBoot: Muxcode=16
  2332. MAXPI State = MAXPI_FINAL_VALUES
  2333. MAXPI_FINAL_VALUES: MrcData->HalfClkPi = 0x88(725 ps Estimate) FullRangePi = 0x88(725 ps Estimate)
  2334. MAXPI_FINAL_VALUES: Muxcode = 0x10
  2335. dq_90:0x21 180:0x43 270:0x65 ccc_90:0x21 180:0x43 270:0x65 dq_rxdll_rxmuxsel:0x15
  2336. ccc_rxdll_rxmuxsel:0x15
  2337. db1:0x10, db2:0x21, db3:0x32 db4:0x43, db5:0x54, db6:0x65, db7:0x76
  2338. setting dq_finec=1
  2339. setting ccc_finec=1
  2340. CH0 Limits
  2341. Fine Hard: 0x2A - 0xB0
  2342. Mux : 0x10 - 0x10
  2343. Coarse : 0x4 - 0xF
  2344. Fine Soft: 0x30 - 0xA0
  2345. DQ_CH_ERR_STAT 0x00000001
  2346. DQ_CODE_STAT 0x00107769
  2347. CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:105 ctlebias=5
  2348. CCC0_CH_ERR_STAT 0x00000001
  2349. CCC0_CODE_STAT 0x0010776F
  2350. CCC0_CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:111
  2351. DQ_CH_ERR_STAT 0x00000001
  2352. DQ_CODE_STAT 0x0010668F
  2353. CH 0:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:143 ctlebias=4
  2354. CH1 Limits
  2355. Fine Hard: 0x2A - 0xB0
  2356. Mux : 0x10 - 0x10
  2357. Coarse : 0x4 - 0xF
  2358. Fine Soft: 0x0 - 0x0
  2359. DQ_CH_ERR_STAT 0x00000001
  2360. DQ_CODE_STAT 0x00106685
  2361. CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:133 ctlebias=4
  2362. CCC1_CH_ERR_STAT 0x00000001
  2363. CCC1_CODE_STAT 0x00106685
  2364. CCC1_CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:133
  2365. DQ_CH_ERR_STAT 0x00000001
  2366. DQ_CODE_STAT 0x0010667B
  2367. CH 1:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:123 ctlebias=4
  2368. Ch 0:fbclktrim:0xF
  2369. Ch 1:fbclktrim:0x1F
  2370. DefaultCmdClkCtl=0
  2371. DefaultCmdClkCtl=0
  2372. DefaultCmdClkCtl=0
  2373. DefaultCmdClkCtl=0
  2374. Speed set to:5
  2375. MAXPI State = MAXPI_INIT
  2376. Ecc Disabled
  2377. setting dq_finec=0
  2378. setting ccc_finec=0
  2379. A0 Offset 0
  2380. CH0 Limits
  2381. Fine Hard: 0x2A - 0xB0
  2382. Mux : 0xA - 0x14
  2383. Coarse : 0x4 - 0xF
  2384. Fine Soft: 0x30 - 0xA0
  2385. WarmBoot: Muxcode=16
  2386. MAXPI State = MAXPI_FINAL_VALUES
  2387. MAXPI_FINAL_VALUES: MrcData->HalfClkPi = 0x88(725 ps Estimate) FullRangePi = 0x88(725 ps Estimate)
  2388. MAXPI_FINAL_VALUES: Muxcode = 0x10
  2389. dq_90:0x21 180:0x43 270:0x65 ccc_90:0x21 180:0x43 270:0x65 dq_rxdll_rxmuxsel:0x15
  2390. ccc_rxdll_rxmuxsel:0x15
  2391. db1:0x10, db2:0x21, db3:0x32 db4:0x43, db5:0x54, db6:0x65, db7:0x76
  2392. setting dq_finec=1
  2393. setting ccc_finec=1
  2394. CH0 Limits
  2395. Fine Hard: 0x2A - 0xB0
  2396. Mux : 0x10 - 0x10
  2397. Coarse : 0x4 - 0xF
  2398. Fine Soft: 0x30 - 0xA0
  2399. DQ_CH_ERR_STAT 0x00000001
  2400. DQ_CODE_STAT 0x00107769
  2401. CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:105 ctlebias=5
  2402. CCC0_CH_ERR_STAT 0x00000001
  2403. CCC0_CODE_STAT 0x0010776F
  2404. CCC0_CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:111
  2405. DQ_CH_ERR_STAT 0x00000001
  2406. DQ_CODE_STAT 0x00106694
  2407. CH 0:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:148 ctlebias=4
  2408. CH1 Limits
  2409. Fine Hard: 0x2A - 0xB0
  2410. Mux : 0x10 - 0x10
  2411. Coarse : 0x4 - 0xF
  2412. Fine Soft: 0x0 - 0x0
  2413. DQ_CH_ERR_STAT 0x00000001
  2414. DQ_CODE_STAT 0x00106685
  2415. CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:133 ctlebias=4
  2416. CCC1_CH_ERR_STAT 0x00000001
  2417. CCC1_CODE_STAT 0x00106680
  2418. CCC1_CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:128
  2419. DQ_CH_ERR_STAT 0x00000001
  2420. DQ_CODE_STAT 0x0010667F
  2421. CH 1:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:127 ctlebias=4
  2422. Ch 0:fbclktrim:0xF
  2423. Ch 1:fbclktrim:0x1F
  2424. DefaultCmdClkCtl=0
  2425. DefaultCmdClkCtl=0
  2426. DefaultCmdClkCtl=0
  2427. DefaultCmdClkCtl=0
  2428. Speed set to:5
  2429. MAXPI State = MAXPI_INIT
  2430. Ecc Disabled
  2431. setting dq_finec=0
  2432. setting ccc_finec=0
  2433. A0 Offset 0
  2434. CH0 Limits
  2435. Fine Hard: 0x2A - 0xB0
  2436. Mux : 0xA - 0x14
  2437. Coarse : 0x4 - 0xF
  2438. Fine Soft: 0x30 - 0xA0
  2439. WarmBoot: Muxcode=16
  2440. MAXPI State = MAXPI_FINAL_VALUES
  2441. MAXPI_FINAL_VALUES: MrcData->HalfClkPi = 0x88(725 ps Estimate) FullRangePi = 0x88(725 ps Estimate)
  2442. MAXPI_FINAL_VALUES: Muxcode = 0x10
  2443. dq_90:0x21 180:0x43 270:0x65 ccc_90:0x21 180:0x43 270:0x65 dq_rxdll_rxmuxsel:0x15
  2444. ccc_rxdll_rxmuxsel:0x15
  2445. db1:0x10, db2:0x21, db3:0x32 db4:0x43, db5:0x54, db6:0x65, db7:0x76
  2446. setting dq_finec=1
  2447. setting ccc_finec=1
  2448. CH0 Limits
  2449. Fine Hard: 0x2A - 0xB0
  2450. Mux : 0x10 - 0x10
  2451. Coarse : 0x4 - 0xF
  2452. Fine Soft: 0x30 - 0xA0
  2453. DQ_CH_ERR_STAT 0x00000001
  2454. DQ_CODE_STAT 0x0010776A
  2455. CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:106 ctlebias=5
  2456. CCC0_CH_ERR_STAT 0x00000001
  2457. CCC0_CODE_STAT 0x0010776B
  2458. CCC0_CH 0:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:7 Coarsei:7 Fine:107
  2459. DQ_CH_ERR_STAT 0x00000001
  2460. DQ_CODE_STAT 0x0010669F
  2461. CH 0:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:159 ctlebias=4
  2462. CH1 Limits
  2463. Fine Hard: 0x2A - 0xB0
  2464. Mux : 0x10 - 0x10
  2465. Coarse : 0x4 - 0xF
  2466. Fine Soft: 0x0 - 0x0
  2467. DQ_CH_ERR_STAT 0x00000001
  2468. DQ_CODE_STAT 0x00106680
  2469. CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:128 ctlebias=4
  2470. CCC1_CH_ERR_STAT 0x00000001
  2471. CCC1_CODE_STAT 0x00106685
  2472. CCC1_CH 1:DQ 0:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:133
  2473. DQ_CH_ERR_STAT 0x00000001
  2474. DQ_CODE_STAT 0x0010667B
  2475. CH 1:DQ 1:RK 0:Val 0x00000010:Max 0x00000010 Err:0 Coarse:6 Coarsei:6 Fine:123 ctlebias=4
  2476. Ch 0:fbclktrim:0xF
  2477. Ch 1:fbclktrim:0x1F
  2478. DefaultCmdClkCtl=0
  2479. DefaultCmdClkCtl=0
  2480. DefaultCmdClkCtl=0
  2481. DefaultCmdClkCtl=0
  2482. CP 69
  2483. Won't run on disabled channels
  2484. Won't run on disabled channels
  2485. CP 6A
  2486. Won't run on disabled channels
  2487. DiffAmpOverride_AstepOnly
  2488. Won't run on disabled channels
  2489. DiffAmpOverride_AstepOnly
  2490. CP A5
  2491. Won't run on disabled channels
  2492. ReceiveEnable
  2493. C00R0
  2494. Initial Delay Value=1768
  2495. Detect Rising Edge Large, Step=25, dithering=0
  2496. S00K0 S01K0 S02K0 S03K0
  2497. CH00 1768:- 1768:P 1768:- 1768:-
  2498. CH00 1793:- 1743:P 1793:- 1793:-
  2499. CH00 1818:- 1718:P 1818:- 1818:-
  2500. CH00 1843:- 1693:P 1843:- 1843:-
  2501. CH00 1868:- 1668:P 1868:P 1868:-
  2502. CH00 1893:- 1643:- 1868:P 1893:P
  2503. CH00 1918:P 1668:- 1868:P 1893:P
  2504. Ch00 1918:1918:P 1668:1668:P 1868:1868:P 1893:1893:P
  2505. Detect Rising Edge Medium, Step=5, dithering=0
  2506. S00K0 S01K0 S02K0 S03K0
  2507. CH00 1918:P 1668:P 1868:P 1893:P
  2508. CH00 1913:P 1663:- 1863:P 1888:P
  2509. CH00 1908:P 1668:- 1858:P 1883:P
  2510. CH00 1903:- 1668:- 1853:- 1878:P
  2511. CH00 1908:- 1668:- 1858:- 1873:P
  2512. CH00 1908:- 1668:- 1858:- 1868:-
  2513. Ch00 1908:1908:P 1668:1668:P 1858:1858:P 1873:1873:P
  2514. Detect Rising Edge Small, Step=1, dithering=5
  2515. S00K0 S01K0 S02K0 S03K0
  2516. CH00 1908:P 1668:P 1858:P 1873:-
  2517. CH00 1907:P 1667:P 1857:P 1874:P
  2518. CH00 1906:P 1666:- 1856:P 1875:P
  2519. CH00 1905:P 1668:P 1855:- 1876:P
  2520. CH00 1904:P 1669:P 1857:P 1877:P
  2521. CH00 1903:- 1670:P 1858:P 1878:P
  2522. CH00 1905:P 1671:P 1859:P 1879:P
  2523. CH00 1906:P 1672:P 1860:P 1874:P
  2524. CH00 1907:P 1667:P 1861:P 1874:P
  2525. CH00 1908:P 1667:P 1856:P 1874:P
  2526. CH00 1909:P 1667:P 1856:P 1874:P
  2527. Ch00 1904:1904:P 1667:1667:P 1856:1856:P 1874:1874:P
  2528. Add 1/4 Clk Value+=68
  2529. Step back clks to find first strobe, Step=272, dithering=0
  2530. S00K0 S01K0 S02K0 S03K0
  2531. CH00 1972:P 1735:P 1924:P 1942:P
  2532. CH00 1700:P 1463:P 1652:P 1670:P
  2533. CH00 1428:P 1191:P 1380:P 1398:P
  2534. CH00 1156:P 0919:- 1108:P 1126:P
  2535. CH00 0884:- 1191:- 0836:- 0854:-
  2536. Ch00 1156:1156:P 1191:1191:P 1108:1108:P 1126:1126:P
  2537. Find first rising edge medium, Step=5, dithering=0
  2538. S00K0 S01K0 S02K0 S03K0
  2539. CH00 1156:P 1191:P 1108:P 1126:P
  2540. CH00 1151:P 1186:P 1103:P 1121:P
  2541. CH00 1146:P 1181:P 1098:P 1116:P
  2542. CH00 1141:P 1176:P 1093:P 1111:P
  2543. CH00 1136:P 1171:P 1088:P 1106:P
  2544. CH00 1131:P 1166:P 1083:P 1101:P
  2545. CH00 1126:P 1161:P 1078:P 1096:P
  2546. CH00 1121:P 1156:P 1073:P 1091:P
  2547. CH00 1116:P 1151:P 1068:P 1086:P
  2548. CH00 1111:P 1146:P 1063:P 1081:P
  2549. CH00 1106:P 1141:P 1058:P 1076:P
  2550. CH00 1101:P 1136:P 1053:P 1071:P
  2551. CH00 1096:P 1131:P 1048:- 1066:P
  2552. CH00 1091:P 1126:P 1053:- 1061:-
  2553. CH00 1086:- 1121:- 1053:- 1066:-
  2554. Ch00 1091:1091:P 1126:1126:P 1053:1053:P 1066:1066:P
  2555. Find first rising edge small, Step=1, dithering=5
  2556. S00K0 S01K0 S02K0 S03K0
  2557. CH00 1091:P 1126:P 1053:P 1066:P
  2558. CH00 1090:P 1125:P 1052:P 1065:P
  2559. CH00 1089:- 1124:P 1051:P 1064:P
  2560. CH00 1091:- 1123:- 1050:P 1063:-
  2561. CH00 1092:P 1125:- 1049:P 1065:P
  2562. CH00 1093:P 1126:- 1048:- 1066:P
  2563. CH00 1094:P 1127:P 1050:P 1067:P
  2564. CH00 1095:P 1128:P 1051:P 1068:P
  2565. CH00 1096:P 1129:P 1052:P 1069:P
  2566. CH00 1097:P 1130:P 1053:P 1064:P
  2567. CH00 1092:P 1131:P 1054:P 1064:P
  2568. CH00 1092:P 1132:P 1049:P 1064:P
  2569. Ch00 1092:1092:P 1127:1127:P 1049:1049:P 1064:1064:P
  2570. C00R1
  2571. Initial Delay Value=1768
  2572. Detect Rising Edge Large, Step=25, dithering=0
  2573. S00K0 S01K0 S02K0 S03K0
  2574. CH00 1768:- 1768:- 1768:- 1768:-
  2575. CH00 1793:- 1793:- 1793:- 1793:-
  2576. CH00 1818:- 1818:- 1818:- 1818:-
  2577. CH00 1843:- 1843:- 1843:- 1843:-
  2578. CH00 1868:- 1868:- 1868:- 1868:-
  2579. CH00 1893:- 1893:- 1893:- 1893:-
  2580. CH00 1918:- 1918:- 1918:- 1918:-
  2581. CH00 1943:- 1943:- 1943:- 1943:-
  2582. CH00 1968:- 1968:- 1968:- 1968:-
  2583. CH00 1993:- 1993:- 1993:- 1993:-
  2584. CH00 2018:- 2018:- 2018:- 2018:-
  2585. CH00 2043:- 2043:- 2043:- 2043:-
  2586. CH00 2068:- 2068:- 2068:- 2068:-
  2587. CH00 2093:- 2093:- 2093:- 2093:-
  2588. CH00 2118:- 2118:- 2118:- 2118:-
  2589. CH00 2143:- 2143:- 2143:- 2143:-
  2590. CH00 2168:- 2168:- 2168:- 2168:-
  2591. 0x10 > limit of 0xF for RecEnDelay_dq. Returning STATUS_LIMIT
  2592.  
  2593. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2594. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2595. ClkCh0 00 00 00 00 -- 01 09 - 3 - 1 -- 0281
  2596. ClkCh0 00 00 01 00 -- 01 09 - 3 - 1 -- 0281
  2597. ClkCh0 00 00 02 00 -- 01 09 - 3 - 1 -- 0281
  2598. ClkCh0 00 00 03 00 -- 01 09 - 3 - 1 -- 0281
  2599. ClkCh0 00 01 00 00 -- 01 09 - 3 - 1 -- 0281
  2600. ClkCh0 00 01 01 00 -- 01 09 - 3 - 1 -- 0281
  2601. ClkCh0 00 01 02 00 -- 01 09 - 3 - 1 -- 0281
  2602. ClkCh0 00 01 03 00 -- 01 09 - 3 - 1 -- 0281
  2603.  
  2604. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2605. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2606. ClkCh1 00 00 00 00 -- 01 09 - 3 - 1 -- 0281
  2607. ClkCh1 00 00 01 00 -- 01 09 - 3 - 1 -- 0281
  2608. ClkCh1 00 00 02 00 -- 01 09 - 3 - 1 -- 0281
  2609. ClkCh1 00 00 03 00 -- 01 09 - 3 - 1 -- 0281
  2610. ClkCh1 00 01 00 00 -- 01 09 - 3 - 1 -- 0281
  2611. ClkCh1 00 01 01 00 -- 01 09 - 3 - 1 -- 0281
  2612. ClkCh1 00 01 02 00 -- 01 09 - 3 - 1 -- 0281
  2613. ClkCh1 00 01 03 00 -- 01 09 - 3 - 1 -- 0281
  2614.  
  2615. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2616. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2617. CmdCh0 00 00 00 00 -- 00 06 - 3 - 0 -- 0142
  2618. CmdCh0 00 00 01 00 -- 00 06 - 3 - 0 -- 0142
  2619. CmdCh0 00 00 02 00 -- 00 06 - 3 - 0 -- 0142
  2620. CmdCh0 00 00 03 00 -- 00 06 - 3 - 0 -- 0142
  2621. CmdCh0 00 01 00 00 -- 00 06 - 3 - 0 -- 0142
  2622. CmdCh0 00 01 01 00 -- 00 06 - 3 - 0 -- 0142
  2623. CmdCh0 00 01 02 00 -- 00 06 - 3 - 0 -- 0142
  2624. CmdCh0 00 01 03 00 -- 00 06 - 3 - 0 -- 0142
  2625.  
  2626. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2627. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2628. CmdCh1 00 00 00 00 -- 00 06 - 3 - 0 -- 0142
  2629. CmdCh1 00 00 01 00 -- 00 06 - 3 - 0 -- 0142
  2630. CmdCh1 00 00 02 00 -- 00 06 - 3 - 0 -- 0142
  2631. CmdCh1 00 00 03 00 -- 00 06 - 3 - 0 -- 0142
  2632. CmdCh1 00 01 00 00 -- 00 06 - 3 - 0 -- 0142
  2633. CmdCh1 00 01 01 00 -- 00 06 - 3 - 0 -- 0142
  2634. CmdCh1 00 01 02 00 -- 00 06 - 3 - 0 -- 0142
  2635. CmdCh1 00 01 03 00 -- 00 06 - 3 - 0 -- 0142
  2636.  
  2637. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2638. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2639. CtlCh0 00 00 00 00 -- 00 04 - 3 - 0 -- 0140
  2640. CtlCh0 00 00 01 00 -- 00 04 - 3 - 0 -- 0140
  2641. CtlCh0 00 00 02 00 -- 00 04 - 3 - 0 -- 0140
  2642. CtlCh0 00 00 03 00 -- 00 04 - 3 - 0 -- 0140
  2643. CtlCh0 00 01 00 00 -- 00 04 - 3 - 0 -- 0140
  2644. CtlCh0 00 01 01 00 -- 00 04 - 3 - 0 -- 0140
  2645. CtlCh0 00 01 02 00 -- 00 04 - 3 - 0 -- 0140
  2646. CtlCh0 00 01 03 00 -- 00 04 - 3 - 0 -- 0140
  2647.  
  2648. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2649. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2650. CtlCh1 00 00 00 00 -- 00 04 - 3 - 0 -- 0140
  2651. CtlCh1 00 00 01 00 -- 00 04 - 3 - 0 -- 0140
  2652. CtlCh1 00 00 02 00 -- 00 04 - 3 - 0 -- 0140
  2653. CtlCh1 00 00 03 00 -- 00 04 - 3 - 0 -- 0140
  2654. CtlCh1 00 01 00 00 -- 00 04 - 3 - 0 -- 0140
  2655. CtlCh1 00 01 01 00 -- 00 04 - 3 - 0 -- 0140
  2656. CtlCh1 00 01 02 00 -- 00 04 - 3 - 0 -- 0140
  2657. CtlCh1 00 01 03 00 -- 00 04 - 3 - 0 -- 0140
  2658.  
  2659. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2660. -------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2661. RxDqsNDelay_dq 00 00 00 00 -- -- 47 - - - - -- 0047
  2662. RxDqsNDelay_dq 00 00 01 00 -- -- 47 - - - - -- 0047
  2663. RxDqsNDelay_dq 00 00 02 00 -- -- 47 - - - - -- 0047
  2664. RxDqsNDelay_dq 00 00 03 00 -- -- 47 - - - - -- 0047
  2665. RxDqsNDelay_dq 00 01 00 00 -- -- 49 - - - - -- 0049
  2666. RxDqsNDelay_dq 00 01 01 00 -- -- 49 - - - - -- 0049
  2667. RxDqsNDelay_dq 00 01 02 00 -- -- 49 - - - - -- 0049
  2668. RxDqsNDelay_dq 00 01 03 00 -- -- 49 - - - - -- 0049
  2669.  
  2670. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2671. -------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2672. RxDqsPDelay_dq 00 00 00 00 -- -- 47 - - - - -- 0047
  2673. RxDqsPDelay_dq 00 00 01 00 -- -- 47 - - - - -- 0047
  2674. RxDqsPDelay_dq 00 00 02 00 -- -- 47 - - - - -- 0047
  2675. RxDqsPDelay_dq 00 00 03 00 -- -- 47 - - - - -- 0047
  2676. RxDqsPDelay_dq 00 01 00 00 -- -- 49 - - - - -- 0049
  2677. RxDqsPDelay_dq 00 01 01 00 -- -- 49 - - - - -- 0049
  2678. RxDqsPDelay_dq 00 01 02 00 -- -- 49 - - - - -- 0049
  2679. RxDqsPDelay_dq 00 01 03 00 -- -- 49 - - - - -- 0049
  2680.  
  2681. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2682. ---------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2683. TxDqDelay_Actual 00 00 00 00 14 03 51 - 0 - 3 -- 0595
  2684. TxDqDelay_Actual 00 00 01 00 14 03 51 - 0 - 3 -- 0595
  2685. TxDqDelay_Actual 00 00 02 00 14 03 51 - 0 - 3 -- 0595
  2686. TxDqDelay_Actual 00 00 03 00 14 03 51 - 0 - 3 -- 0595
  2687. TxDqDelay_Actual 00 01 00 00 14 03 55 - 0 - 3 -- 0599
  2688. TxDqDelay_Actual 00 01 01 00 14 03 55 - 0 - 3 -- 0599
  2689. TxDqDelay_Actual 00 01 02 00 14 03 55 - 0 - 3 -- 0599
  2690. TxDqDelay_Actual 00 01 03 00 14 03 55 - 0 - 3 -- 0599
  2691.  
  2692. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2693. --------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2694. TxDqDrive 00 00 00 00 14 01 51 - 3 - 1 -- 0323
  2695. TxDqDrive 00 00 01 00 14 01 51 - 3 - 1 -- 0323
  2696. TxDqDrive 00 00 02 00 14 01 51 - 3 - 1 -- 0323
  2697. TxDqDrive 00 00 03 00 14 01 51 - 3 - 1 -- 0323
  2698. TxDqDrive 00 01 00 00 14 01 55 - 3 - 1 -- 0327
  2699. TxDqDrive 00 01 01 00 14 01 55 - 3 - 1 -- 0327
  2700. TxDqDrive 00 01 02 00 14 01 55 - 3 - 1 -- 0327
  2701. TxDqDrive 00 01 03 00 14 01 55 - 3 - 1 -- 0327
  2702.  
  2703. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2704. ------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2705. TxDqsDelay_dq 00 00 00 00 14 01 04 - 3 - 1 -- 0276
  2706. TxDqsDelay_dq 00 00 01 00 14 01 04 - 3 - 1 -- 0276
  2707. TxDqsDelay_dq 00 00 02 00 14 01 04 - 3 - 1 -- 0276
  2708. TxDqsDelay_dq 00 00 03 00 14 01 04 - 3 - 1 -- 0276
  2709. TxDqsDelay_dq 00 01 00 00 14 01 07 - 3 - 1 -- 0279
  2710. TxDqsDelay_dq 00 01 01 00 14 01 07 - 3 - 1 -- 0279
  2711. TxDqsDelay_dq 00 01 02 00 14 01 07 - 3 - 1 -- 0279
  2712. TxDqsDelay_dq 00 01 03 00 14 01 07 - 3 - 1 -- 0279
  2713.  
  2714. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2715. ------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2716. RecEnDelay_dq 00 00 00 00 17 15 128 - 2 - 15 -- 2168
  2717. RecEnDelay_dq 00 00 01 00 17 15 128 - 2 - 15 -- 2168
  2718. RecEnDelay_dq 00 00 02 00 17 15 128 - 2 - 15 -- 2168
  2719. RecEnDelay_dq 00 00 03 00 17 15 128 - 2 - 15 -- 2168
  2720. RecEnDelay_dq 00 01 00 00 17 15 128 - 2 - 15 -- 2168
  2721. RecEnDelay_dq 00 01 01 00 17 15 128 - 2 - 15 -- 2168
  2722. RecEnDelay_dq 00 01 02 00 17 15 128 - 2 - 15 -- 2168
  2723. RecEnDelay_dq 00 01 03 00 17 15 128 - 2 - 15 -- 2168
  2724.  
  2725. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2726. -------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2727. RecEnPiCode_dq 00 00 00 00 -- -- 128 - - - - -- 0128
  2728. RecEnPiCode_dq 00 00 01 00 -- -- 128 - - - - -- 0128
  2729. RecEnPiCode_dq 00 00 02 00 -- -- 128 - - - - -- 0128
  2730. RecEnPiCode_dq 00 00 03 00 -- -- 128 - - - - -- 0128
  2731. RecEnPiCode_dq 00 01 00 00 -- -- 128 - - - - -- 0128
  2732. RecEnPiCode_dq 00 01 01 00 -- -- 128 - - - - -- 0128
  2733. RecEnPiCode_dq 00 01 02 00 -- -- 128 - - - - -- 0128
  2734. RecEnPiCode_dq 00 01 03 00 -- -- 128 - - - - -- 0128
  2735.  
  2736. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2737. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2738. ClkCh0 01 00 00 00 -- -1 -1 - -1 - -1 -- -001
  2739. ClkCh0 01 00 01 00 -- -1 -1 - -1 - -1 -- -001
  2740. ClkCh0 01 00 02 00 -- -1 -1 - -1 - -1 -- -001
  2741. ClkCh0 01 00 03 00 -- -1 -1 - -1 - -1 -- -001
  2742. ClkCh0 01 01 00 00 -- -1 -1 - -1 - -1 -- -001
  2743. ClkCh0 01 01 01 00 -- -1 -1 - -1 - -1 -- -001
  2744. ClkCh0 01 01 02 00 -- -1 -1 - -1 - -1 -- -001
  2745. ClkCh0 01 01 03 00 -- -1 -1 - -1 - -1 -- -001
  2746.  
  2747. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2748. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2749. ClkCh1 01 00 00 00 -- -1 -1 - -1 - -1 -- -001
  2750. ClkCh1 01 00 01 00 -- -1 -1 - -1 - -1 -- -001
  2751. ClkCh1 01 00 02 00 -- -1 -1 - -1 - -1 -- -001
  2752. ClkCh1 01 00 03 00 -- -1 -1 - -1 - -1 -- -001
  2753. ClkCh1 01 01 00 00 -- -1 -1 - -1 - -1 -- -001
  2754. ClkCh1 01 01 01 00 -- -1 -1 - -1 - -1 -- -001
  2755. ClkCh1 01 01 02 00 -- -1 -1 - -1 - -1 -- -001
  2756. ClkCh1 01 01 03 00 -- -1 -1 - -1 - -1 -- -001
  2757.  
  2758. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2759. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2760. CmdCh0 01 00 00 00 -- -1 -1 - -1 - -1 -- -001
  2761. CmdCh0 01 00 01 00 -- -1 -1 - -1 - -1 -- -001
  2762. CmdCh0 01 00 02 00 -- -1 -1 - -1 - -1 -- -001
  2763. CmdCh0 01 00 03 00 -- -1 -1 - -1 - -1 -- -001
  2764. CmdCh0 01 01 00 00 -- -1 -1 - -1 - -1 -- -001
  2765. CmdCh0 01 01 01 00 -- -1 -1 - -1 - -1 -- -001
  2766. CmdCh0 01 01 02 00 -- -1 -1 - -1 - -1 -- -001
  2767. CmdCh0 01 01 03 00 -- -1 -1 - -1 - -1 -- -001
  2768.  
  2769. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2770. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2771. CmdCh1 01 00 00 00 -- -1 -1 - -1 - -1 -- -001
  2772. CmdCh1 01 00 01 00 -- -1 -1 - -1 - -1 -- -001
  2773. CmdCh1 01 00 02 00 -- -1 -1 - -1 - -1 -- -001
  2774. CmdCh1 01 00 03 00 -- -1 -1 - -1 - -1 -- -001
  2775. CmdCh1 01 01 00 00 -- -1 -1 - -1 - -1 -- -001
  2776. CmdCh1 01 01 01 00 -- -1 -1 - -1 - -1 -- -001
  2777. CmdCh1 01 01 02 00 -- -1 -1 - -1 - -1 -- -001
  2778. CmdCh1 01 01 03 00 -- -1 -1 - -1 - -1 -- -001
  2779.  
  2780. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2781. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2782. CtlCh0 01 00 00 00 -- -1 -1 - -1 - -1 -- -001
  2783. CtlCh0 01 00 01 00 -- -1 -1 - -1 - -1 -- -001
  2784. CtlCh0 01 00 02 00 -- -1 -1 - -1 - -1 -- -001
  2785. CtlCh0 01 00 03 00 -- -1 -1 - -1 - -1 -- -001
  2786. CtlCh0 01 01 00 00 -- -1 -1 - -1 - -1 -- -001
  2787. CtlCh0 01 01 01 00 -- -1 -1 - -1 - -1 -- -001
  2788. CtlCh0 01 01 02 00 -- -1 -1 - -1 - -1 -- -001
  2789. CtlCh0 01 01 03 00 -- -1 -1 - -1 - -1 -- -001
  2790.  
  2791. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2792. ------ -- -- -- -- --- --- --- - --- --- --- ---- ----
  2793. CtlCh1 01 00 00 00 -- -1 -1 - -1 - -1 -- -001
  2794. CtlCh1 01 00 01 00 -- -1 -1 - -1 - -1 -- -001
  2795. CtlCh1 01 00 02 00 -- -1 -1 - -1 - -1 -- -001
  2796. CtlCh1 01 00 03 00 -- -1 -1 - -1 - -1 -- -001
  2797. CtlCh1 01 01 00 00 -- -1 -1 - -1 - -1 -- -001
  2798. CtlCh1 01 01 01 00 -- -1 -1 - -1 - -1 -- -001
  2799. CtlCh1 01 01 02 00 -- -1 -1 - -1 - -1 -- -001
  2800. CtlCh1 01 01 03 00 -- -1 -1 - -1 - -1 -- -001
  2801.  
  2802. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2803. -------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2804. RxDqsNDelay_dq 01 00 00 00 -- -- 47 - - - - -- 0047
  2805. RxDqsNDelay_dq 01 00 01 00 -- -- 47 - - - - -- 0047
  2806. RxDqsNDelay_dq 01 00 02 00 -- -- 47 - - - - -- 0047
  2807. RxDqsNDelay_dq 01 00 03 00 -- -- 47 - - - - -- 0047
  2808. RxDqsNDelay_dq 01 01 00 00 -- -- 49 - - - - -- 0049
  2809. RxDqsNDelay_dq 01 01 01 00 -- -- 49 - - - - -- 0049
  2810. RxDqsNDelay_dq 01 01 02 00 -- -- 49 - - - - -- 0049
  2811. RxDqsNDelay_dq 01 01 03 00 -- -- 49 - - - - -- 0049
  2812.  
  2813. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2814. -------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2815. RxDqsPDelay_dq 01 00 00 00 -- -- 47 - - - - -- 0047
  2816. RxDqsPDelay_dq 01 00 01 00 -- -- 47 - - - - -- 0047
  2817. RxDqsPDelay_dq 01 00 02 00 -- -- 47 - - - - -- 0047
  2818. RxDqsPDelay_dq 01 00 03 00 -- -- 47 - - - - -- 0047
  2819. RxDqsPDelay_dq 01 01 00 00 -- -- 49 - - - - -- 0049
  2820. RxDqsPDelay_dq 01 01 01 00 -- -- 49 - - - - -- 0049
  2821. RxDqsPDelay_dq 01 01 02 00 -- -- 49 - - - - -- 0049
  2822. RxDqsPDelay_dq 01 01 03 00 -- -- 49 - - - - -- 0049
  2823.  
  2824. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2825. ---------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2826. TxDqDelay_Actual 01 00 00 00 14 03 51 - 0 - 3 -- 0595
  2827. TxDqDelay_Actual 01 00 01 00 14 03 51 - 0 - 3 -- 0595
  2828. TxDqDelay_Actual 01 00 02 00 14 03 51 - 0 - 3 -- 0595
  2829. TxDqDelay_Actual 01 00 03 00 14 03 51 - 0 - 3 -- 0595
  2830. TxDqDelay_Actual 01 01 00 00 14 03 55 - 0 - 3 -- 0599
  2831. TxDqDelay_Actual 01 01 01 00 14 03 55 - 0 - 3 -- 0599
  2832. TxDqDelay_Actual 01 01 02 00 14 03 55 - 0 - 3 -- 0599
  2833. TxDqDelay_Actual 01 01 03 00 14 03 55 - 0 - 3 -- 0599
  2834.  
  2835. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2836. --------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2837. TxDqDrive 01 00 00 00 14 01 51 - 3 - 1 -- 0323
  2838. TxDqDrive 01 00 01 00 14 01 51 - 3 - 1 -- 0323
  2839. TxDqDrive 01 00 02 00 14 01 51 - 3 - 1 -- 0323
  2840. TxDqDrive 01 00 03 00 14 01 51 - 3 - 1 -- 0323
  2841. TxDqDrive 01 01 00 00 14 01 55 - 3 - 1 -- 0327
  2842. TxDqDrive 01 01 01 00 14 01 55 - 3 - 1 -- 0327
  2843. TxDqDrive 01 01 02 00 14 01 55 - 3 - 1 -- 0327
  2844. TxDqDrive 01 01 03 00 14 01 55 - 3 - 1 -- 0327
  2845.  
  2846. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2847. ------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2848. TxDqsDelay_dq 01 00 00 00 14 01 04 - 3 - 1 -- 0276
  2849. TxDqsDelay_dq 01 00 01 00 14 01 04 - 3 - 1 -- 0276
  2850. TxDqsDelay_dq 01 00 02 00 14 01 04 - 3 - 1 -- 0276
  2851. TxDqsDelay_dq 01 00 03 00 14 01 04 - 3 - 1 -- 0276
  2852. TxDqsDelay_dq 01 01 00 00 14 01 07 - 3 - 1 -- 0279
  2853. TxDqsDelay_dq 01 01 01 00 14 01 07 - 3 - 1 -- 0279
  2854. TxDqsDelay_dq 01 01 02 00 14 01 07 - 3 - 1 -- 0279
  2855. TxDqsDelay_dq 01 01 03 00 14 01 07 - 3 - 1 -- 0279
  2856.  
  2857. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2858. ------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2859. RecEnDelay_dq 01 00 00 00 17 01 01 - 3 - 1 -- 0273
  2860. RecEnDelay_dq 01 00 01 00 17 01 01 - 3 - 1 -- 0273
  2861. RecEnDelay_dq 01 00 02 00 17 01 01 - 3 - 1 -- 0273
  2862. RecEnDelay_dq 01 00 03 00 17 01 01 - 3 - 1 -- 0273
  2863. RecEnDelay_dq 01 01 00 00 17 01 01 - 3 - 1 -- 0273
  2864. RecEnDelay_dq 01 01 01 00 17 01 01 - 3 - 1 -- 0273
  2865. RecEnDelay_dq 01 01 02 00 17 01 01 - 3 - 1 -- 0273
  2866. RecEnDelay_dq 01 01 03 00 17 01 01 - 3 - 1 -- 0273
  2867.  
  2868. Signal CH RK ST HZ 272 136 1 M CC0 CC1 CC2 Vref Dly
  2869. -------------- -- -- -- -- --- --- --- - --- --- --- ---- ----
  2870. RecEnPiCode_dq 01 00 00 00 -- -- 01 - - - - -- 0001
  2871. RecEnPiCode_dq 01 00 01 00 -- -- 01 - - - - -- 0001
  2872. RecEnPiCode_dq 01 00 02 00 -- -- 01 - - - - -- 0001
  2873. RecEnPiCode_dq 01 00 03 00 -- -- 01 - - - - -- 0001
  2874. RecEnPiCode_dq 01 01 00 00 -- -- 01 - - - - -- 0001
  2875. RecEnPiCode_dq 01 01 01 00 -- -- 01 - - - - -- 0001
  2876. RecEnPiCode_dq 01 01 02 00 -- -- 01 - - - - -- 0001
  2877. RecEnPiCode_dq 01 01 03 00 -- -- 01 - - - - -- 0001
  2878. CP 0xA5, Status[0]
  2879. !!!ERROR: FspMemoryInitApi() - Initialization Failure. Error Code 0
  2880. FspMemoryInit returned 0x80000007
  2881. FspMemoryInit returned an error!
  2882.  
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